JP2970376B2 - Method of manufacturing complementary semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention complementary relates manufacturing <br/> manufacturing method of a semiconductor device, without particularly deteriorating the degree of integration and the operation speed of the complementary semiconductor device, complementary semiconductor capable enhance radiation-resistant a method of manufacture of the device.

[0002]

2. Description of the Related Art When a complementary semiconductor device is used as a component for space-borne equipment, there arises a problem that cosmic rays (for example, γ rays) increase static current consumption. This is because the irradiation of γ-rays or the like causes a hole-electron pair to be generated in the field oxide film, and holes having a low mobility are captured at the interface between the silicon substrate and the silicon oxide film and fixed. This fixed positive charge causes the threshold voltage of the parasitic nMOS transistor to decrease, so that the surface of the silicon substrate in contact with the field oxide film is easily inverted and the leak current increases.

Conventionally, as a means for preventing the increase of the leak current, a high impurity concentration region called a guard band is provided near the boundary of the well, thereby preventing the inversion of the substrate surface. FIG.
FIG. 5 is a cross-sectional view of a complementary semiconductor device having a guard band proposed in Japanese Patent Application Publication No. 09664,
(B) is a step sectional view for illustrating the manufacturing method.

First, boron is selectively ion-implanted into an n-type silicon substrate 1a to form a p-type well 3, a silicon nitride film is grown on the entire surface, and a portion of the silicon nitride film to be an element isolation region is removed by etching. I do. Here, by leaving a silicon nitride film also at the boundary between the p-type well 3 serving as an element isolation region and the n-type silicon substrate 1a, this portion is prevented from being oxidized. This remaining portion straddles the p-type well 3 and the n-type silicon substrate 1a.

Next, a selective oxidation (LOCOS method: LOCal Oxidation of Silico) is performed using a silicon nitride film as a mask material.
n) is performed to form the field oxide film 5 to a thickness of about 350 nm. Next, the silicon nitride film on the boundary between the n-type silicon substrate 1a and the p-type well 3 which has not been oxidized earlier is removed, and boron is ion-implanted into this portion to make the impurity concentration higher than that of the p-type well 3. P ⁺ type guard band 7
To form Further, an intermediate oxide film 8 having a thickness of about 150 nm is formed on the p ⁺ guard band 7 by performing thermal oxidation. Next, the silicon nitride film on the element region is removed, and thermal oxidation is performed on the entire surface to form a gate oxide film 9 having a thickness of, for example, 25 nm.
[FIG. 5A].

Next, CVD (Chemical Vapor Depositio)
A gate electrode 10 is formed by depositing a polysilicon layer serving as a gate electrode on the entire surface by the method n) and patterning it into a predetermined shape using a photoresist. At this time, patterning is performed so that the polysilicon layer remains on the p ⁺ -type guard band 7 in the p-type well 3. Further, although not shown, p-type source / drain regions are formed in the n-type silicon substrate 1a and n-type source / drain regions are formed in the p-type well 3 by ion implantation using the gate electrode 10 as a mask [FIG. b)].

Next, an interlayer insulating film 13 of silicon dioxide is formed on the entire surface by CVD, a contact hole is made, an aluminum wiring 14 is formed, and the gate electrodes are connected. A passivation film 15 made of silicon dioxide is formed thereon, and the fabrication of the complementary semiconductor device of the conventional example is completed [FIG. 5 (c)].

In the complementary semiconductor device having such a structure,
Since the thickness of the intermediate thickness oxide film 8 above the p ⁺ -type guard band 7 is formed thinner than the field oxide film 5, the amount of fixed positive charges generated by γ-ray irradiation in this portion is reduced. As a result, the shift of the threshold value in the negative direction is reduced, and the leakage current can be reduced. Further, since the gate electrode 10 remains at least above the p-type well 3 above the intermediate thickness oxide film 8 on the thin p ⁺ -type guard band, the thermal oxide film below the gate electrode 10 In addition, the interlayer insulating film 13 can be formed separately from the CVD oxide film, and crystal defects of the interlayer insulating film 13 which is the CVD oxide film can be reduced. This can further reduce the accumulation of the fixed positive charge.

For the purpose of preventing latch-up, Japanese Patent Application Laid-Open No. 1-308077 discloses that an upper element isolation film of a semiconductor layer portion having a high impurity ion concentration is thicker than a gate oxide film. A complementary semiconductor device thinner than the element isolation oxide film is described. In the method of manufacturing has been complementary semiconductor device according to this publication, the field after oxide film type formed, removing the silicon nitride film of the p ⁺ -type guard band to be formed on the region, to form an intermediate thickness oxide film newly Images A resist film is provided, and boron is ion-implanted using the resist film as a mask to form a p ⁺ -type guard band.

[0010]

SUMMARY OF THE INVENTION The above-mentioned JP-A-Hei 2-3 has been described.
In the conventional example disclosed in 09664 JP, as shown in FIG. 5, p ⁺ -type guard band 7 is n-type silicon substrate 1
It is formed over a and the p-type well 3. However, in order to prevent an increase in static current consumption, at least the p-type well 3
P ⁺ guard band 7 may be formed in a part of
The p ⁺ type guard band 7 is provided on the portion of the type silicon substrate 1a.
There is no need to make. Therefore, according to the prior art, the area of the guard band is unnecessarily widened and the integration is impaired.

In the prior art shown in FIG.
Although the intermediate thickness oxide film 8 is formed by performing thermal oxidation after performing guard band ion implantation, the method of performing thermal oxidation for a long time after introducing impurities at a high concentration as described above requires a substrate. Many defects occur in the inside, causing a cause of an increase in leak. On the other hand, Japanese Patent Application Laid-Open No.
In the prior art described in Japanese Patent Application Laid-Open Publication No. H10-157, the above problem is solved because boron ions for guard band formation are implanted after the formation of the intermediate oxide film. But,
In this case, it is necessary to remove the silicon nitride film on the guard band formation region and perform two photoresist steps for the ion implantation mask for the guard band, resulting in a large number of steps.

Further, in the conventional examples described in the above publications, an oxide film having an intermediate thickness is formed on the entire p ⁺ -type guard band, but the thermal oxide film is more positive than the CVD oxide film. Since the holes are easily captured, the complementary semiconductor device having the above configuration has a drawback that the amount of fixed positive charge accumulated by γ-ray irradiation increases, and the amount of shift of the threshold increases.

[0013]

[0014]

Means for Solving the Problems To solve the above problems,
According to the present invention, a step of forming an n-type well (2) and a p-type well (3) in contact with the same on a semiconductor substrate (1), and forming a silicon nitride film (4) on the entire surface. Removing a silicon nitride film at a place where an element isolation insulating film is to be formed, performing a thermal oxidation to form a thick element isolation film (5) at a portion where the silicon nitride film is removed, and a photoresist film (6). Is selectively formed, and the silicon nitride film on the region where the guard band is to be formed and the region where the gate electrode is to be passed is removed using the photoresist film as a mask, and the photoresist film and the element isolation insulating film are masked. Into the region where both regions are in contact with each other.
forming a p + -type guard band (7) in the p-type well side; and performing thermal oxidation to form a p + -type guard band on the p + -type guard band that is thinner than the element isolation insulating film and thicker than the gate insulating film. forming a third insulating film (8), the remaining p
Excluding the silicon nitride film on the area where the + guard band is to be formed
And introduce p-type impurities to the removed portion of the silicon nitride film.
Forming the remaining part of the p + type guard band
And a method for manufacturing a complementary semiconductor device, comprising:

[0015]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a plan view showing an embodiment of the present invention, and FIGS. 1B and 1C respectively show FIGS.
It is sectional drawing of the AA 'line and BB' line of (a). FIG.
As shown in FIG. 1, an n-type well 2 and a p-type well 3 are formed on a p-type silicon substrate 1, and a p ⁺ -type guard band 7 is formed in a portion of the p-type well 3 near the n-type well 2. ,
7a are formed. Here, p ⁺ type guard band 7
“a” also serves as a diffusion layer for applying a substrate potential to the p-type well 3.

Field oxide films 5 for element isolation are formed on both sides of the p ⁺ -type guard bands 7 and 7a, and the field oxide films 5 are formed on the p ⁺ -type guard bands 7.
An intermediate oxide film 8 which is thinner and thicker than the gate oxide film is formed, and a gate oxide film 9 is formed on the p ⁺ -type guard band 7a. A gate oxide film 9 is formed on the active regions of n-type well 2 and p-type well 3. A gate electrode 10 is provided on each of the wells.
Are formed on both sides of the gate electrode 10 in each well, p ⁺ -type diffusion layers 11 and n ⁺ -type diffusion layers 12 constituting source / drain regions are formed, and p-channel MOS transistors Qp, n A channel MOS transistor Qn is formed. Gate electrode 1 on both wells
Numeral 0 is connected on the field oxide film, and the gate electrode is formed wider on the field oxide film than on the active region for contact with the upper aluminum wiring.

Next, the manufacturing method of this embodiment will be described with reference to FIGS. FIGS. 2 (a) to 2 (c) show FIG.
FIG. 3A is a process cross-sectional view taken along a line AA ′ of FIG.
(A)-(c) is process sectional drawing in the BB 'line | wire cross section of FIG.1 (a). Phosphorus is added to the p-type silicon semiconductor substrate 1 doped with boron at about 1 × 10 ¹⁵ cm ⁻³ for 10 ¹⁶ cm.
^{-3 is} doped into n-type well 2 and boron is added to 10 ¹⁶
A p-type well 3 is formed by doping about cm ⁻³ so that both are in contact with each other. A silicon nitride film 4 having a thickness of about 120 nm
Then, the silicon nitride film 4 in the element isolation region forming portion is selectively removed. Here, the silicon nitride film 4 is also left near the boundary between the n-type well 2 and the p-type well 3 serving as an element isolation region, thereby preventing this portion from being oxidized. The remaining portion is set in the p-type well 3 so as not to enter the n-type well 2. Next, selective oxidation is performed using the silicon nitride film 4 as a mask material to form a field oxide film 5 having a thickness of about 450 nm [FIG.
(A), FIG. 3 (a)].

Next, a photoresist is applied, and exposure and development are performed to form a photoresist film 6 exposing the silicon nitride film 4 on the area where the guard band is to be formed and on the area where the gate electrode is to be passed. Using this as a mask, the silicon nitride film is removed. Then, using the photoresist film 6 and the field oxide film 5 as a mask, boron is ion-implanted at an energy of 30 keV and a dose of about 5 × 10 ¹⁵ cm ⁻² to form a p-type well 3. Impurity concentration (10 ²⁰ c
m ⁻³ ) p ⁺ guard band 7 is formed [FIG.
(B), FIG. 3 (b)].

After the photoresist film 6 is peeled off, thermal oxidation is performed to form an intermediate oxide film 8 having a thickness of about 200 nm on the portion where the silicon nitride film has been removed (that is, on the p ⁺ -type guard band 7 formation region). [FIG. 2 (c), FIG. 3 (c)]. Next, after removing the remaining silicon nitride film 4 and removing the underlying oxide film thereunder, thermal oxidation is performed to form a gate oxide film 9 having a thickness of about 20 nm. At this time, the gate oxide film 9 is also formed on the region where the p ⁺ -type guard band 7a is to be formed.

Next, a polycide layer for forming a gate electrode is deposited on the entire surface by CVD and sputtering, and photolithography and RIE (reactive ion etching) are performed.
The gate electrode 10 is formed by patterning into a predetermined shape by the method g). Subsequently, a region other than the active region of the p-type well 3 is masked with a photoresist, phosphorus is ion-implanted to form an n ⁺ -type diffusion layer 12, and an n-channel MOS transistor Qn is formed on the p-type well 3. I do. Similarly, the active region of the p-type well 3 is masked with a photoresist, boron ions are implanted to form ap ⁺ -type diffusion layer 11, and a p-channel MOS transistor Qp is formed on the n-type well 2. A p ⁺ -type guard band 7a also serving as a diffusion layer for fixing the potential of the well is formed in a region on the p-type well 3 interposed between the field oxide films 5 [FIG.
(A), (b), (c)].

Thereafter, although not shown, according to a standard method, silicon dioxide is deposited on the entire surface by a CVD method to form an interlayer insulating film, a contact hole is formed in the interlayer insulating film, and aluminum is deposited by, for example, a sputtering method. Is patterned to form an aluminum wiring. Finally, a passivation film made of silicon dioxide or the like is formed on the entire surface to complete the manufacture of the complementary semiconductor device of this embodiment.

In the complementary semiconductor device formed as described above, the p ⁺ -type guard band is formed only in the p-type well 3, so that it has a structure suitable for high density without occupying an extra space. It has become. Further, the silicon oxide film on the p ⁺ -type guard band is a thin oxide film of the gate oxide film in most regions, and the intermediate thickness oxide film 8 is formed only in a part. Therefore, introduction of defects into the high impurity concentration region due to thermal oxidation can be reduced, and the amount of fixed positive charges accumulated in the oxide film can be reduced to prevent an increase in leak current. In the above manufacturing method, the step of selectively removing the silicon nitride film 4 on the p ⁺ -type guard band 7 formation region and the ion implantation step for forming the p ⁺ -type guard band 7 are performed by one photolithography. Since the semiconductor device according to the present embodiment can be implemented by steps, the semiconductor device of the present embodiment can be manufactured with less man-hours.

FIG. 4 (a) is a plan view showing a reference example of the present invention, and FIGS. 4 (b) and 4 (c) are lines AA 'and BB' in FIG. 4 (a), respectively. FIG. 4, since the portion corresponding to those of the previous embodiment shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted, in the present embodiment, p ⁺ -type guard band 7 is formed by one ion implantation, and an intermediate oxide film 8 is entirely formed thereon. In the semiconductor device of this reference example, in the step of selectively removing the silicon nitride film after the formation of the field oxide film 5, all the silicon nitride film in the region where the p ⁺ -type guard band is to be formed is removed, and boron ions are implanted into the portion. To form a p ⁺ -type guard band, and then forming an intermediate-thickness oxide film 8 by thermal oxidation at that portion.

The preferred embodiment has been described above.
The present invention is not limited to these examples, and various changes can be made without departing from the scope of the invention. For example, although the p-type silicon substrate is used in the embodiment, an n-type silicon substrate or an epitaxial substrate may be used. In the embodiment, the case of the twin well system has been described, but the present invention can be similarly applied to the case of the n-type well and the p-type well.
Further, instead of polycide, n
Type or p-type polysilicon can be used.

[0025]

As described above, according to the present invention, the width of the p ⁺ -type guard band is reduced to a necessary minimum, so that the p ⁺ -type guard band is integrated by the width of the p ⁺ -type guard band in the conventional n-type well. And the parasitic gate capacitance can be reduced by the area. Further, since the silicon oxide film having an intermediate film thickness on the p ⁺ -type guard band is limited only to the portion passing through the gate electrode and the other region is a thin gate oxide film, the thermal oxidation process after forming the high concentration region is shortened. Generation of defects in the substrate can be suppressed, and accumulation of fixed positive charges on the p ⁺ -type guard band can be suppressed to prevent an increase in leak current. In addition, since the removal of the silicon nitride film on the region where the p ⁺ -type guard band is to be formed and the ion implantation for the p ⁺ -type guard band are performed using one photoresist mask, the radiation resistance is reduced by a smaller number of steps. A highly complementary semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view illustrating one embodiment of the present invention.

FIG. 2 is a process cross-sectional view for explaining a manufacturing method according to one embodiment of the present invention.

FIG. 3 is a process cross-sectional view for explaining a manufacturing method according to one embodiment of the present invention.

FIG. 4 is a plan view and a cross-sectional view illustrating a reference example of the present invention.

FIG. 5 is a process sectional view for explaining the manufacturing method of the conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 p-type silicon substrate 1 a n-type silicon substrate 2 n-type well 3 p-type well 4 silicon nitride film 5 field oxide film 6 photoresist film 7, 7 ap ⁺ guard band 8 intermediate oxide film 9 gate oxide film 10 gate Electrode 11 p ⁺ type diffusion layer 12 n ⁺ type diffusion layer 13 interlayer insulating film 14 aluminum wiring 15 passivation film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8234-21/8238 H01L 21/8249 H01L 27/08 H01L 27/088-27/092

Claims (1)

(57) [Claims] A step of providing a first conductivity type region and a second conductivity type region in contact with the semiconductor substrate on a semiconductor substrate; forming a silicon nitride film on the entire surface; and forming a silicon nitride film at a location where an element isolation insulating film is to be formed. Removing, thermally oxidizing to form a thick device isolation film on the removed portion of the silicon nitride film, and selectively forming a photoresist film to form a guard band using the photoresist film as a mask. Removing the silicon nitride film on the region and the region where the gate electrode is to pass, selectively introducing a second conductivity type impurity using the photoresist film and the element isolation insulating film as a mask, and contacting the two regions. High impurity concentration second
Forming a part of a conductive type guard band; and performing a third thermal oxidation on the high impurity concentration second conductive type guard band, the third thickness being smaller than the thickness of the element isolation insulating film and being larger than the thickness of the gate insulating film. Forming the insulating film, removing the remaining silicon nitride film on the region where the high impurity concentration second conductivity type guard band is to be formed, and introducing the high impurity concentration second conductivity type impurity into the removed portion of the silicon nitride film. Forming a high impurity concentration second conductivity type guard band in the remaining portion.