JPH09107084A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce manufacturing processes by forming a semiconductor region which forms one electrode of an information storage capacitive element of a dynamic memory cell and a semiconductor region connected to a drain region of a non-volatile memory cell in the same manufacturing process. SOLUTION: A process for forming a semiconductor region 7 which forms a lower electrode of an information storage capacitive element C of a memory cell DM and a process for forming a semiconductor region 7 of a field-effect transistor Qf of a memory cell FM are performed in a same manufacturing process, and thereafter, a process for forming dielectric film 8 of the information storage capacitive element C and a process for forming a tunnel insulating film 8 of the field-effect transistor Qf are performed in the same manufacturing process, thereby the semiconductor region 7 and the tunnel insulating film 8 of the field-effect transistor Qf can be formed in a process wherein the semiconductor region 7 and the dielectric film 8 of the information storage capacitive element C are formed. As a result, the manufacturing processes of a semiconductor integrated circuit device can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having a dynamic random access memory and a non-volatile memory.

[0002]

BACKGROUND OF THE INVENTION Semiconductor integrated circuit device having a built-in microcomputer, RAM as a memory unit of the microcomputer (R andom A ccess M emory)
And has a ROM (R ead O nly M emory ). The RAM is mounted S (S Tatic) RAM, the memory cell (memory element) of the six MOS
It is composed of a FET (6MOS structure). The ROM mask ROM, EP (E rasable P rog
rammable) ROM or EEP (E lectri
cally E rasable P rogrammab
le) ROM is installed. EEPROM is FLO
TOX (Flo ating Gate T unnel
Ox ide) memory cell structures are used.

The semiconductor integrated circuit device having the above-described structure has six SRAM memory cells used as RAM.
Since it has a MOS structure, the area of the memory cell is increased and the degree of integration is reduced. Therefore, as a RAM of this type of semiconductor integrated circuit device, D (Dynamic) is used instead of SRAM.
ic) There is a proposal to use RAM. For example, Nikkei McGraw-Hill Inc., Nikkei Microdevice, July 1987, pages 71 to 73. The DRAM of the proposed semiconductor integrated circuit device has memory cells for memory cell selection M
It is composed of a series circuit of an OSFET and an information storage capacitive element. The information storage capacitor has a so-called planar structure in which an n-type semiconductor region (lower electrode), a dielectric film, and a plate electrode (upper electrode) formed on the main surface of the semiconductor substrate are sequentially stacked.

Since this semiconductor integrated circuit device has a small number of DRAM memory cell elements, it is characterized in that the memory cell area can be reduced and the degree of integration can be improved.

The semiconductor integrated circuit device is an EEP
Since the DRAM memory cell is formed by utilizing a part of the manufacturing process of the ROM FLOTOX structure memory cell, there is a feature that the manufacturing process can be reduced. This semiconductor integrated circuit device has a DRAM, an EEPR as described above.
An OM and a MISFET forming a peripheral circuit are mounted, and the manufacturing method of these elements is as follows.

First, a gate insulating film is formed on the main surface of the semiconductor substrate in the floating gate electrode formation region of the memory cell having the FLOTOX structure of the EEPROM.

Next, a part of the gate insulating film is removed,
A tunnel silicon oxide film having a thickness smaller than that of the gate insulating film is formed.

Next, a floating gate electrode is formed on the gate insulating film and the tunnel silicon oxide film.

Next, a gate insulating film is formed on the floating gate electrode. By utilizing this process and the same manufacturing process as that process, the dielectric film (silicon oxide film) of the information storage capacitive element of the memory cell of the DRAM and the gate insulating film of the MISFET of the peripheral circuit are formed.

Next, a control gate electrode is formed on the floating gate electrode of the FLOTOX structure memory cell with a gate insulating film interposed. By using this process, a plate electrode (upper electrode) is formed on the dielectric film of the information storage capacitor element of the DRAM memory cell and a gate electrode is formed on the gate insulating film of the MISFET of the peripheral circuit by the same manufacturing process as that process. Form.

[0011]

As described above, the dielectric film of the information storage capacitor is formed of the gate insulating film between the floating gate electrode and the control gate electrode of the memory cell having the FLOTOX structure and the peripheral circuit. MISF
It is formed in the same manufacturing process as the gate insulating film of ET. Since a relatively high voltage required for the information writing operation, reading operation and erasing operation is applied to the control gate electrode of the FLOTOX structure memory cell, the gate insulating film below the control gate electrode is formed to have a small film thickness. I can't. Moreover, since an operating voltage of about 5 [V] is usually applied to the gate electrode of the MISFET of the peripheral circuit,
The gate insulating film below the gate electrode cannot be formed with a small thickness. Therefore, the dielectric film of the information storage capacitor formed in the same manufacturing process as the gate insulating film is formed to have substantially the same thickness as the gate insulating film. Therefore, the amount of charge accumulated in the information storage capacitor element of the memory cell of the DRAM decreases, and the area occupied by the information storage dose element increases in order to increase the charge amount. As a result,
Since the occupied area of the RAM increases, the integration degree of the semiconductor integrated circuit device decreases.

Further, in order to increase the charge amount of the information storage capacitive element of the memory cell of the DRAM, FLOTO is used.
It is necessary to form a dielectric film by a manufacturing process different from that of the gate insulating film having the X structure and the gate insulating film of MISSET of the peripheral circuit. Therefore, in order to improve the degree of integration, the number of manufacturing steps of the semiconductor integrated circuit device is increased.

An object of the present invention is to provide a technique capable of improving the degree of integration in a semiconductor integrated circuit device having a dynamic memory (DRAM) and a non-volatile memory.

Another object of the present invention is to achieve the above object by reducing the area of the dynamic memory element and optimizing the characteristics of the nonvolatile memory element and the elements of the peripheral circuit. To provide the technology.

Another object of the present invention is to provide a technique capable of reducing the manufacturing process of the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In a method of manufacturing a semiconductor integrated circuit device including a dynamic memory element having a planar structure information storage capacity element and a FLOTOX structure non-volatile storage element, an information storage capacity element of the dynamic type storage element is provided. A semiconductor region forming one of the electrodes and a semiconductor region connected to the drain region of the nonvolatile memory element are formed in the same manufacturing step, and thereafter, the dielectric film of the information storage capacitor and the nonvolatile layer are formed. The tunnel insulating film of the memory element is formed in the same manufacturing process.

According to the above-mentioned means, the semiconductor region connected to the drain region of the nonvolatile memory element and the tunnel insulation in the step of forming the semiconductor region forming one electrode of the information storage capacitor and the dielectric film. Since the film can be formed, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the semiconductor region and the tunnel insulating film. Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device containing a microcomputer.

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment I) A semiconductor integrated circuit device incorporating a microcomputer according to a first embodiment of the present invention is shown in FIG.
It is shown in FIG.

As shown in FIGS. 1 (a) and 1 (b),
The semiconductor integrated circuit device is composed of one common p-type semiconductor substrate 1 made of single crystal silicon. That is, although the semiconductor substrate 1 is illustrated separately in FIG. 1A and FIG. 1B in the drawing, it is actually formed integrally.

On the main surface of the semiconductor substrate 1, as shown in FIG.
Storage elements of AM and ROM are configured. The RAM is composed of a DRAM, and its memory cell (dynamic memory element) DM is described. ROM is EE
A PROM, an EPROM, and a mask ROM are configured, and a memory cell (nonvolatile memory element) FM of the FLOTOX structure of the EEPROM and a memory cell (nonvolatile memory element) EM of the EPROM are described. Since the memory cell of the mask ROM has substantially the same structure as the element (n-channel MISFET) shown in FIG. 1B, it is not shown here and its explanation is omitted. Also,
On the main surface of the other region of the semiconductor substrate 1, as shown in FIG. 1B, a complementary MISFET (CM
OS) is configured. CMOS is an n-channel MI
SFET Qn ₁ , Qn ₂ , p-channel MISFET Q
It is configured by combining n ₁ and Qn ₂ . Each of the p-channel MISFETs Qp ₁ and Qn ₂ is formed on the main surface of the n-type well region 2 provided on the main surface portion of the semiconductor substrate 1.

The semiconductor element formed on the main surface of the semiconductor substrate 1 is electrically isolated from other regions by the field insulating film 3 and the p-type channel stopper region 4. The semiconductor element formed on the main surface of the well region 2 is the field region 2
The semiconductor element formed on the main surface of is electrically isolated from other regions by the field insulating film 3. The field insulating film 3 is formed of a silicon oxide film in which main surfaces of the semiconductor substrate 1 and the well region 2 are selectively oxidized. The channel stopper region 4 is located on the main surface of the semiconductor substrate 1 and below the field insulating film 3.

The memory cell DM of the DRAM is shown in FIG.
As shown on the left side of FIG.
It is composed of a series circuit of ds and an information storage capacitive element C.

The information storage capacitor C is constructed by sequentially stacking an n-type semiconductor region (lower electrode) 7, a dielectric film 8 and a plate electrode (upper electrode) 9. The information storage capacitive element C has a so-called planar structure (MOS structure).

The semiconductor region 7 is formed on the main surface portion of the semiconductor substrate 1.

The dielectric film 8 is formed of a silicon oxide film obtained by oxidizing the main surface of the semiconductor region 7 (semiconductor substrate 1). The dielectric film 8 has substantially the same film thickness as the tunnel insulating film (silicon oxide film) 8 of the memory cell FM of the EEPROM described later,
For example, it is formed with a thin film thickness of about 100 [Å].
Each of the dielectric film 8 and the tunnel insulating film 8 has a memory cell selection MISFET Qds and a peripheral circuit MISFET.
It is formed to have a smaller film thickness than the gate insulating film 6 or 12 of Qn ₁ , Qn ₂ , Qn ₁ , and Qn ₂ . That is, since the dielectric film 8 of the information storage capacitive element C is formed to be thin, it is configured so that the charge storage amount of the information storage capacitive element C can be increased and the area of the memory cell DM can be reduced. There is.

The plate electrode 9 is formed on the dielectric film 8. The plate electrode 9 is formed of, for example, a polycrystalline silicon film into which an impurity (P, As or B) that reduces the resistance value is introduced. The plate electrode 9 is, for example, 3000-4
It is formed with a film thickness of about 000 [Å]. This plate electrode 9 is formed of the first-layer gate electrode material in the manufacturing process. An interlayer insulating film 10 is provided on the surface of the plate electrode 9.

The memory cell selection MISFET Qds is
Mainly, the semiconductor substrate 1, the gate insulating film 12, the gate electrode 1
3, a pair of n-type semiconductor regions 15 and a pair of n + -type semiconductor regions 19 serving as a source region and a drain region. That is, the memory cell selecting MISFET Qds
Is an n-channel MISFET.

The semiconductor substrate 1 is used as a channel forming region.

The gate insulating film 12 is formed of a silicon oxide film obtained by oxidizing the main surface portion of the semiconductor substrate 1. As described above, the gate insulating film 12 is formed to be thicker than the dielectric film 8 of the information storage capacitive element C, for example, a film thickness of about 250 [Å]. That is, the gate insulating film 12 can secure the dielectric strength voltage between the semiconductor substrate 1 and the gate electrode 13 in a normal operation range (for example, the voltage between the semiconductor substrate 1 and the gate electrode 13 is 5 [V]). Is configured.

The gate electrode 13 is formed on the gate insulating film 12. The gate electrode 13 is formed of, for example, a polycrystalline silicon film into which an impurity that reduces the resistance value is introduced. The gate electrode 13 is, for example, 3000 to 4000 [Å]
It is formed with a film thickness of about. The gate electrode 13 is formed of the second-layer gate electrode material in the manufacturing process. In order to reduce the resistance value of the gate electrode 13, a single-layer refractory metal film or refractory metal silicide film, or a refractory metal film or refractory metal silicide film is provided on a polycrystalline silicon film. It may be formed of a composite film. Further, the gate electrode 13 is formed integrally with the word line (WL) 13.

The low impurity concentration n-type semiconductor region 15 is provided between the high impurity concentration n + -type semiconductor region 19 and the channel formation region. This semiconductor region 15 is a so-called L
Constitute a MISFET of the DD (L ightly D oped D rain ) structure. The semiconductor region 15 is self-aligned with the gate electrode 13. The high impurity concentration n + type semiconductor region 19 is configured to be self-aligned with the gate electrode 13 with the sidewall spacer 18 interposed.

This memory cell selecting MISFET Qds
One semiconductor region 19 is integrally configured (connected) with the semiconductor region 7 which is the lower electrode of the information storage capacitive element C. In the other semiconductor region 19 of the memory cell selecting MISFET Qds, the connection hole 2 formed in the interlayer insulating film 21 is formed.
The wiring 23 is connected through 2. The wiring 23 is used as a complementary data line (DL). The wiring 23 is formed of, for example, aluminum, Si, or an aluminum alloy to which Cu is added. Si reduces the alloy spike phenomenon. Cu reduces stress migration.

Although not shown, a final passivation film is formed on the memory cell DM thus constructed.

The memory cell FM of the EEPROM is shown in FIG.
As shown in the central portion of (a), a field effect transistor Qf having a FLOTOX structure and a memory cell selecting MISFET.
It is composed of a series circuit with Qfs. That is, the memory cell FM has a two-transistor structure.

The field effect transistor Qf is configured to have information "1" or "0". The field effect transistor Qf mainly includes a pair of semiconductor substrate 1, semiconductor region 7, gate insulating film 6, tunnel insulating film 8, floating gate electrode 9, gate insulating film 11, control gate electrode 13, source region and drain region. It is composed of an n-type semiconductor region 15 and a pair of n + -type semiconductor regions 19.

The semiconductor substrate 1 is used as a channel forming region.

The semiconductor region 7 is formed integrally with the semiconductor region 19 used as the drain region, and is extended to the main surface portion of the semiconductor substrate 1 below the tunnel insulating film 8.

The gate insulating film 6 is formed of a silicon oxide film formed by oxidizing the main surface of the semiconductor substrate 1. The gate insulating film 6 is formed to have a thickness larger than that of the dielectric film 8 of the information storage capacitive element C, for example, about 500 [Å]. That is, the gate insulating film 6 is formed in the semiconductor region 7 and the floating gate electrode in the normal information writing operation and erasing operation range (for example, the voltage between the semiconductor region 7 and the control gate electrode 13 is 17 to 20 [V]). It is configured so that a withstand voltage with respect to 9 can be secured.

The tunnel insulating film 8 is formed of a silicon oxide film obtained by removing a part of the gate insulating film 6 below the floating gate electrode 9 and oxidizing the main surface of the semiconductor substrate 1 in the removed part. Like the dielectric film 8, the tunnel insulating film 8 is formed to have a thin film thickness, for example, a film thickness of about 100 [Å]. Thus, the thin tunnel insulating film 8
Since the tunnel current amount per unit area can be increased, the time required for the information writing operation and the erasing operation of the memory cell FM can be shortened.

The floating gate electrode 9 is made of the first-layer gate electrode material, like the plate electrode 9 of the information storage capacitive element C.

The gate insulating film 11 is formed of a silicon oxide film obtained by oxidizing the surface of the floating gate electrode 9.
The gate insulating film 11 is configured so as to ensure a withstand voltage between the floating gate electrode 9 and the control gate electrode 13 in the information writing operation, reading operation and erasing operation ranges. The gate insulating film 11 is, for example, 30
It is formed with a relatively thick film thickness of about 0 to 400 [Å].

The control gate electrode 13 is provided on the gate insulating film 11. Control gate electrode 1
3 is an MI for selecting a memory cell DM memory cell DM
Like the gate electrode 13 of the SFET Qds, it is made of the second-layer gate electrode material.

The field effect transistor Qf has an LDD structure.

The memory cell selecting MISFET Qfs is
Basically, it is composed of a semiconductor substrate 1, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 15 which are source and drain regions, and a pair of n + -type semiconductor regions 19.

The gate insulating film 6 and the gate electrode 9 are respectively
Each of the field effect transistors Qf has substantially the same manufacturing process. MISFET for memory cell selection
Qfs has an LDD structure. Semiconductor region 1 which is a source region of MISFET Qfs for memory cell selection
9 is formed integrally with the semiconductor region 19 which is the drain region of the field effect transistor Qf.

A shunt wiring 13 is provided on the gate electrode 9 of the memory cell selecting MISFET Qfs with an interlayer insulating film 11 interposed. This shunt wiring 13
Is the interlayer insulating film 11 for each memory cell selection MISFET Qfs or every predetermined number in the extending direction of the word line.
It is connected to the gate electrode 9 through a connection hole (not shown) formed in. That is, the shunt wiring 13 is
It is possible to reduce the resistance value of the gate electrode 9 of the memory cell selecting MISFET Qfs and the word line formed integrally with the gate electrode 9. In addition, MISFETQ for memory cell selection
Like the field effect transistor Qf, fs has a two-layer gate structure including the gate electrode 9 and the shunt wiring 13. In this way, the field effect transistor Q
If each of the memory cell selection MISFET Qfs is constructed with a two-layer gate structure, the inter-gate dimension between the two can be defined only by the processing dimension without requiring a mask alignment margin dimension in the manufacturing process. That is, the space between the field effect transistor Qf and the memory cell selecting MISFET fs can be reduced, and the area occupied by the memory cell FM can be reduced.

Field effect transistor Q of memory cell FM
A wiring 23 is connected to the semiconductor region 19 which is the source region of f through a connection hole 22. This wiring 23 is used as a source wiring (SL). A wiring 23 is connected through a connection hole 22 to the semiconductor region 19 which is the drain region of the memory cell selecting MISFET Qfs of the memory cell FM. The wiring 23 is used as a data line (DL).

The memory cell EM of the EPROM is shown in FIG.
As shown on the right side of (a), it is composed of a field effect transistor. The memory cell EM mainly includes a semiconductor substrate 1, a gate insulating film 6, a floating gate electrode 9, a gate insulating film 11, a control gate electrode 13, and a pair of n-type semiconductor regions 16 which are a source region and a drain region.
And a pair of n + type semiconductor regions 19.

This memory cell EM is the same as the EEPROM.
Like the field effect transistor Qf of the memory cell FM, it has a two-layer gate structure and an LDD structure.
The n-type semiconductor region 16 having a low impurity concentration of the field effect transistor, which is the memory cell EM, is the M of the LDD structure.
N of low impurity concentration such as ISFET Qds, Qf, Qfs
The impurity concentration is higher than that of the type semiconductor region 15. Further, the semiconductor region 16 is formed by another MISFET Qd.
The impurity concentration of s, Qf, Q, s, etc. is lower than that of the n + type semiconductor region 19 having a high impurity concentration. The semiconductor region 16 is configured to increase the electric field strength in the vicinity of the drain region of the field effect transistor and increase the amount of hot carriers generated. That is, the semiconductor region 16 increases the amount of hot electrons injected into the floating gate electrode 9 of the memory cell EM,
The information writing operation time is shortened. Further, the semiconductor region 16 is configured to reduce the resistance value of the source region and the drain region near the channel formation region, reduce the transfer conductance, and shorten the information read time.

A wiring 23 is connected through a connection hole 22 to the semiconductor region 19 which is the source region of the field effect transistor which is the memory cell EM. The wiring 23 is used as a source wiring (SL). A connection hole 22 is formed in the semiconductor region 19 which is the drain region of the field effect transistor.
The wiring 23 is connected through. The wiring 23 is used as a data line (DL).

The peripheral circuit CMOS, that is, n-channel MISFETs Qn ₁ , Qn ₂ and p-channel MISFET Q
Each of p ₁ and Qp ₂ is configured as shown in FIG. 1B.

The n-channel MISFET Qn ₁ is composed of a semiconductor substrate 1, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 15 which are source and drain regions, and a pair of n + -type semiconductor regions 19. .

The n-channel MISFET Qn ₂ is composed of a semiconductor substrate 1, a gate insulating film 12, a gate electrode 13, a pair of n-type semiconductor regions 15 which are source and drain regions, and a pair of n + -type semiconductor regions 19. .

The p-channel MISFET Qp ₁ is composed of a well region 2, a gate insulating film 6, a gate electrode 9, a pair of p-type semiconductor regions 17 which are source and drain regions, and a pair of p + -type semiconductor regions 20. .

The p-channel MISFET Qp ₂ is composed of a well region 2, a gate insulating film 12, a gate electrode 13, a pair of p-type semiconductor regions 17 which are source and drain regions, and a pair of p + -type semiconductor regions 20. .

Each of the n-channel MISFET Qn ₁ and the p-channel MISFET Qp ₁ has the memory cell F.
The gate insulating film 6 and the gate electrode 9 are formed by the same manufacturing process as that of the gate insulating film 6 of the M field effect transistor Qf and the like, and the floating gate electrode 9. That is, in each of the n-channel MISFET Qn ₁ and the p-channel MISFET Qp ₁ , the gate electrode 9 is formed of the first-layer gate electrode material.

On the other hand, the n-channel MISFETQ
In each of the n ₂ and p channel MISFETs Qp ₂ , the gate insulating film 12 and the gate electrode 13 are formed by the same structure process as that of the gate insulating film 12 and the gate electrode 13 of the memory cell selecting MISFET Qds of the memory cell DM. ing. That is, the n-channel MISFETQ
In each of the n ₂ and p channel MISFETQp ₂ , the gate electrode 13 is formed of the second layer gate electrode material.

The MISFETs Qn ₁ , Qn ₂ , Qp ₁ ,
Each of Qp ₂ has an LDD structure. A wiring 23 is connected to each semiconductor region 19 of the n-channel MISFETs Qn ₁ and Qn ₂ . p-channel MISFET
A wiring 23 is connected to each semiconductor region 20 of Qp ₁ and Qp ₂ .

Thus, the DARM memory cell DM
(Dynamic memory element), memory cell FM (nonvolatile memory element) of FLOTOX structure, and MIS of peripheral circuit
In a semiconductor integrated circuit device including FETs (Qn ₁ , Qn ₂ , Qp ₁ , Qp ₂ ), the dielectric film 8 of the information storage capacitor C of the memory cell DM and the field effect transistor Qf of the memory cell FM are The tunnel insulating film 8 is replaced with the M
By forming the film thickness thinner than the gate insulating film 6 or 12 of the ISFET, the charge storage amount of the information storage capacitive element C can be improved and the area occupied by the memory cell DM can be reduced, so that the integration of the DRAM can be reduced. Since the tunnel current that can flow in the tunnel insulating film 8 can be increased, the memory cell F of the EEPROM can be increased.
It is possible to shorten the information writing time of M, and
Since the withstand voltage of the gate insulating film 6 or 12 of the ISFET can be improved, the electrical reliability can be improved.

Next, a method of manufacturing the semiconductor integrated circuit device will be described with reference to FIGS. 2A and 2B to 9A and 9B. ) For a brief explanation.

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, the p channel MI of the peripheral circuit CMOS
In the SFET Qp ₁ and Qp ₂ formation region, an n-type well region 2 is formed in the main surface portion of the semiconductor substrate 1. Also, n ~
The n-channel MISFE of the CMOS of the whole main surface of the semiconductor substrate 1 different from the well region 2 or the peripheral circuit
A p-type well region may be formed in the TQn ₁ and Qn ₂ forming regions.

Next, the field insulating film 3 is formed on the main surfaces of the semiconductor substrate 1 and the well region 2 between the semiconductor element formation regions. The field insulating film 3 is formed of a silicon oxide film in which the respective main surfaces of the semiconductor substrate 1 and the well region 2 are selectively oxidized. The p-type channel stopper region 4 is formed under the field insulating film 3 on the main surface of the semiconductor substrate 1 by substantially the same manufacturing process as the process of forming the field insulating film 3.

Next, as shown in FIGS. 2A and 2B, a gate insulating film 6A is formed on the main surfaces of the semiconductor substrate 1 and the well region 2 in the semiconductor element forming region. This gate insulating film 6A is a field effect transistor or M
Used as a part of the gate insulating film of ISFET. The gate insulating film 6A is formed of a silicon oxide film obtained by oxidizing the main surfaces of the semiconductor substrate 1 and the well region 2.

Next, as shown in FIGS. 3 (a) and 3 (b), in the information storage capacitive element C forming region of the memory cell DM of the DRAM and the field effect transistor Qf forming region of the memory cell FM of the EEPROM. The n-type semiconductor region 7 is formed in the main surface portion of the semiconductor substrate 1 in the same manufacturing process.
The semiconductor region 7 forms a lower electrode (one electrode) in a region where the information storage capacitor C is formed. Further, the semiconductor region 7 is formed in the field effect transistor Qf formation region so that a tunnel current flows between the drain region (19) and the floating gate electrode (9). The semiconductor region 7 is formed by introducing an n-type impurity such as As or P into the main surface portion of the semiconductor substrate 1 through the gate insulating film 6A. The semiconductor region 7 has, for example, 10 ¹⁵ [atoms]
/ Cm ² ] of As is introduced by ion implantation with an energy of about 60 to 100 [KeV]. When introducing this n-type impurity, a photoresist film (not shown) is used as a mask for introduction.

Next, the gate insulating film 6A is selectively removed in the information storage capacitive element C forming region of the DRAM memory cell DM and the field effect transistor Qf forming region of the EEPROM memory cell FM. The gate insulating film 6A in the field effect transistor Qf forming region removes a part under the floating gate electrode (9) forming region.

Next, as shown in FIGS. 4A and 4B, in the region where the gate insulating film 6A is removed,
A dielectric film 8 and a tunnel insulating film 8 are formed on the main surface portion of the semiconductor substrate 1 (actually, the semiconductor region 7) in the same manufacturing process. The dielectric film 8 is formed on the main surface of the semiconductor region 7 in the information storage capacitor C forming region. The tunnel insulating film 8 is formed on the main surface of the semiconductor region 7 in the field effect transistor Qf forming region. Each of the dielectric film 8 and the tunnel insulating film 8 is formed of a silicon oxide film obtained by oxidizing the main surface of the semiconductor region 7, and has a thin film thickness as described above. By the process of forming the dielectric film 8 and the tunnel insulating film 8, FIG.
As shown in FIGS. 4A and 4B, the gate insulating film 6A is formed.
Are grown to form the gate insulating film 6. The gate insulating film 6 is formed to have a large film thickness as described above because the film thickness of the dielectric film 8 or the tunnel insulating film 8 is added to the gate insulating film 6A.

Next, the tunnel insulating film 8 is formed on the dielectric film 8.
A first gate electrode layer 9 is deposited on the entire surface of the substrate including the upper portion and the gate insulating film 6 and the like. The first gate electrode layer 9 is formed of, for example, a polycrystalline silicon film deposited by CVD. After the polycrystalline silicon film is deposited, an n-type impurity, for example, P for reducing the resistance value is introduced (ion implantation or thermal diffusion).

Next, the first gate electrode layer 9 is subjected to a predetermined patterning, and the pattern is shown in FIGS. 5 (a) and 5 (b).
As shown in, the plate electrode 9, the floating gate electrode 9, and the gate electrode 9 are formed in the same manufacturing process. The plate electrode 9 is formed on the dielectric film 8 in the information storage capacitive element C forming region of the DRAM memory cell DM. The floating gate electrode 9 is EEPR
It is formed on the tunnel insulating film 8 and the gate insulating film 6 in the field effect transistor Qf forming region of the OM and on the gate insulating film 6 in the field effect transistor forming region of the EPROM, respectively. Each floating gate electrode 9 is patterned only in the gate width direction. The gate electrode 9 is
They are formed on the gate insulating film 6 in the memory cell selecting MISFET Qfs forming region of the EEPROM, the CMOS n-channel MISFET Qn ₁ forming region, and the p-channel MISFET Qp ₁ forming region, respectively. By the step of forming the plate electrode 9, the semiconductor region (lower electrode) 7, the dielectric film 8, and the plate electrode (upper electrode) 9 are sequentially superposed on each other, and the information storage capacitive element C of the memory cell DM of the DRAM is formed. Is completed.

Next, an insulating film is formed to cover the plate electrode 9, the floating gate electrode 9 and the gate electrode 9. This insulating film is formed of a silicon oxide film in which the respective surfaces of the plate electrode 9, the floating gate electrode 9, and the gate electrode 9 are oxidized.

Next, with the insulating film on the plate electrode 9 left, the insulating film on the floating gate electrode 9 and the gate electrode 9 and the first gate electrode layer 9 are formed. The gate insulating film 6 in the non-existing region is selectively removed.

Next, the entire surface of the substrate is subjected to an oxidation treatment, and the result shown in FIG.
As shown in FIGS. 6A and 6B, the interlayer insulating film 10 is formed on the surface of the plate electrode 9, the gate insulating film 11 is formed on the surface of the floating gate electrode 9, the insulating film 11 is formed on the surface of the gate electrode 9, and the semiconductor substrate 1 is formed. The gate insulating film 12 is formed on the main surface of the well region 2 and the main surface of the well region 2. The interlayer insulating film 10, the gate insulating film 11, the insulating film 11, and the gate insulating film 12 are formed by the same manufacturing process. The interlayer insulating film 10 is formed with a thick film thickness of, for example, about 2000 to 3000 [Å]. Each of the gate insulating film 11 and the insulating film 11 is formed to have a film thickness of, for example, about 300 to 400 [Å]. The gate insulating film 12 is formed with a film thickness of, for example, about 250 [Å]. It should be noted that the interlayer insulating film 10 on the surface of the plate electrode 9 basically insulates the plate electrode 9 and the word line 13 extending above the plate electrode 9, and therefore is preferably thick, but like the gate insulating film 11 and the like. Formed with a thin film thickness,
You may reduce a manufacturing process.

Next, the gate insulating film 1 is formed on the interlayer insulating film 10.
A second gate electrode layer 13 is deposited on the entire surface of the substrate including the first layer, the insulating film 11, and the gate insulating film 12. The second gate electrode layer 13 is formed of, for example, a polycrystalline silicon film deposited by CVD. An n-type impurity is introduced into this polycrystalline silicon film in the same manner as in the first gate electrode layer 9.

Next, in each of the memory cell FM forming region of the EEPROM and the memory cell EM forming region of the EPROM, the second patterning of the gate electrode layer 13 is performed for the first time. In this patterning, the second gate electrode layer 13 is patterned, and the interlayer insulating film 11 and the floating gate electrode 9 are sequentially patterned (overlapped) using the same mask. By this patterning, the control gate electrode 13 of the field effect transistor Qf and the shunt wiring 13 of the memory cell selecting MISFET Qfs can be formed in the memory cell FM forming region of the EEPROM. Further, the control gate electrode 13 of the field effect transistor can be formed in the memory cell EM formation region of the EPROM. The patterning is performed by using anisotropic etching such as RIE. In the memory cell FM of the EEPROM, the field effect transistor Qf and the memory cell selecting MISFET Qf
By forming each of s in a double-layered gate structure, the dimension between the gate electrodes is not added with the mask alignment margin dimension in the manufacturing process, and the dimension between the gate electrodes can be defined by the processing accuracy of the mask. Therefore, the area occupied by the memory cell FM can be reduced.

Next, in each of the memory cell DM forming region of the DRAM, the n-channel MISFET Qn ₂ forming region and the p-channel MISFET Qp ₂ forming region of the CMOS, the second patterning is performed on the gate electrode layer 13 of the second layer. Give. By performing this patterning, as shown in FIGS. 7A and 7B, the memory cell selection MISFET Qds, the n-channel MISFET Qn ₂ , the p-channel MISFET Q are selected.
Each gate electrode 13 of p ₂ can be formed.
The patterning is performed using anisotropic etching such as RIE.

Next, the entire surface of the substrate is oxidized to form an insulating film 14 covering the surfaces of the gate electrodes 9 and 13, the floating gate electrode 9 and the control gate electrode 13.
The insulating film 14 is formed to increase the film thickness of each of the gate insulating films 6 and 12 at the ends of the gate electrodes 9 and 13 and to improve the withstand voltage.

Next, the memory cell selection MISFET Qds formation region of the memory cell DM of the DRAM and the EEPROM.
Memory cell FM formation region, CMOS n-channel MI
An n-type semiconductor region 15 is formed in the main surface portion of the semiconductor substrate 1 in each of the SFET Qn ₁ and Qn ₂ formation regions. The semiconductor region 15 can be formed, for example, by introducing P of about 10 ¹³ [atoms / cm ² ] by ion implantation with energy of about 50 to 80 [KeV].

Next, the CMOS p-channel MISF is used.
In the ETQp ₁ and Qp ₂ formation regions, the p-type semiconductor region 17 is formed on the main surface portion of the well region 2. Semiconductor region 17
Is 10 ¹³ [atoms / cm ² ] of B, for example.
It can be formed by introducing by ion implantation with an energy of about 20 [KeV].

Next, as shown in FIGS. 8A and 8B, in the memory cell EM formation region of the EPROM,
An n-type semiconductor region 16 having an impurity concentration higher than that of the n-type semiconductor region 15 is formed on the main surface portion of the semiconductor substrate 1. The semiconductor region 16 is mainly configured to increase the electric field strength in the vicinity of the drain region and increase the amount of hot carriers generated. The semiconductor region 16 has, for example, 10 ¹⁵ [atoms]
/ Cm < ² >] of As is introduced by ion implantation with an energy of about 60 to 100 [KeV].

Each of the semiconductor regions 15, 16 and 17 for forming these LDD structures has gate electrodes 9 and 1, respectively.
3, the floating gate electrode 9 and the control gate electrode 13 are self-aligned. The semiconductor regions 15, 16 and 17 may be formed in different order, or may be formed before the insulating film 14 is formed.

Next, sidewall spacers 18 are formed on the side walls of the gate electrodes 9 and 13, the floating gate electrode 9 and the control gate electrode 13, respectively.
The sidewall spacers 18 can be formed, for example, by subjecting a silicon oxide film deposited by CVD to anisotropic etching such as RIE.

Next, the memory cell selection MISFET Qds forming region of the DRAM memory cell DM and the EEPROM.
Memory cell FM forming region of EPROM, memory cell E of EPROM
M formation region, CMOS n-channel MISFETQ
In the n ₁ and Qn ₂ formation regions, the n + type semiconductor region 19 is formed on the main surface portion of the semiconductor substrate 1. In the semiconductor region 19, for example, As of about 10 ¹⁶ [atoms / cm ² ] is 60 to 60.
It can be formed by introducing by ion implantation with an energy of about 100 [KeV]. Semiconductor region 1
9 is formed in self-alignment with the respective gate electrodes 9, 13 floating gate electrode 9 and control gate electrode 13. By the process of forming the semiconductor region 19, the memory cell selecting MISFET of the memory cell DM is formed.
Qds, the field effect transistor Qf of the memory cell FM,
MISFET Qfs for memory cell selection, memory cell EM
Field effect transistor, n-channel MISFET Qn
Each of ₁ and Qn ₂ is completed.

Next, as shown in FIGS. 9A and 9B, CMOS p-channel MISFETs Qp ₁ and Qp _{2 are provided.}
In each formation region of p,
A + type semiconductor region 20 is formed. The semiconductor region 20 contains 10 to 20 B of about 10 ¹⁵ [atoms / cm ² ], for example.
It can be formed by introducing by ion implantation with energy of about [KeV]. This semiconductor region 20
P-channel MISFET Qp
Each of ₁ and Qp ₂ is completed.

Next, the interlayer insulating film 21 and the connection hole 22 are sequentially formed, and the wiring 23 is formed as shown in FIGS. 1 (a) and 1 (b). The interlayer insulating film 21 is, for example, B
The PSG film or a single layer of the PSG film or a composite film mainly composed of the PSG film is formed.

Thereafter, a final passivation film (not shown) is formed on the entire surface of the substrate to complete the semiconductor integrated circuit device of the present Example I.

As described above, the memory cell (dynamic type memory element) D of the DRAM having the information storage capacitive element C is used.
In a method of manufacturing a semiconductor integrated circuit device having an EEPROM memory cell (nonvolatile storage element) FM having M and a tunnel insulating film 8, a dielectric film 8 of an information storage capacitive element C of the memory cell DM is formed. By performing the step of forming and the step of forming the tunnel insulating film 8 of the memory cell FM in the same manufacturing step, the tunnel insulating film 8 can be formed in the step of forming the dielectric film 8.
The manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the process of forming the tunnel insulating film 8.

A DR having an information storage capacitive element C
E having AM memory cell DM and tunnel insulating film 8
In a method of manufacturing a semiconductor integrated circuit device including a memory cell FM of an EPROM, a step of forming a semiconductor region 7 forming a lower electrode of an information storage capacitive element C of the memory cell DM, and a field effect of the memory cell FM. The step of forming the semiconductor region 7 of the transistor Qf is performed in the same manufacturing step, and thereafter, the step of forming the dielectric film 8 of the information storage capacitor C and the tunnel insulating film 8 of the field effect transistor Qf are formed. The tunnel insulating film 8 is formed in the semiconductor region 7 of the field effect transistor Qf in the process of forming the semiconductor region 7 and the dielectric film 8 of the information storage capacitive element C by performing the same manufacturing process as the forming process. Therefore, the manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the process of forming the semiconductor region 7 and the tunnel insulating film 8. It is possible.

A DR having an information storage capacitive element C
AM memory cell DM and floating gate electrode 9
EEPROM memory cell FM (or and EP
In a method of manufacturing a semiconductor integrated circuit device including a memory cell EM of ROM, a step of forming a plate electrode (upper electrode) 9 of an information storage capacitive element C of the memory cell DM, and the memory cell FM (or and / or Memory cell EM)
By performing the process of forming the floating gate electrode 9 in the same manufacturing process, the information storage capacitive element C is formed.
Since the floating gate electrode 9 can be formed in the step of forming the plate electrode 9, the manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the floating gate electrode 9.

Further, the memory cell DM of the DRAM having the capacitance element C for storing information and the MISFET Qds for selecting the memory cell and the memory cell FM of the EEPROM having the floating gate electrode 9 and the control gate electrode 13 (or the memory cell EM of the EPROM). And a floating gate of the memory cell FM (or the memory cell EM) in the method of manufacturing a semiconductor integrated circuit device including the step of forming an information storage capacitive element C plate electrode (upper electrode) 9 of the memory cell DM. The step of forming the electrode 9 is performed in the same manufacturing step, and the memory cell D
Gate electrode 1 of M memory cell selection MISFET Qds
3 and the step of forming the control gate electrode 13 of the memory cell FM (or the memory cell EM) are performed in the same manufacturing process, so that the plate electrode 9 of the information storage capacitor C and the memory cell are formed. MI for selection
Since the floating gate electrode 9 and the control gate electrode 9 of the memory cell FM can be formed in the step of forming the gate electrode 13 of the SFET Qds, the floating gate electrode 9 and the control gate electrode 13 are formed.
The number of manufacturing steps of the semiconductor integrated circuit device can be reduced by an amount corresponding to the step of forming.

In addition, DRAM memory cells DM and E
In a method of manufacturing a semiconductor integrated circuit device having a memory cell FM of EPROM, a semiconductor region 7, a dielectric film 8, a plate electrode 9, a gate electrode 13 of a memory cell selection MISFET Qds of the information storage capacitor C of the memory cell DM. And the step of forming each of the semiconductor region 7, the tunnel insulating film 8, the floating gate electrode 9, and the control gate electrode 13 of the memory cell FM in the same manufacturing process. In the process of forming each of the DM semiconductor region 7, the dielectric film 8, the plate electrode 9, and the gate electrode 13, the semiconductor region 7, tunnel insulating film 8, floating gate electrode 9, and control gate electrode 13 of the memory cell FM are formed. Since each can be formed, the semiconductor integrated circuit device has a corresponding amount. It is possible to further reduce the granulation step.

(Embodiment II) The present embodiment II is the same as the semiconductor integrated circuit device of the embodiment I except that the DRAM is used.
The gate electrode material of the second layer is used to form the plate electrode of the information storage capacitive element of the memory cell of FIG.
It is a second embodiment of the present invention in which the gate electrode of the ISFET is formed of the first-layer gate electrode material.

A semiconductor integrated circuit device incorporating a microcomputer according to the second embodiment of the present invention is shown in FIG. 10 (a cross-sectional view of a main part showing each element). Embodiment II is DRA
Since the other element structure except the memory cell of M is the same as that of the first embodiment, FIG. 10 shows the memory cell DM of DRAM, the memory cell FM and EPROM of EEPOM.
Only the memory cell EM of is shown.

As shown in FIG. 10, D of the semiconductor integrated circuit
The memory cell DM of the RAM is a memory cell selection MISF.
It is composed of a series circuit of ETQds and an information storage capacitive element C.

The information storage capacitor C of the memory cell DM has a planar structure in which an n-type semiconductor region (lower electrode) 7, a dielectric film 8 and a plate electrode (upper electrode) 13 are sequentially stacked. ing. The plate electrode 13 is the second
It is formed of the gate electrode material of the layer. Dielectric film 8
Is formed with a thin film thickness like the tunnel insulating film 8 of the field effect transistor Qf of the memory cell FM of the EEPROM.

The memory cell selecting MISFET Qds is
It comprises a semiconductor substrate 1, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 15 which are source regions and drain regions, and a pair of n + -type semiconductor regions 19. The gate electrode 9 is formed of a first-layer gate electrode material.

Next, a method of manufacturing the semiconductor integrated circuit device will be briefly described with reference to FIGS. 11 to 13 (cross-sectional views of essential parts shown in each manufacturing process).

First, similarly to the first embodiment, the well region 2 is formed in the semiconductor substrate 1, and then the field insulating film 3 and the p-type channel stopper region 4 are sequentially formed.

Next, in the semiconductor element forming region, the gate insulating film 6A is formed on the main surfaces of the semiconductor substrate 1 and the well region 2, respectively.

Next, the information storage capacitive element C forming region of the memory cell DM of the DRAM and the memory cell F of the EEPROM.
An n-type semiconductor region 7 is formed on the main surface portion of each semiconductor substrate 1 in the M field effect transistor Qf forming region.

Next, in the field effect transistor Qf forming region of the memory cell FM of the EEPROM, a part of the gate insulating film 6A on the semiconductor region 7 is removed, and as shown in FIG. 1, a tunnel is formed in the removed region. The insulating film 8 is formed. By the step of forming the tunnel insulating film 8, the gate insulating film 6A in the other region is grown on the gate insulating film 6. Unlike Embodiment I, Embodiment II is
The dielectric film 8 of the information storage capacitive element C is formed by a process different from the process of forming the tunnel insulating film 8.

Next, the first-layer gate electrode layer 9 is formed on the entire surface of the substrate including the gate insulating film 6 and the tunnel insulating film 8. Then, the gate electrode layer 9 of the first layer is subjected to predetermined patterning to form the gate electrode 9 and the floating gate electrode 9. The gate electrode 9 is formed on the gate insulating film 6 in each of the memory cell selection MISFET Qds formation region of the DRAM memory cell DM and the memory cell selection MISFET Qfs formation region of the EEPROM memory cell FM. The floating gate electrode 9 is E
Field effect transistor Q of EPROM memory cell FM
On the gate insulating film 6 and the tunnel insulating film 8 of f, EPRO
It is formed on each of the gate insulating films 6 of the M memory cells EM. Although not shown, the gate electrode 9 is formed in the peripheral circuit CMOS n-channel MISFET Qn ₁ forming region,
It is also formed on each gate insulating film 6 in the p-channel MISFET Qp ₁ forming region.

Next, an insulating film 11A is formed on the surface of each of the gate electrode 9 and the floating gate electrode 9.
The insulating film 11A is formed of a silicon oxide film obtained by oxidizing the surfaces of the gate electrode 9 and the floating gate electrode 9. Although not shown in the figure, a p-channel MISFETQp on the main surface of the semiconductor substrate 1 in the n-channel MISFETQn ₂ forming region of the peripheral circuit is formed by the step of forming the insulating film 11A.
_A gate insulating film used as a part of the gate insulating film (12) is formed on each of the main surfaces of the well regions 2 of the ₂ formation region.

Next, as shown in FIG. 12, the gate insulating film 6 in the information storage capacitive element C forming region of the DRAM memory cell DM is selectively removed to expose the main surface of the semiconductor region 7.

Next, a dielectric film 8 is formed on the exposed main surface of the semiconductor region 7. The dielectric film 8 is formed of, for example, a silicon oxide film formed by oxidizing the main surface of the semiconductor substrate 1. The dielectric film 8 is formed in a step different from that of the tunnel insulating film 8, but is formed with a substantially similar thin film thickness. The insulating film 11 is formed by the process of forming the dielectric film 8.
A is grown, and the insulating film 11 is formed on the surface of the gate electrode 9 and the gate insulating film 11 is formed on the surface of the floating gate electrode 9.
Can be formed. Further, the CMOS n-channel MISFET Qn ₂ forming region of the peripheral circuit, the p-channel M
The gate insulating film 12 can be formed by growing the gate insulating film in each of the ISFET Qp ₂ forming regions.

Next, the second-layer gate electrode layer 13 is formed on the entire surface of the substrate including the dielectric film 8, the gate insulating film 11 (and the gate insulating film 12 not shown) and the like. And
This second gate electrode layer 13 is patterned twice, and each of the plate electrode 13, the control gate electrode 13, the shunt wiring 13 (and the gate electrode 13 of the peripheral circuit) is subjected to patterning as shown in FIG. To form.

After that, the insulating film 14, the semiconductor regions 15, 16, and 17, the sidewall spacers 18, the semiconductor regions 19 and 20, and the interlayer insulating film 2 are formed as in the first embodiment.
The semiconductor integrated circuit device of the present embodiment II is completed by sequentially forming 1, the connection hole 22, and the wiring 23.

The semiconductor integrated circuit device configured as described above can achieve the following effects in addition to the effects of the first embodiment.

A method of manufacturing a semiconductor integrated circuit device comprising a memory cell DM of a DRAM having an information storage capacitive element C and an EEPROM memory cell FM (or an EPOM memory cell EM) having a control gate electrode 13, A step of forming a plate electrode (upper electrode) 13 of the information storage capacitive element C of the memory cell DM;
By performing the step of forming the control gate electrode 13 of the memory cell FM (or the memory cell EM) in the same manufacturing step, the control gate electrode 13 is formed in the step of forming the plate electrode 13 of the information storage capacitive element C. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by an amount corresponding to the step of forming the control gate electrode 13.

Further, the memory cell DM of the DRAM having the capacitance element C for storing information and the MISFET Qds for memory cell selection and the memory cell FM of the EEPROM having the floating gate electrode 9 and the control gate electrode 13 (or the memory cell EM of the EPROM). And a step of forming the floating gate electrode 9 of the memory cell FM, and a memory cell selecting MISFE for the memory cell DM.
The step of forming the gate electrode 9 of TQds is performed in the same manufacturing step, and the step of forming the control gate electrode 13 of the memory cell FM and the plate electrode 13 of the information storage capacitive element C of the memory cell DM are formed. By performing the same process as the process, the floating gate electrode 9 and the control gate electrode 9 of the memory cell FM are formed in the process of forming the gate electrode 9 of the memory cell selecting MISFET Qds and the plate electrode 13 of the information storage capacitive element C. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by an amount corresponding to the step of forming the floating gate electrode 9 and the control gate electrode 13.

Further, the memory cells DM and E of the DRAM are
In the method of manufacturing a semiconductor integrated circuit device having an EPROM memory cell FM, the semiconductor region 7 of the information storage capacitor C of the memory cell DM, the plate electrode 13, and the gate electrode 9 of the memory cell selecting MISFET Qds are formed. By performing the step and the step of forming the semiconductor region 7, the control gate electrode 13, and the floating gate electrode 9 of the memory cell FM in the same manufacturing process, the semiconductor region 7 of the memory cell DM, the plate electrode 13, Since each of the semiconductor region 7, the control gate electrode 13, and the floating gate electrode 9 of the memory cell FM can be formed in the step of forming each of the gate electrodes 9, the manufacturing process of the semiconductor integrated circuit device corresponding to that can be performed. It can be further reduced.

(Embodiment III) This embodiment is a third embodiment of the present invention in which the semiconductor element in the semiconductor integrated circuit device of the embodiment I has a single-layer gate structure.

FIG. 14 shows a semiconductor integrated circuit device incorporating a microcomputer which is the third embodiment of the present invention.
It is shown in (a) and FIG. 14 (b) (a cross-sectional view of an essential part showing each element).

As shown in FIGS. 14A and 14B, the information storage capacitive element C of the memory cell DM of the DRAM.
Has a planar structure in which an n-type semiconductor region (lower electrode) 7, a dielectric film 8, and a plate electrode (upper electrode) 9 are sequentially stacked. The plate electrode 9 is formed of a first-layer gate electrode material. The dielectric film 8 is formed with a thin film thickness as in the first embodiment.

The memory cell selecting MISFET Qds is
The semiconductor substrate 1, the gate insulating film 6, the gate electrode 9, and the pair of n-type semiconductor regions 15 which are the source region and the drain region.
And a pair of n + type semiconductor regions 19. The gate electrode 9 is formed of a first-layer gate electrode material. That is, the memory cell DM of the DRAM has a single-layer gate structure.

The memory cell FM of the EEPROM is shown in FIG.
Although the sectional structure is not shown in FIGS. 14A and 14B, as shown in FIG. 17 (a plan view of the memory cell), the field effect transistor Qf and the memory cell selecting MISFET are shown.
It is composed of a series circuit with Qfs.

The field effect transistor Qf includes a semiconductor substrate 1, an n-type semiconductor region 7, a gate insulating film (first gate insulating film) 6, a tunnel insulating film 8, a floating gate electrode 9, a gate insulating film (second gate insulating film). ) 6, a control gate electrode 7A, a pair of n-type semiconductor regions 15 which are a source region and a drain region, and a pair of n + -type semiconductor regions 19. The floating gate electrode 9 is formed of a first-layer gate electrode material. The floating gate electrode 9 is provided so as to extend in the gate width direction up to the control gate electrode 7A formed in the n-type semiconductor region. A gate insulating film (second gate insulating film) 6 is provided between the floating gate electrode 9 and the control gate electrode 7A. The control gate electrode (semiconductor region) 7A is formed in the same manufacturing process as the semiconductor region 7. The control gate electrode 7A has a wiring 23 used as a word line WL through the connection hole 22.
It is connected to the.

The memory cell selecting MISFET Qfs is
As shown in FIG. 17, the semiconductor substrate 1, the gate insulating film 6,
Gate electrode 9, a pair of n-type semiconductor regions 15 and a pair of n + -type semiconductor regions 19 which are a source region and a drain region
It is composed of The gate electrode 9 is made of a first-layer gate electrode material. The gate electrode 9 is formed integrally with the word line (WL) 9. The memory cell selecting MISFET Qfs has substantially the same structure as the memory cell selecting MISFET Qds of the DRAM memory cell DM and the n-channel MISFET Qn of the peripheral circuit. That is, the memory cell FM of the EEPROM
Field effect transistor Qf, MIS for memory cell selection
Each of the FETs Qfs has a single-layer gate structure.

The memory cell EM of the EPROM is the EE
Field effect transistor Qf of PROM memory cell FM
It has a structure similar to. That is, the memory cell EM
Is the semiconductor substrate 1 and the gate insulating film (first gate insulating film)
6, floating gate electrode 9, gate insulating film (second
The gate insulating film) 6 and the control gate electrode (n-type semiconductor region) 7A. This memory cell (field effect transistor) EM has a single-layer gate structure.

Peripheral circuit CMOS n-channel MISF
The ETQn is composed of a semiconductor substrate 1, a gate insulating film 12, a gate electrode 9, a pair of n-type semiconductor regions 15 that are a source region and a drain region, and a pair of n + -type semiconductor regions 19. The gate electrode 9 is formed of a first-layer gate electrode material.

The p-channel MISFET Qp is composed of a well region 2, a gate insulating film 12, a gate electrode 9, a pair of p-type semiconductor regions 17 which are source and drain regions, and a pair of p + -type semiconductor regions 20. The gate electrode 9 is formed of a first-layer gate electrode material. That is, each of the n-channel MISFETQn and the p-channel MISFETQp of the CMOS has a single-layer gate structure.

Next, the method of manufacturing the semiconductor integrated circuit device will be described with reference to FIGS. 15 (a) and 15 (b) and FIG.
A brief description will be given with reference to (a) and FIG. 16 (b) (cross-sectional views of relevant parts shown in each manufacturing process).

First, similarly to the first embodiment, the well region 2 is formed on the main surface of the semiconductor substrate 1, and then the field insulating film 3 and the p-type channel stopper region 4 are formed.

Next, in the semiconductor element forming region, the insulating film 6A used as a part of the gate insulating film is formed on the main surfaces of the semiconductor substrate 1 and the well region 2, respectively.

Next, the CMOS n channel M of the peripheral circuit
ISFETQn formation region, p-channel MISFETQp
In each of the formation regions, the insulating film 6A is selectively removed.

Then, the n-channel MISFETQn forming region and the p-channel MISF from which the insulating film 6A is removed are formed.
In each of the ETQp forming regions, a gate insulating film 12 is newly formed on each main surface of the semiconductor substrate 1 and the well region 2. By the step of forming the gate insulating film 12, the insulating film 6A is grown to form the gate insulating film 6 on the main surfaces of the semiconductor substrate 1 and the well region 2, respectively.

Next, as shown in FIGS. 15A and 15B, the information storage capacitive element C forming region of the memory cell DM of the DRAM, the field effect transistor Qf and the memory cell of the memory cell FM of the EEPROM are formed. MISFE for selection
In each of the TQfs formation region and the EPROM memory cell EM formation region, an n-type semiconductor region 7 and a control gate electrode 7A are formed on the main surface portion of the semiconductor substrate 1. Each of the semiconductor region 7 and the control gate electrode 7A can be formed by introducing an n-type impurity by ion implantation.

Next, the information storage capacitive element C forming region of the memory cell DM of the DRAM and the memory cell F of the EEPROM.
In each of the formation regions of the M field effect transistor Qf, the gate insulating film 6 is selectively removed. Then, a dielectric film 8 and a tunnel insulating film 8 are formed on the removed main surface of the semiconductor substrate 1.

Next, the first gate electrode layer 9 is formed on the entire surface of the substrate including the gate insulating films 6 and 12, the dielectric film 8 and the tunnel insulating film 8. Thereafter, the first gate electrode layer 9 is subjected to a predetermined patterning, so that as shown in FIGS. 16 (a) and 16 (b),
Each of the plate electrode 9 and the gate electrode 9 and the floating gate electrode 9 can be formed. The plate electrode 9 forms an upper electrode of the information storage capacitive element C of the memory cell DM of the DRAM. The gate electrode 9 is the memory cell D
M memory cell selection MISFET Qds, EEPRO
M memory cell FM memory cell selecting MISFETQ
fs, CMOS MISFETs Qn and Qp of the peripheral circuit
To form the respective gate electrodes. The floating gate electrode 9 forms the field effect transistor Qf of the memory cell FM and the floating gate electrode of the memory cell EM of the EPROM.

Next, as in the first embodiment, the semiconductor regions 15, 16, 17 and the sidewall spacers 18,
Semiconductor regions 19 and 20, interlayer insulating film 21, connection holes 22,
By sequentially forming each of the wirings 23, as shown in FIG.
As shown in FIGS. 4A and 14B, the semiconductor integrated circuit device is completed.

The semiconductor integrated circuit device configured as described above can achieve the following effects in addition to the effects of the first embodiment.

DRAM memory cells DM and EEPRO
In a method of manufacturing a semiconductor integrated circuit device including M memory cells FM (or EPROM memory cells EM), an n-type semiconductor region (lower electrode) 7 of an information storage capacitive element C of the memory cell DM is formed. By performing the step and the step of forming the n-type semiconductor region 7 and the control gate electrode (n-type semiconductor region) 7A of the memory cell FM in the same manufacturing process, the semiconductor region 7 of the information storage capacitive element C is formed. Since the semiconductor region 7 and the control gate electrode 7A of the memory cell FM can be formed in the forming process, the process corresponding to the process of forming the semiconductor region 7 and the control gate electrode 7A is equivalent to the manufacturing process of the semiconductor integrated circuit device. Can be reduced.

Also, DRAM memory cells DM and EE
In a method of manufacturing a semiconductor integrated circuit device including a PROM memory cell FM (and an EPROM memory cell EM), an information storing capacitive element C plate electrode (upper electrode) 9 and a memory cell selecting MIS of the memory cell DM are provided.
The step of forming the gate electrode 9 of the FET Qds and the step of forming the floating gate electrode 9 of the field effect transistor Qf of the memory cell FM are performed by the same manufacturing process, whereby the plate electrode 9 of the information storage capacitive element C is formed. Also, since the floating gate electrode 9 of the memory cell FM can be formed in the step of forming the gate electrode 9 of the memory cell selecting MISFET Qds, the semiconductor integrated circuit device corresponds to the step of forming the floating gate electrode 9. The manufacturing process of can be reduced.

Further, since the semiconductor integrated circuit device has the single-layer gate structure, the number of conductive layers is small, and the manufacturing process of the semiconductor integrated circuit device can be simplified.

(Embodiment IV) This embodiment IV is the same as the semiconductor integrated circuit device of the embodiment I except that the DRAM
4 is a fourth embodiment of the present invention in which the information storage capacitive element of the memory cell is configured to have a stacked structure.

A semiconductor integrated circuit device incorporating a microcomputer which is Embodiment IV of the present invention is shown in FIG. 18 (a cross-sectional view of a main portion showing each element).

As shown in FIG. 18, the memory cell DM of the DRAM is composed of a series circuit of a memory cell selecting MISFET Qds and a stacked structure information storage capacitive element C.

The memory cell selecting MISFET Qds is
Similar to Embodiment III, the gate electrode 9 is made of the first-layer gate electrode material.

The information storage capacitive element C is formed by sequentially stacking the plate electrode (lower electrode) 13, the dielectric film 26, and the plate electrode 27. Plate electrode 1
3 is the data line 2 of the MISFET Qds for memory cell selection
3 is connected to the semiconductor region 19 on the side not connected. This connection is made through the connection hole 25 formed in the interlayer insulating film 24 and defined by the sidewall spacer 18. The plate electrode 13 is formed of a second-layer gate electrode material, for example, a polycrystalline silicon film. The dielectric film 26 is formed of a single layer of a silicon oxide film, a silicon nitride film, a tantalum oxide film or a composite film thereof formed by an insulating film forming method such as CVD or sputtering. The plate electrode 27 is formed of a third-layer gate electrode material, for example, a polycrystalline silicon film. The second-layer gate electrode material, the third
Although not shown, each of the gate electrode materials of the layers is used as wirings and resistance elements in other regions.

EEPROM memory cells FM, EPRO
Each of the memory cell EM of M and the CMOS (not shown) of the peripheral circuit has a single-layer gate structure, as in the third embodiment.

Although the method of manufacturing the semiconductor integrated circuit device of this embodiment is omitted, basically, after forming a semiconductor element having a single-layer gate structure such as the MISFET Qds for memory cell selection of the memory cell DM of the DRAM, Memory cell DM
The information storage capacitive element C is formed.

The semiconductor integrated circuit device having such a structure can achieve the same effects as those of the first embodiment.

Although the invention made by the present inventor has been specifically described based on the above-mentioned embodiment, the present invention is
Of course, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

For example, according to the present invention, an EEPROM memory cell has a one-transistor structure (field-effect transistor Qf).
Only).

[0147] Further, the present invention is that the memory cells of the EEPROM MNOS (M etal N itride O xide S emiconducto
It may be composed of a field effect transistor having the structure r).

[0148]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

In the semiconductor integrated circuit device having the dynamic type memory element and the non-volatile memory element, the number of manufacturing steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of essential parts of a semiconductor integrated circuit device incorporating a microcomputer that is Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view of an essential part showing each manufacturing step of the semiconductor integrated circuit.

FIG. 3 is a cross-sectional view of an essential part showing each manufacturing step of the semiconductor integrated circuit.

FIG. 4 is a main-portion cross-sectional view showing each of the manufacturing steps of the semiconductor integrated circuit;

FIG. 5 is a cross-sectional view of an essential part showing each manufacturing step of the semiconductor integrated circuit.

FIG. 6 is a cross-sectional view of an essential part showing each manufacturing step of the semiconductor integrated circuit.

FIG. 7 is a main-portion cross-sectional view showing each of the manufacturing steps of the semiconductor integrated circuit;

FIG. 8 is a main-portion cross-sectional view showing each of the manufacturing steps of the semiconductor integrated circuit;

FIG. 9 is a sectional view of a key portion, showing each manufacturing step of the semiconductor integrated circuit.

FIG. 10 is a main-portion cross-sectional view of a semiconductor integrated circuit device including a microcomputer which is Embodiment II of the present invention.

FIG. 11 is a main-portion cross-sectional view showing each of the manufacturing steps of the semiconductor integrated circuit device;

FIG. 12 is a fragmentary cross-sectional view showing each of the manufacturing steps of the semiconductor integrated circuit device;

FIG. 13 is a main-portion cross-sectional view showing each of the manufacturing steps of the semiconductor integrated circuit device;

FIG. 14 is a cross-sectional view of essential parts of a semiconductor integrated circuit device incorporating a microcomputer that is Embodiment III of the present invention.

FIG. 15 is a main-portion cross-sectional view showing each of the manufacturing steps of the semiconductor integrated circuit device;

FIG. 16 is a fragmentary cross-sectional view showing each of the manufacturing steps of the semiconductor integrated circuit device;

FIG. 17 is a plan view showing a memory cell of an EEPROM of the semiconductor integrated circuit.

FIG. 18 is a main-portion cross-sectional view of a semiconductor integrated circuit device including a microcomputer which is Embodiment IV of the present invention.

[Explanation of symbols]

DM, FM, EM ... Memory cell, Qds, Qfs ... MISFET for memory cell selection, C ... Capacitance element for information storage,
Qf ... electric field transistor, Qn, Qp ... MISFET,
6, 11, 12 ... Gate insulating film, 7, 15, 16, 1
7, 19, 20 ... Semiconductor region, 8 ... Dielectric film, tunnel insulating film, 9 ... Gate electrode, plate electrode, floating gate electrode, 13 ... Gate electrode, control gate electrode.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H01L 21/8247 29/788 29/792

Claims (11)

[Claims] 1. A semiconductor integrated circuit device comprising a dynamic storage element having an information storage capacitive element and a memory cell selection MISFET, and a plurality of MISFETs constituting a peripheral circuit of the dynamic storage element on one semiconductor substrate. The MISFET forming the peripheral circuit is the selection M
A semiconductor integrated circuit device comprising a MISFET having a gate insulating film having a thickness different from that of the gate insulating film of the ISFET. 2. A semiconductor integrated circuit device comprising a dynamic memory element having an information storage capacitive element and a memory cell selecting MISFET, and a plurality of MISFETs constituting a peripheral circuit thereof on one semiconductor substrate. The MISFET forming the peripheral circuit is the selection M
A semiconductor integrated circuit device comprising a MISFET having a gate insulating film having a thickness smaller than that of a gate insulating film of ISFET. What is claimed is: 1. A semiconductor integrated circuit device comprising: a dynamic memory element having an information storage capacitor element and a memory cell selecting MISFET; and a MISFET forming a peripheral circuit thereof on a single semiconductor substrate. MIS for cell selection
A semiconductor integrated circuit device, wherein the gate insulating film of the FET is thicker than the gate insulating film of the MISFET forming the peripheral circuit. 3. A method of manufacturing a semiconductor integrated circuit device comprising a dynamic memory element having an information storage capacitive element and a memory cell selecting MISFET, and a MISFET forming a peripheral circuit thereof on one semiconductor substrate. , MIS for memory cell selection of the dynamic memory element
A step of sequentially forming a gate insulating film and a gate electrode of the FET, and a gate insulating film of the MISFET forming the peripheral circuit is formed into a memory cell selecting MIS of the dynamic memory element.
Forming the gate electrode of the MISFET constituting the peripheral circuit after forming the gate insulating film to be thinner than the gate insulating film of the FET, and manufacturing the semiconductor integrated circuit device. 4. A method of manufacturing a semiconductor integrated circuit device comprising a dynamic memory element having an information storage capacitive element and a memory cell selecting MISFET, and a MISFET forming a peripheral circuit thereof on one semiconductor substrate. , MIS for memory cell selection of the dynamic memory element
Forming a gate insulating film of the FET, and forming a gate insulating film of the MISFET of the peripheral circuit as a MISFET for selecting a memory cell of the dynamic memory element.
Forming the gate insulating film thinner than the gate insulating film, and a memory cell selecting MIS of the dynamic memory element.
MIS constituting the gate electrode of the FET and the peripheral circuit
And a step of forming a gate electrode of the FET. 5. A gate insulating film and a gate electrode of a MISFET forming a peripheral circuit different from the peripheral circuit are formed by a step of forming a gate insulating film and a gate electrode of the memory cell selecting MISFET of the dynamic memory element. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein the semiconductor integrated circuit device is formed. 6. A semiconductor integrated circuit device comprising a dynamic storage element having an information storage capacitive element and a memory cell selection MISFET, and a plurality of MISFETs constituting a peripheral circuit thereof on one semiconductor substrate. The MISFET forming the peripheral circuit is the selection M
A semiconductor integrated circuit device comprising a MISFET having a gate insulating film that is thicker than the thickness of the gate insulating film of the ISFET. 7. A method of manufacturing a semiconductor integrated circuit device, comprising: a dynamic memory element having an information storage capacitive element and a memory cell selecting MISFET; and a MISFET forming a peripheral circuit thereof on one semiconductor substrate. And a step of sequentially forming a gate insulating film and a gate electrode of the MISFET forming the peripheral circuit, and a step of sequentially forming a gate insulating film and a gate electrode of the MISFET forming the dynamic memory element. A method of manufacturing a semiconductor integrated circuit device having a feature. 8. A method of manufacturing a semiconductor integrated circuit device, comprising: a dynamic memory element having an information storage capacitive element and a memory cell selecting MISFET; and a MISFET forming a peripheral circuit thereof on one semiconductor substrate. A step of forming a gate insulating film of a MISFET forming the peripheral circuit, and a memory cell selecting MIS of the dynamic memory element.
The gate insulating film of the FET is used as the MI that constitutes the peripheral circuit.
Forming the gate insulating film thinner than the gate insulating film of the SFET, and selecting a memory cell MIS of the dynamic memory element
MIS constituting the gate electrode of the FET and the peripheral circuit
And a step of forming a gate electrode of the FET. 9. A gate insulating film and a gate electrode of a MISFET forming a peripheral circuit different from the peripheral circuit are formed by a step of forming a gate insulating film and a gate electrode of the memory cell selecting MISFET of the dynamic memory element. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the semiconductor integrated circuit device is formed. 10. The semiconductor integrated circuit device according to claim 1, further comprising a non-volatile memory element provided with a floating gate electrode. 11. The semiconductor integrated circuit device according to claim 10, wherein the gate insulating film provided under the floating gate electrode is configured as a tunnel insulating film for passing a tunnel current.