JPH1187639A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of manufacture processes for a semiconductor integrated circuit device. SOLUTION: In the method for manufacturing a semiconductor integrated circuit device, wherein at least a DRAM an a logic circuit are comprised on the same substrate, a capacitance element C3 of the logic circuit is formed in a process where a capacitance element of a memory cell MD of the DRAM is formed. The capacitance element C3 is formed after a transistor element has been formed in an element formation region of the surface of the substrate, and an inter-layer insulating film 15 is formed on an upper layer of the transistor element. The formation of the capacitance element C3 comprises a process where a lower part electrode 17 is formed on the inter-layer insulating film 15, a process where a dielectrics film 18 is formed on the lower part electrode 17, and a process where an upper part electrode 19 is formed on the dielectrics film 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a semiconductor integrated circuit device, in particular, on the same substrate, a system IC that circuits having different functions are mixed at least two (I ntegrated C i
rcuit).

[0002]

As a semiconductor integrated circuit device, DRAM on the same semiconductor substrate (D ynamic R andum A ccess M emor
y) and CPU (C entral P rocessing U nit ) system IC was mixed logic circuit such as has been developed. In this system IC, since the DRAM and the logic circuit are mounted on the same substrate, the data transfer speed between the DRAM and the logic circuit is high. For this type of system IC,
For example, CIC C 1996 [“Perform
ance Evaluation of a Microprocessor with On-ch
ip DRAM and High Bandwidth Internal Bus ”,
S. Iwata et. al., CICC'96 13.1 p269
272].

[0003]

SUMMARY OF THE INVENTION The present inventor has proposed the above-mentioned D
As a result of studying a system IC having a RAM and a logic circuit, the following problems were found.

[0004] The DRAM has one bit of information ("1").
Or "0") of memory cells that store MISFET (M e
tal I nsulator S emiconductor F ield E ffect T ran
(sistor) and a capacitor. This capacitive element has a laminated structure in which a lower electrode, a dielectric film, and an upper electrode are sequentially laminated. Each of the lower electrode and the upper electrode is formed of, for example, a polycrystalline silicon film into which an impurity for reducing a resistance value is introduced. The dielectric film is formed of, for example, a single-layer film made of a silicon oxide film or a silicon nitride film, or a multilayer film made of a silicon oxide film and a silicon nitride film.

In the logic circuit, a decoupling capacitive element is inserted between power supply wirings in order to prevent fluctuations in power supply potential due to switching noise. This capacitive element
The gate electrode as an upper electrode, a gate insulating film as a dielectric film, MIS (M etal a semiconductor region formed on the main surface of the semiconductor substrate under the gate insulating film and the lower electrode I nsu
It is composed of lator S emiconductor) structure. That is,
In the system IC, the capacitance element of the DRAM and the capacitance element of the logic circuit are formed in separate steps, and the number of manufacturing steps of the system IC increases correspondingly.

An object of the present invention is to provide a technique capable of reducing the number of manufacturing steps of a semiconductor integrated circuit device. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. A method of manufacturing a semiconductor integrated circuit device having at least a DRAM and a logic circuit on the same substrate, wherein a capacitor of the logic circuit is formed in a step of forming a capacitor of a memory cell of the DRAM. The formation of the capacitance element is performed after forming a transistor element in an element formation region on the surface of the substrate and forming an interlayer insulating film on the transistor element. The formation of the capacitive element includes a step of forming a lower electrode on the interlayer insulating film, a step of forming a dielectric film on the lower electrode, and a step of forming an upper electrode on the dielectric film. .

According to the above-described means, the capacitance element of the logic circuit is formed in the same step as the capacitance element of the DRAM memory cell.
The number of manufacturing steps of the semiconductor integrated circuit device can be reduced.

Further, since the capacitance element of the logic circuit has a laminated structure in which the lower electrode, the dielectric film, and the upper electrode are sequentially laminated on the interlayer insulating film, the occupied area is larger than that of the capacitance element of the MIS structure. Scaled down. As a result, the area occupied by the logic circuit can be reduced, and the size of the semiconductor integrated circuit device can be reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described below together with an embodiment in which the present invention is applied to a system IC. In the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a block diagram of a system IC according to an embodiment of the present invention. As shown in FIG. 1, a system IC according to the present embodiment includes a DRAM unit 51, an SRAM
(S tatic R andom A ccess M emory) unit 52, logic unit 53 has a structure in which mixed on the same substrate respectively of the analog circuit unit 54. These units are interconnected via an input / output data bus (I / O-BUS).

As shown in FIG. 2 (main part circuit diagram), the DRAM unit 51 is provided with a memory cell MD for storing 1-bit information ("1" or "0").
A sense amplifier circuit DSA is arranged as a peripheral circuit. The memory cell MD is a memory cell selecting element n
It is composed of a series circuit of a channel MISFET Qs and a capacitance element C1 as an information storage element, and is arranged in a region where a word line WL and a bit line BL intersect. The plurality of memory cells MD are arranged in a matrix in the memory cell array region. The sense amplifier circuit DSA
n-channel MISFET Qn, p-channel MISFET
Qp and a resistance element R as a load element.

As shown in FIG. 3 (main part circuit diagram), the SRAM unit 52 is provided with a memory cell MS for storing 1-bit information ("1" or "0").
A sense amplifier circuit SSA is arranged as a peripheral circuit.

The memory cell MS is composed of a flip-flop circuit composed of two inverter circuits, two n-channel MISFETs Qt as transfer elements, and a capacitive element C2 as an α-line soft error countermeasure element. 2
Each of the two inverter circuits includes a p-channel MISFET Qf as a load element and an n-channel MISFET Qd as a driving element. P channel MISFET Qf and n channel MIS of one inverter circuit
Each drain region of the FET Qd is configured as a storage node portion (information storage node portion) A of a flip-flop circuit, and a p-channel MISFET Q of the other inverter circuit.
Each drain region of the f-channel and n-channel MISFETs Qd is configured as a storage node section (information storage node section) B of the flip-flop circuit.

The one n-channel MISFET Qt
Is inserted between the storage node unit A of the flip-flop circuit and the bit line BL1, and the other n-channel MISFE
TQt is inserted between the storage node section B of the flip-flop circuit and the bit line BL2. The operations of the two n-channel MISFETs Qt are controlled by the word lines WL.

One electrode of the capacitor C2 is connected to the storage node A of the flip-flop circuit, and the other electrode is connected to the storage node B of the flip-flop circuit. That is, the capacitor C2 is added to the storage node of the flip-flop circuit.

The sense amplifier circuit SSA is an n-channel MISFE, similarly to the sense amplifier circuit DSA.
TQn, a p-channel MISFET Qp, and a resistance element R as a load element.

The logic circuit unit 53 includes a NOT gate circuit, a NOR gate circuit, a NAND gate circuit,
Logic circuits such as an R gate circuit and an AND gate circuit are provided. Although not shown, the logic circuit includes a p-channel MISFET and an n-channel MISFET. Further, in the logic circuit unit 53, as shown in FIG. 4 (main part circuit diagram), a capacitive element C3 is arranged. The capacitive element C3 is inserted between the first reference power supply line Vcc and the second reference power supply line Vss for decoupling in order to prevent fluctuation of the power supply potential due to switching noise. Between the first reference power supply line Vcc and the second reference power supply line Vss, p-channel MISFETs Qp and n
A channel MISFET Qn is inserted.

In the logic circuit unit 53, a resistance element R is arranged as shown in FIG. The resistance element R has one end connected to a signal transmission path connecting the flip-flop circuit FF1 and the flip-flop circuit FF2, and is inserted into a diagnostic path connected to the other end of the flip-flop circuit FF3. In FIG. 6, reference sign GT is a logic circuit, and reference sign BA is a buffer circuit.

As shown in FIG. 5 (main circuit diagram), the analog circuit unit is provided with a switched capacitor circuit including an operational amplifier OP, an n-channel MISFET Qn, and a capacitor C4. As shown in the circuit diagram), an A / D converter including an encoder circuit ED, an operational amplifier circuit OP, and a resistance element R is arranged. Operational amplifier circuit OP and encoder circuit ED
Are p-channel MISFET and n-channel MISFE
T.

The capacitance element C2 of the SRAM unit 52, the capacitance element C3 of the logic circuit unit 53, and the capacitance element C4 of the analog circuit unit 54 are formed in the step of forming the capacitance element C1 of the DRAM unit 51.

The resistance element R of the DRAM unit 51, the resistance element R of the SRAM unit 52, and the resistance element R of the logic circuit unit 53 are connected to the analog circuit unit 54.
Is formed in the step of forming the resistance element R.

The n-channel MIS of each unit is
The FET and the p-channel MISFET are formed in the same step.

Next, a specific structure of the system IC will be described with reference to FIGS. FIG. 8 shows each element (n-channel MISFET, p-channel MISF) constituting the logic circuit unit 53.
(ET, capacitance element, resistance element). In FIG.
2 shows a memory cell MD of a DRAM unit 51 and a memory cell MS of an SRAM unit 52.

The elements forming the sense amplifier circuit of the DRAM unit 51, the elements forming the sense amplifier circuit of the SRAM unit 52, and the elements forming the analog circuit unit 54 are the respective elements forming the logic circuit unit 53. Since these elements have substantially the same structure, the illustration of these elements is omitted.

In FIGS. 8 and 9, the upper layer of the wiring 22, which will be described later, is not shown and hatching (parallel diagonal lines) representing a cross section is partially omitted for the sake of clarity.

As shown in FIGS. 8 and 9, the system IC
Is mainly composed of a p-type semiconductor substrate 1 made of, for example, single crystal silicon. An n-type well region 3 is formed in a p-channel field-effect transistor forming region on the surface of the p-type semiconductor substrate 1.

The memory cell M of the DRAM unit 51
N-channel MISFE as a memory cell selecting element for D
As shown in FIG. 9, TQs is formed in an n-channel field effect transistor forming region on the surface of p-type semiconductor substrate 1 in a region surrounded by field insulating film 2. The n-channel MISFET Qs mainly includes a p-type semiconductor substrate 1 serving as a channel forming region, a gate insulating film 4, a gate electrode 5A, a pair of n-type semiconductor regions 6 serving as source and drain regions, and a pair of n-type semiconductor regions. 9
It is composed of The pair of n-type semiconductor regions 6 are formed in self-alignment with the gate electrode 5A, and the pair of n-type semiconductor regions 9 are formed of side wall insulating films formed on side surfaces of the gate electrode 5A.
(Sidewall spacers). The pair of n-type semiconductor regions 9 has a higher impurity concentration than the n-type semiconductor region 6. Ie, n-channel MISFETQs the LDD (L ightly D oped D
rain) structure.

The memory cell M of the DRAM unit 51
The capacitive element C1, which is the information storage element of D, has an interlayer insulating film 1
5 surface. The capacitive element C1 has a laminated structure in which a lower electrode 17, a dielectric film 18, and an upper electrode 19 are sequentially laminated from the surface of the interlayer insulating film 15. Each of the lower electrode 17 and the upper electrode 19 is formed of, for example, a titanium nitride (TiN) film. The dielectric film 18 is formed of, for example, a tantalum oxide (TaOx) film or a lead titanium zirconate (Pb (Zr, Ti) O ₃ ) film.

The lower electrode 17 of the capacitive element C1 is formed by the conductive burying material 16 buried in the connection hole of the interlayer insulating film 15.
Is electrically connected to one n-type semiconductor region 9 of the n-channel MISFET Qs. n-channel MIS
The other n-type semiconductor region 9 of the FET Qs is
5 is electrically connected to the bit line BL via the conductive embedding material 12 embedded in the connection hole. The conductive embedding material 12 is formed of, for example, a polycrystalline silicon film into which an impurity for reducing a resistance value is introduced.

The n-channel MISFET Qs is arranged below the bit line BL, and the capacitive element C1 is connected to the bit line BL.
It is arranged in the upper layer. That is, the memory cell MD has a capacitor C1 serving as an information storage element in an upper layer of the bit line BL.
It is composed of a COB of arranging the (C apacitor O ver B itline) structure. By arranging the capacitance element C1 of the memory cell MD in the upper layer of the bit line BL in this manner, the size of the capacitance element C1 in the planar direction can be maximized, and the occupied area of the memory cell MD is reduced. However, it is possible to secure a charge amount necessary to store 1 [bit] of information.

The memory cell M of the SRAM unit 52
An n-channel MISFET Qd, which is an element for driving S,
As shown in FIG. 9, in a region surrounded by the field insulating film 2, an n-channel field-effect transistor forming region on the surface of the p-type semiconductor substrate 1 is formed. The n-channel MISFET Qd mainly includes a p-type semiconductor substrate 1 serving as a channel forming region, a gate insulating film 4, a gate electrode 5A, and a pair of n serving as a source region and a drain region.
And a pair of n-type semiconductor regions 9. That is, the n-channel MISFET Qd has the same LDD structure as the n-channel MISFET Qs described above.

A silicide layer 14 is formed on the surface of the gate electrode 5A and the surface of the n-type semiconductor region 9 of the n-channel MISFET Qd. The silicide layer 14 is formed of, for example, a titanium silicide (TiSix) film.

The memory cell M of the SRAM unit 52
The p-channel MISFET Qf, which is a load element of S,
As shown in FIG. 9, in a region surrounded by the field insulating film 2, it is formed on the surface of the n-type well region 3. The p-channel MISFET Qf mainly includes an n-type well region 3 serving as a channel formation region, a gate insulating film 4, a gate electrode 5A, a pair of n-type semiconductor regions 7 serving as source and drain regions, and a pair of n-type semiconductor regions. 1
0. The pair of n-type semiconductor regions 7 are formed in self-alignment with the gate electrode 5A, and the pair of n-type semiconductor regions 10 are self-aligned with the side wall insulating film (sidewall spacer) formed on the side surface of the gate electrode 5A. It is formed with. The pair of n-type semiconductor regions 10 has a higher impurity concentration than the n-type semiconductor region 7. That is, the p-channel MISFET Qf has an LDD structure.

A silicide layer 14 is formed on the surface of the gate electrode 5A of the p-channel MISFET Qf and the surface of the p-type semiconductor region 10.

The memory cell M of the SRAM unit 52
Capacitance element C2 which is an element for countermeasures against α-ray soft error of S
Are formed on the surface of the interlayer insulating film 15 as shown in FIG. The capacitive element C2 has a laminated structure in which a lower electrode 17, a dielectric film 18, and an upper electrode 19 are sequentially laminated from the surface of the interlayer insulating film 15. This capacitance element C2 is formed in the step of forming the above-described capacitance element C1.

The lower electrode 17 of the capacitive element C2 is formed by the conductive burying material 16 buried in the connection hole of the interlayer insulating film 15.
Through one of the n-channel MISFETs Qd
And electrically connected to one n-type semiconductor region 10 of one channel MISFET Qf via a conductive burying material 16 buried in a connection hole of the interlayer insulating film 15. It is connected.

The upper electrode 19 of the capacitive element C2 is formed of the conductive burying material 16 buried in the connection hole of the interlayer insulating film 15.
Through one of the n-channel MISFETs Qd
And electrically connected to one n-type semiconductor region 10 of the other channel MISFET Qf via a conductive burying material 16 buried in a connection hole of the interlayer insulating film 15. It is connected.

The other n-type semiconductor region 9 of the other n-channel MISFET Qd is buried in the conductive burying material 16 buried in the connection hole of the interlayer insulating film 15 and in the connection hole of the interlayer insulating film 20. It is electrically connected to a wiring 22 formed on the surface of the interlayer insulating film 20 via a conductive burying material 21. Also, the other p-channel MISFET
The other n-type semiconductor region 10 of Qf is formed via conductive burying material 16 buried in the connection hole of interlayer insulating film 15 and conductive burying material 21 buried in the connection hole of interlayer insulating film 20. Thus, it is electrically connected to the wiring 22 formed on the surface of the interlayer insulating film 20. Each of the conductive embedding materials 16 and 21 is formed of, for example, a tungsten (W) film. The wiring 22 has, for example, a laminated structure in which a titanium nitride film, an aluminum (Al) alloy film to which copper (Cu) is added, and a titanium nitride film are sequentially laminated.

The n-channel MISFET Qt which is a transfer element of the memory cell MS of the SRAM unit 52
Although not shown, has the same structure as the n-channel MISFET Qd.

The n-channel M of the logic circuit unit 53
The ISFET Qn is formed in an n-channel field effect transistor forming region on the surface of the p-type semiconductor substrate 1 in a region surrounded by the field insulating film 2 as shown in FIG. This n-channel MISFET Qn
It is mainly composed of a p-type semiconductor substrate 1 serving as a channel forming region, a gate insulating film 4, a gate electrode 5A, a pair of n-type semiconductor regions 6 and a pair of n-type semiconductor regions 9 serving as source and drain regions. . That is, the n-channel MISF
The ETQn has the same LDD structure as the n-channel MISFET Qs described above.

A silicide layer 14 is formed on the surface of the gate electrode 5A of the n-channel MISFET Qn and the surface of the n-type semiconductor region 9. This n-channel MISF
Each of the pair of n-type semiconductor regions 9 of the ETQn includes a conductive burying material 16 buried in the connection hole of the interlayer insulating film 15 and a conductive burying material 21 buried in the connection hole of the interlayer insulating film 20. And is electrically connected to the wiring 22 via.

The p-channel M of the logic circuit unit 53
As shown in FIG. 8, the ISFET Qp is formed on the surface of the n-type well region 3 in a region surrounded by the field insulating film 2. This p-channel MISFE
The TQp mainly includes an n-type well region 3, which is a channel forming region, a gate insulating film 4, a gate electrode 5A, a pair of n-type semiconductor regions 7, which are a source region and a drain region, and a pair of n-type semiconductor regions 10. Have been. That is, the p-channel MISFET Qp is
Like the TQf, it has an LDD structure.

A silicide layer 14 is formed on the surface of the gate electrode 5A of the p-channel MISFET Qp and the surface of the p-type semiconductor region 10. This p-channel MIS
Each of the pair of n-type semiconductor regions 10 of the FET Qp is formed of a conductive burying material 16 buried in a connection hole of the interlayer insulating film 15.
In addition, it is electrically connected to the wiring 22 via the conductive burying material 21 buried in the connection hole of the interlayer insulating film 20.

The capacitance element C3 of the logic circuit unit 53
Is formed on the surface of the interlayer insulating film 15 as shown in FIG. The capacitive element C3 has a laminated structure in which a lower electrode 17, a dielectric film 18, and an upper electrode 19 are sequentially laminated from the surface of the interlayer insulating film 15. This capacitance element C3 is formed in the step of forming the above-described capacitance element C1.

The resistance element R of the logic circuit unit 53
Is formed of a polycrystalline silicon film 5B formed on the surface of field insulating film 2 as shown in FIG. The contact region at one end and the contact region at the other end of the polycrystalline silicon film 5B are set to have a higher impurity concentration than the impurity concentration of the intermediate region sandwiched between these contact regions. A silicide layer 1 is formed on the surface of the contact region on one end and the surface of the contact region on the other end of the polycrystalline silicon film 5B.
4 are formed. One end and the other end of the resistance element R are respectively provided with a conductive burying material 16 buried in a connection hole of the interlayer insulating film 15 and a conductive burying material buried in a connection hole of the interlayer insulating film 20. It is electrically connected to the wiring 22 via the material 21.

Although not shown in FIGS. 8 and 9, the capacitance element C4 of the analog circuit unit 54 has the same configuration as the above-described capacitance element C1, and is formed in the step of forming the capacitance element C1.

The resistance element R of the DRAM unit 51,
Although not shown in FIGS. 8 and 9, the resistance element R of the SRAM unit 52 and the resistance element R of the analog circuit unit 54 have the same configuration as the resistance element R of the logic circuit unit 53 described above. These resistance elements R are formed in a step of forming the resistance elements R of the analog circuit unit 54.

Next, a method of manufacturing the system IC will be described with reference to FIGS. 10 to 25 (a cross-sectional view of a main part for describing the manufacturing method). In FIGS. 10 to 25, hatching representing a cross section is shown for easy understanding of the drawings.
(Parallel oblique lines) are partially omitted.

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared. Next, a field insulating film 2 is formed in an element isolation region on the surface of the p-type semiconductor substrate 1. Field insulating film 2, a groove is formed in the element isolation region of the p-type semiconductor substrate 1 of the surface, then the entire surface, for example, CVD on the surface of the substrate 1 including the groove (C hemical V apor D eposit
The silicon oxide film is formed by ion) method, then subjected to CMP (C hemical M echanical P olishing ) process is formed on the silicon oxide film.

Next, an n-type well region 3 is selectively formed in a p-channel field effect transistor forming region on the surface of the substrate 1. The steps so far are shown in FIGS.

Next, a gate insulating film 4 is formed on the p-channel field effect transistor forming region and the n-channel field effect transistor forming region on the surface of the p-type semiconductor substrate 1. The gate insulating film 4 is formed of a thermal silicon oxide film.

Next, a polycrystalline silicon film 5 into which impurities are not introduced is formed on the entire surface of the surface of the substrate 1 by a CVD method.

Next, a mask 30 is formed on the surface of the polycrystalline silicon film 5. The mask 30 is formed by a photolithography technique. Mask 30 has an opening on the p-channel field-effect transistor forming region of substrate 1 and has an opening on a region of polycrystalline silicon film 5 which is to be a contact region of the resistance element.

Next, using the mask 30 as an impurity introduction mask, boron (B) is implanted as a p-type impurity into the polycrystalline silicon film 5 exposed from the mask 30 by ion implantation. The steps so far are shown in FIGS.

Next, the mask 30 is removed.
A mask 31 is formed on the surface of the polycrystalline silicon film 5.
The mask 31 is formed by a photolithography technique. The mask 31 has an opening on the n-channel field-effect transistor formation region of the substrate 1.

Next, using the mask 31 as a mask for introducing impurities, phosphorus (P) is introduced as an n-type impurity into the polycrystalline silicon film 5 exposed from the mask 31 by ion implantation. The steps up to this point are shown in FIGS.

Next, after removing the mask 31, the polycrystalline silicon film 5 is patterned to form a gate electrode 5.
A and the resistance element R are formed and not shown,
A word line WL is formed.

Next, arsenic (As) as an n-type impurity is selectively introduced into the n-channel field effect transistor forming region on the surface of the p-type semiconductor substrate 1 by ion implantation to form a pair of n-type semiconductor regions 6. Form. In this step, the resistive element R is covered with a mask.

Next, boron (B) as a p-type impurity is selectively introduced into the p-channel field effect transistor forming region on the surface of the p-type semiconductor substrate 1 by ion implantation to form a pair of p-type semiconductor regions 7. Form. In this step, boron is also introduced into the resistance element R.

Next, a side wall is formed on the side surface of the gate electrode 5A.
An edge film 8 is formed. The side wall insulating film 8 is formed on the p-type semiconductor substrate 1.
For example, a silicon oxide film is formed on the entire surface of the
After that, RIE (ReactiveIon
Etching) or the like. This
In the step, the sidewall insulating film 8 is also formed on the side surface of the resistance element R.
It is formed.

Next, arsenic (As) as an n-type impurity is selectively introduced into the n-channel field effect transistor forming region on the surface of the p-type semiconductor substrate 1 by ion implantation to form a pair of n-type semiconductor regions 9. Form. In this step, the resistive element R is covered with a mask. By this step, n
Channel MISFET Qn, n channel MISFET Q
Each of the s and n-channel MISFETs Qd is formed, and an n-channel MISFET Qt (not shown) is formed.

Next, boron (B) as a p-type impurity is selectively introduced into the p-channel field effect transistor forming region on the surface of the p-type semiconductor substrate 1 by ion implantation to form a pair of p-type semiconductor regions 10. Form. In this step, the intermediate region of the resistance element R is covered with a mask. By this step, the p-channel MISFET Qp and the p-channel M
Each of the ISFETs Qf is formed. The steps up to this point are shown in FIGS.

Next, an insulating film 11 made of, for example, a silicon oxide film is formed on the entire surface of the p-type semiconductor substrate 1 by a CVD method.

Next, a connection hole is formed in the insulating film 11,
Thereafter, a conductive embedding material 12 is formed in the connection hole.

Next, a wiring material made of, for example, a tungsten (W) film is formed on the entire surface of the insulating film 11 by sputtering, and thereafter, the wiring material is patterned to form a bit line BL. At the same time, although not shown, bit lines BL1 and BL2 are formed. The steps so far are shown in FIGS.

Next, an insulating film 13 made of, for example, a silicon oxide film is formed on the entire surface of the insulating film 11 by a CVD method. After that, each of the insulating film 13 and the insulating film 11 is subjected to RI
E, etc., is selectively applied, and the n-channel MI
The insulating films 11 and 13 are left over the region of the SFET Qs and the intermediate region of the resistance element R, and the insulating films 13 and 11 in other regions are removed.

Next, a silicide layer 14 is formed on the surface of the gate electrode 5A, on the surface of the n-type semiconductor region 9 and on the surface of the p-type semiconductor region 10, and on the contact region of the resistance element R. 14 is formed. The silicide layer 14 is formed on the entire surface of the substrate 1 by, for example, titanium.
(Ti) film is formed, and then heat treatment is performed to cause the gate electrode 5A, the n-type semiconductor region 9, the p-type semiconductor region 10, and the Si of the resistive element R to react with the Ti of the titanium film.
An unreacted titanium film not reacting with Si is selectively removed by, for example, a wet etching method. In this step, the n-channel MISFET Qs and the resistance element R
Is covered with the insulating film 11, the silicide layer 14 is not formed on the surface of the n-type semiconductor region 7 of the n-channel MISFET Qs and the surface of the intermediate region of the resistor R. The steps up to this point are shown in FIGS.

Next, an insulating film made of, for example, a silicon oxide film is deposited on the entire surface of the substrate 1 by a CVD method to form an interlayer insulating film 15, and thereafter, a connection hole is formed in the interlayer insulating film 15. Then, the conductive embedding material 16 is inserted into the connection hole.
To form The steps up to this point are shown in FIGS.

Next, a DR is formed on the surface of the interlayer insulating film 15.
The capacitance element C1 of the memory cell MD of the AM unit 51 is formed, and the memory cell MS of the SRAM unit 52 is formed.
Element C2 of the logic circuit unit 53 and the capacitance element C2 of the logic circuit unit 53
Form 3 In this step, not shown,
The capacitance element of the analog circuit unit 54 is also formed at the same time. In these capacitive elements, a first electrode material made of, for example, a titanium nitride (TiN) film is formed on the surface of the interlayer insulating film 15 and then the first electrode material is patterned to form a lower electrode 17. And then the lower electrode 1
For example, a tantalum oxide (TaOx) film or lead titanium zirconate (Pb (Z
A dielectric film 18 made of an (r, Ti) O ₃ ) film is formed, thereafter, the dielectric film 18 is patterned, and then, for example, over the entire surface of the interlayer insulating film 15 including the dielectric film 18, for example. A second electrode material made of a titanium nitride (TiN) film is formed, and thereafter, the second electrode material is patterned to form an upper electrode 19. The steps up to this point are shown in FIGS.

Next, an interlayer insulating film 20 is formed on the entire surface of the substrate 1 including the surface of the upper electrode 19, and thereafter, a connection hole is formed in the interlayer insulating film 20, and thereafter, a connection hole is formed in the connection hole. By forming a conductive embedding material 21 and then forming a wiring 22 on the surface of the interlayer insulating film 20, FIG.
And the state shown in FIG. Thereafter, an interlayer insulating film, a second
By forming the wiring of the layer, the interlayer insulating film, the wiring of the third layer, and the final protective film, the system IC of this embodiment is almost completed.

As described above, according to the present embodiment, the following effects can be obtained. (1) In the step of forming the capacitance element C1 of the memory cell MD of the DRAM, the capacitance element C3 of the logic circuit is formed in the same step as the capacitance element C1 of the memory cell MD of the DRAM by forming the capacitance element C3 of the logic circuit. Since it is formed, the number of manufacturing steps of the system IC can be reduced by an amount corresponding to the step of the capacitor C3 of the logic circuit.

The capacitance element C 3 of the logic circuit has a laminated structure in which the lower electrode 17, the dielectric film 18, and the upper electrode 19 are sequentially laminated on the interlayer insulating film 15.
The occupied area is reduced as compared with the capacitance element having the MIS structure.
As a result, the area occupied by the logic circuit can be reduced, so that the size of the system IC can be reduced.

(2) In the process of forming the capacitance element C1 of the DRAM memory cell MD, the capacitance of the SRAM memory cell MS is formed by forming the capacitance element C2 added to the storage node of the SRAM memory cell MS. Element C
2 is formed in the same step as the capacitive element C1 of the memory cell MD of the DRAM, so that the capacitive element C2 of the memory cell MS is formed.
The number of manufacturing steps of the system IC can be reduced by the amount corresponding to the above step.

(3) In the step of forming the capacitance element C1 of the memory cell MD of the DRAM, the capacitance element C4 of the analog circuit is formed by forming the capacitance element C4 of the analog circuit. Is formed in the same process as the capacitor C4 of the analog circuit.
The number of manufacturing steps of the system IC can be reduced by the amount corresponding to the above step.

(4) In the step of forming the resistance element R of the analog circuit, by forming the resistance element R of the sense amplifier circuit DSA of the DRAM, the sense amplifier circuit D is formed.
Since the resistance element R of the SA is formed in the same step as the resistance element R of the analog circuit, the number of manufacturing steps of the system IC can be reduced by the amount corresponding to the resistance element R of the sense amplifier circuit DSA.

(5) In the step of forming the resistance element R of the analog circuit, by forming the resistance element R of the sense amplifier circuit SSA of the SRAM, the sense amplifier circuit S is formed.
Since the resistance element R of the SA is formed in the same step as the resistance element R of the analog circuit, the number of manufacturing steps of the system IC can be reduced by the amount corresponding to the resistance element R of the sense amplifier circuit SSA.

(6) In the step of forming the resistance element R of the analog circuit, the resistance element R of the logic circuit is formed in the same step as the resistance element R of the analog circuit by forming the resistance element R of the logic circuit. Therefore, the number of manufacturing steps of the system IC can be reduced corresponding to the resistance element R of the logic circuit.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

[0080]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. According to the present invention, the number of manufacturing steps of a semiconductor integrated circuit device can be reduced. According to the present invention,
The size of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a system IC according to an embodiment of the present invention.

FIG. 2 is a main part circuit diagram of the system IC.

FIG. 3 is a main part circuit diagram of the system IC.

FIG. 4 is a main part circuit diagram of the system IC.

FIG. 5 is a main part circuit diagram of the system IC.

FIG. 6 is a main part circuit diagram of the system IC.

FIG. 7 is a main part circuit diagram of the system IC.

FIG. 8 is a sectional view of a main part of the system IC.

FIG. 9 is a sectional view of a main part of the system IC.

FIG. 10 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 11 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 12 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 13 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 14 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 15 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 16 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 17 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 18 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 19 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 20 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 21 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 22 is an essential part cross sectional view for describing the method of manufacturing the system IC;

FIG. 23 is an essential part cross sectional view for describing the method of manufacturing the system IC;

FIG. 24 is a fragmentary cross-sectional view for explaining the method for manufacturing the system IC.

FIG. 25 is an essential part cross sectional view for describing the method of manufacturing the system IC;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type semiconductor substrate, 2 ... field insulating film, 3 ... n-type well region, 4 ... gate insulating film, 5A ... gate electrode, 6
... n-type semiconductor region, 7 ... p-type semiconductor region, 9 ... n-type semiconductor region, 10 ... p-type semiconductor region, 12 ... conductive burying material,
14: silicide layer, 15: interlayer insulating film, 16: conductive burying material, 17: lower electrode, 18: dielectric film, 19: upper electrode, 20: interlayer insulating film, 21: conductive burying material, 22 …
Wiring, C1, C2, C3, C4: Capacitance element, R: Resistance element, MD, MS: Memory cell, DSA, SSA: Sense amplifier circuit, WL: Word line, BL, BL1, BL2 ...
Bit line, Qn, Qs, Qt, Qd... N-channel MIS
FET, Qp, Qf ... p-channel MISFET, 51 ...
DRAM unit, 52 ... SRAM unit, 53 ... Logic circuit unit, 54 ... Analog circuit unit.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yasushi Sekine 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd.

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device having at least a DRAM and a logic circuit on the same substrate,
A method of manufacturing a semiconductor integrated circuit device, comprising: forming a capacitance element of the logic circuit in the step of forming a capacitance element of a memory cell of the DRAM. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said capacitance element is a capacitance element inserted for decoupling between power supply wirings of said logic circuit. 3. At least a DRAM and an SR on the same substrate.
A method for manufacturing a semiconductor integrated circuit device having an AM,
A method of manufacturing a semiconductor integrated circuit device, comprising: forming a capacitor element to be added to a storage node portion of the SRAM memory cell in the step of forming the capacitor element of the DRAM memory cell. 4. A method of manufacturing a semiconductor integrated circuit device having at least a DRAM and an analog circuit on the same substrate, wherein the step of forming a capacitance element of a memory cell of the DRAM includes forming a capacitance element of the analog circuit. A method for manufacturing a semiconductor integrated circuit device, comprising: 5. The method according to claim 1, wherein the formation of the capacitance element is performed after forming a transistor element in an element formation region on a surface of the substrate and forming an interlayer insulating film on an upper layer of the transistor element. Any one of claim 4
13. The method for manufacturing a semiconductor integrated circuit device according to the above item. 6. The method of forming a capacitive element, comprising: forming a lower electrode on the interlayer insulating film; forming a dielectric film on the lower electrode; and forming an upper electrode on the dielectric film. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, further comprising the step of: 7. A method of manufacturing a semiconductor integrated circuit device having at least an analog circuit and a DRAM on the same substrate, wherein in the step of forming a resistance element of the analog circuit, a resistance element of a sense amplifier circuit of the DRAM is formed. A method for manufacturing a semiconductor integrated circuit device. 8. A method of manufacturing a semiconductor integrated circuit device having at least an analog circuit and an SRAM on the same substrate, wherein in the step of forming a resistance element of the analog circuit, a resistance element of a sense amplifier circuit of the SRAM is formed. A method for manufacturing a semiconductor integrated circuit device.