CN113571586B - Double-doped source-drain single transistor exclusive-or gate and manufacturing method thereof - Google Patents
Double-doped source-drain single transistor exclusive-or gate and manufacturing method thereof Download PDFInfo
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- CN113571586B CN113571586B CN202110784870.2A CN202110784870A CN113571586B CN 113571586 B CN113571586 B CN 113571586B CN 202110784870 A CN202110784870 A CN 202110784870A CN 113571586 B CN113571586 B CN 113571586B
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- 239000000463 material Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 abstract 2
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- 230000009977 dual effect Effects 0.000 description 4
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- 238000000206 photolithography Methods 0.000 description 3
- 230000002146 bilateral effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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Abstract
The invention discloses a double-doped source-drain single-transistor exclusive-OR gate and a manufacturing method thereof, wherein two partitions with donor doping and acceptor doping are formed on a source region and a drain region of a transistor, when two signal input ends simultaneously input high level or low level, the double-doped source-drain single-transistor exclusive-OR gate is in an electron conduction state or a hole conduction state to realize high level output, when one of the two signal input ends is in the high level and the other signal input end is in the low level, the double-doped source-drain single-transistor exclusive-OR gate is in an electron blocking state and a hole blocking state to realize low level output, so that the double-doped source-drain single-transistor disclosed by the invention realizes exclusive-OR gate logic only through a single transistor per se, and the complexity of the exclusive-OR gate is greatly reduced.
Description
Technical Field
The invention relates to the technical field of CMOS integrated circuit design and manufacture, in particular to a double-doped source drain single transistor exclusive-OR gate suitable for high-integration low-power consumption CMOS integrated circuit design and manufacture technology and a manufacturing method thereof.
Background
Based on the existing CMOS field effect transistor technology, on the premise of determining an integration process, the larger the number of transistors adopted in the design for realizing a specific function, the larger the chip area required to be occupied for realizing the function. The prior art-based exclusive-or gate is generally implemented by connecting an inverter consisting of 4 or more complementary metal oxide semiconductor field effect transistors and taking the exclusive-or gate logic out of 2 transistors, so that at least 6 or more transistors are needed, and implementing the exclusive-or gate logic by using fewer transistors helps to further simplify the cell structure of the basic gate circuit of the integrated circuit, and more exclusive-or gates are implemented on the same integrated process technology and the same chip area to improve the integration level.
Disclosure of Invention
The invention aims to provide a double-doped source-drain single-transistor exclusive-OR gate and a manufacturing method thereof, which enable an integrated circuit to realize the logical function of the exclusive-OR gate by using the least number of transistors, namely a single transistor.
In order to achieve the above purpose, the present invention provides the following technical solutions: the double-doped source-drain single transistor exclusive-OR gate comprises a silicon substrate of an SOI wafer, wherein a substrate insulating layer of the SOI wafer is arranged above the silicon substrate of the SOI wafer, the substrate insulating layer of the SOI wafer is an insulating material layer, and a semiconductor film region, an interchangeable N-type source drain region a, an interchangeable P-type source drain region a, an interchangeable N-type source drain region b, an interchangeable P-type source drain region b, an insulating medium layer, a gate electrode insulating layer, a gate electrode a and a gate electrode b are arranged above the substrate insulating layer of the SOI wafer; the semiconductor thin film region is made of semiconductor material, and the upper surface, the left side and the right side of the front side and the rear side of the semiconductor thin film region are in contact with the gate electrode insulating layer; the upper surface and the central parts of the front and rear side surfaces of the semiconductor thin film region are in contact with the insulating medium layer;
the interchangeable N-type source drain region a and the interchangeable P-type source drain region a are semiconductor regions doped with N-type impurities and P-type impurities respectively; the interchangeable N-type source drain region a and the interchangeable P-type source drain region a are simultaneously positioned at the left side of the semiconductor film region and are in contact with the semiconductor film region;
the front side surface of the interchangeable N-type source drain region a and the rear side surface of the interchangeable P-type source drain region a are in contact with the insulating medium layer; the back side surface of the interchangeable N-type source drain region a and the front side surface of the interchangeable P-type source drain region a are in contact with the depletion-preventing isolation layer a; the depletion-preventing isolation layer a is made of insulating dielectric materials;
the left side of the upper surfaces of the interchangeable N-type source drain region a and the interchangeable P-type source drain region a are in contact with the interchangeable source drain electrode a, and the right side of the upper surfaces of the interchangeable N-type source drain region a and the interchangeable P-type source drain region a are in contact with the insulating medium layer;
the interchangeable N-type source drain region b and the interchangeable P-type source drain region b are semiconductor regions doped with N-type impurities and P-type impurities respectively; the interchangeable N-type source drain region b and the interchangeable P-type source drain region b are simultaneously positioned on the right side of the semiconductor film region and are in contact with the semiconductor film region;
the front side surface of the interchangeable N-type source drain region b and the rear side surface of the interchangeable P-type source drain region b are in contact with the insulating medium layer; the back side surface of the interchangeable N-type source drain region b and the front side surface of the interchangeable P-type source drain region b are in contact with the depletion-preventing isolation layer b; the depletion-preventing isolation layer b is made of insulating dielectric materials;
the surfaces of the front side and the rear side of the interchangeable N-type source drain region b and the interchangeable P-type source drain region b are in contact with the insulating medium layer, the right side of the upper surfaces of the interchangeable N-type source drain region b and the interchangeable P-type source drain region b are in contact with the interchangeable source drain electrode b, and the left side of the upper surfaces of the interchangeable N-type source drain region b and the interchangeable P-type source drain region b are in contact with the insulating medium layer;
the insulating medium layer is made of insulating medium material; the gate electrode insulating layer is made of insulating dielectric material, and the upper surface, the front side surface and the rear side surface of the left side part of the gate electrode insulating layer are in contact with the gate electrode a; the upper surface and the front and rear side surfaces of the right side portion of the gate electrode insulating layer are in contact with the gate electrode b; the gate electrode a and the gate electrode b are metal, alloy, polysilicon or metal silicide; the gate electrode a is in contact with the upper surface of the left side part and the front and rear side surfaces of the gate electrode insulating layer, the gate electrode a is insulated and isolated from each other by the gate electrode insulating layer and the semiconductor film region, and the gate electrode a is insulated and isolated from the interchangeable source-drain electrode a and the interchangeable source-drain electrode b by the insulating dielectric layer; the gate electrode b is in contact with the upper surface and the front and rear side surfaces of the right side part of the gate electrode insulating layer, the gate electrode b is insulated and isolated from each other by the gate electrode insulating layer and the semiconductor thin film region, and the gate electrode b is insulated and isolated from the interchangeable source-drain electrode a and the interchangeable source-drain electrode b by the insulating dielectric layer; the gate electrode a and the gate electrode b are insulated and isolated from each other through an insulating dielectric layer; the interchangeable source drain electrode a is metal, alloy or metal silicide, and the lower surface of the interchangeable source drain electrode a is contacted with the left sides of the upper surfaces of the interchangeable N-type source drain region a and the interchangeable P-type source drain region a to form ohmic type reverse barrier layer contact; the interchangeable source drain electrode b is metal, alloy or metal silicide, and the lower surface of the interchangeable source drain electrode b is contacted with the right side of the upper surfaces of the interchangeable N-type source drain region b and the interchangeable P-type source drain region b to form ohmic type reverse barrier layer contact.
Compared with the prior art, the invention has the beneficial effects that:
1. the implemented exclusive-OR gate has simple structure
According to the double-doped source-drain single-transistor exclusive-OR gate and the manufacturing method thereof, the exclusive-OR gate logic can be realized by only one transistor with the double-doped source-drain structure, so that the complexity of the exclusive-OR gate circuit structure is greatly simplified, and the integration level of an integrated circuit is easy to improve.
2. The logic transmission function of the bidirectional exclusive-OR gate can be realized:
the double-doped source-drain single-transistor exclusive-OR gate and the manufacturing method thereof have the structural characteristics of bilateral symmetry, and the interchangeable source-drain electrode a and the interchangeable source-drain electrode b can be interchanged with each other, namely, any one end of the interchangeable source-drain electrode a and any one end of the interchangeable source-drain electrode b are connected with a power supply voltage input end, and the other end of the interchangeable source-drain electrode a and the interchangeable source-drain electrode b are connected with an exclusive-OR gate output end to output the exclusive-OR gate.
Drawings
FIG. 1 is a top view of a dual doped source drain single transistor exclusive OR gate of the present invention;
FIG. 2 is a cross-sectional view of a dual-doped source-drain single-transistor XOR gate of the present invention along the dashed line A of FIG. 1;
FIG. 3 is a cross-sectional view of a dual doped source drain single transistor XOR gate of the present invention along the dashed line B of FIG. 1;
FIG. 4 is a cross-sectional view of a dual doped source drain single transistor XOR gate of the present invention along the dashed line C of FIG. 1;
FIG. 5 is a cross-sectional view of a dual doped source drain single transistor XOR gate of the present invention along the dashed line D of FIG. 1;
fig. 6 is a circuit connection diagram of the double doped source drain single transistor exclusive-or gate of the present invention.
FIG. 7 is a top view of step one;
FIG. 8 is a cross-sectional view along the broken line A of step one;
FIG. 9 is a cross-sectional view along the broken line B of step one;
FIG. 10 is a top view of step two;
FIG. 11 is a cross-sectional view along the broken line A of step two;
FIG. 12 is a cross-sectional view along the broken line B of step two;
FIG. 13 is a cross-sectional view along the broken line C of step two;
FIG. 14 is a cross-sectional view along the broken line D of step two;
FIG. 15 is a top view of step three;
FIG. 16 is a cross-sectional view along the broken line A of step three;
FIG. 17 is a cross-sectional view along the broken line B of step three;
FIG. 18 is a cross-sectional view along the broken line C of step three;
FIG. 19 is a cross-sectional view along the broken line D of step three;
FIG. 20 is a cross-sectional view along the broken line E of step three;
FIG. 21 is a top view of step four;
FIG. 22 is a cross-sectional view along the broken line A of step four;
FIG. 23 is a top view of step five;
FIG. 24 is a cross-sectional view along the broken line A of step five;
FIG. 25 is a cross-sectional view along the broken line B of step five;
FIG. 26 is a cross-sectional view along the broken line C of step five;
FIG. 27 is a cross-sectional view along the broken line D of step five;
FIG. 28 is a cross-sectional view along the broken line E of step five;
FIG. 29 is a top view of step six;
FIG. 30 is a cross-sectional view along the broken line A of step six;
FIG. 31 is a cross-sectional view along the broken line B of step six;
FIG. 32 is a cross-sectional view along the broken line C of step six;
FIG. 33 is a cross-sectional view along the broken line D of step six;
FIG. 34 is a top view of step seven;
FIG. 35 is a cross-sectional view along the broken line A of step seven;
FIG. 36 is a cross-sectional view along the broken line B of step seven;
FIG. 37 is a cross-sectional view along the broken line C of step seven;
FIG. 38 is a top view of step eight;
FIG. 39 is a cross-sectional view along the broken line A of step eight;
FIG. 40 is a cross-sectional view along the broken line B of step eight;
FIG. 41 is a cross-sectional view along the broken line C of step eight;
FIG. 42 is a cross-sectional view along the broken line D of step eight;
FIG. 43 is a top view of step nine;
FIG. 44 is a cross-sectional view along the broken line A of step nine;
FIG. 45 is a cross-sectional view along the broken line B of step nine;
FIG. 46 is a cross-sectional view along the broken line C of step nine;
fig. 47 is a sectional view along the broken line D of step nine;
FIG. 48 is a cross-sectional view along the broken line E of step nine;
FIG. 49 is a cross-sectional view along the broken line E of step nine;
FIG. 50 is a cross-sectional view along the broken line E of step nine;
1. a silicon substrate of the SOI wafer; 2. a substrate insulating layer of the SOI wafer; 3. a semiconductor thin film region; 4. interchangeable N-type source drain regions a; 5. interchangeable P-type source drain regions a; 6. interchangeable N-type source drain regions b; 7. interchangeable P-type source drain regions b; 8. an insulating dielectric layer; 9. a gate electrode insulating layer; 10. a gate electrode a; 11. a gate electrode b; 12. interchangeable source-drain electrodes a; 13. interchangeable source-drain electrodes b; 14. an anti-depletion isolation layer a; 15. an anti-depletion isolation layer b; 16. a signal input terminal A; 17. and a signal input terminal B; 18. a power supply voltage input terminal; 19. and an exclusive OR gate output.
Detailed Description
Referring to fig. 1-5, the present invention provides a technical solution: the double doped source drain single transistor exclusive-or gate comprises a silicon substrate 1 of an SOI wafer, and is characterized in that: the SOI device comprises a silicon substrate 1 of an SOI wafer, a substrate insulating layer 2 of the SOI wafer, a semiconductor film region 3, an interchangeable N-type source drain region a4, an interchangeable P-type source drain region a5, an interchangeable N-type source drain region b6, an interchangeable P-type source drain region b7, an insulating medium layer 8, a gate electrode insulating layer 9, a gate electrode a10 and a gate electrode b11, wherein the substrate insulating layer 2 of the SOI wafer is an insulating material layer; the semiconductor film region 3 is made of semiconductor material, and the upper surface and the left and right sides of the front and rear side surfaces of the semiconductor film region 3 are in contact with the gate electrode insulating layer 9; central portions of the upper surface and the front and rear side surfaces of the semiconductor thin film region 3 are in contact with the insulating dielectric layer 8; the interchangeable N-type source drain region a4 and the interchangeable P-type source drain region a5 are semiconductor regions doped with N-type impurities and P-type impurities respectively; the interchangeable N-type source drain region a4 and the interchangeable P-type source drain region a5 are simultaneously positioned at the left side of the semiconductor film region 3 and are in contact with the semiconductor film region 3; the front side surface of the interchangeable N-type source drain region a4 and the rear side surface of the interchangeable P-type source drain region a5 are in contact with the insulating dielectric layer 8; the back side surface of the interchangeable N-type source drain region a4 and the front side surface of the interchangeable P-type source drain region a5 are in contact with the depletion preventing isolation layer a 14; the depletion-preventing isolation layer a14 is made of insulating dielectric materials; the left side of the upper surfaces of the interchangeable N-type source drain region a4 and the interchangeable P-type source drain region a5 are in contact with the interchangeable source drain electrode a12, and the right side of the upper surfaces of the interchangeable N-type source drain region a4 and the interchangeable P-type source drain region a5 are in contact with the insulating dielectric layer 8; the interchangeable N-type source drain region b6 and the interchangeable P-type source drain region b7 are semiconductor regions doped with N-type impurities and P-type impurities respectively; the interchangeable N-type source drain region b6 and the interchangeable P-type source drain region b7 are simultaneously positioned on the right side of the semiconductor film region 3 and are in contact with the semiconductor film region 3; the front side surface of the interchangeable N-type source drain region b6 and the rear side surface of the interchangeable P-type source drain region b7 are in contact with the insulating dielectric layer 8; the back side surface of the interchangeable N-type source drain region b6 and the front side surface of the interchangeable P-type source drain region b7 are in contact with the depletion preventing isolation layer b 15; the depletion prevention isolation layer b15 is made of insulating dielectric materials; the right side of the upper surfaces of the interchangeable N-type source drain region b6 and the interchangeable P-type source drain region b7 are in contact with the interchangeable source drain electrode b13, and the left side of the upper surfaces of the interchangeable N-type source drain region b6 and the interchangeable P-type source drain region b7 are in contact with the insulating dielectric layer 8; the insulating medium layer 8 is made of insulating medium material; the gate electrode insulating layer 9 is an insulating dielectric material, and the upper surface and the front and rear side surfaces of the left side portion of the gate electrode insulating layer 9 are in contact with the gate electrode a 10; the upper surface and the front and rear side surfaces of the right side portion of the gate electrode insulating layer 9 are in contact with the gate electrode b11; the gate electrode a10 and the gate electrode b11 are metal, alloy, polysilicon or metal silicide; the gate electrode a10 is in contact with the upper surface of the left side portion and the front and rear side surfaces of the gate electrode insulating layer 9, the gate electrode a10 is insulated from each other by the gate electrode insulating layer 9 and the semiconductor thin film region 3, and the gate electrode a10 is insulated from the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode b13 by the insulating dielectric layer 8; the gate electrode b11 is in contact with the upper surface and the front and rear side surfaces of the right side portion of the gate electrode insulating layer 9, the gate electrode b11 is insulated from each other by the gate electrode insulating layer 9 and the semiconductor thin film region 3, and the gate electrode b11 is insulated from the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode b13 by the insulating dielectric layer 8; the gate electrode a10 and the gate electrode b11 are insulated from each other by the insulating dielectric layer 8; the interchangeable source drain electrode a12 is metal, alloy or metal silicide, and the lower surface of the interchangeable source drain electrode a12 is contacted with the left side of the upper surfaces of the interchangeable N-type source drain region a4 and the interchangeable P-type source drain region a5 to form ohmic type reverse barrier layer contact; the interchangeable source drain electrode b13 is metal, alloy or metal silicide, and the lower surface of the interchangeable source drain electrode b13 is in contact with the right side of the upper surfaces of the interchangeable N-type source drain region b6 and the interchangeable P-type source drain region b7 and forms an ohmic type reverse barrier layer contact.
As shown in fig. 6, the present invention further provides a method for using a double doped source drain single transistor xor gate, in which the gate electrode a10 is connected to one of two signal input terminals of the xor gate, namely, the signal input terminal a16 and the signal input terminal B17, and the gate electrode B11 is connected to two signal input terminals of the xor gate, namely, to the other end of the signal input terminal a16 and the signal input terminal B17 except for the connection with the gate electrode a 10; the interchangeable source-drain electrode a12 is connected to one of the power supply voltage input terminal 18 and the exclusive-or gate output terminal 19, while the interchangeable source-drain electrode b13 is connected to the other of the power supply voltage input terminal 18 and the exclusive-or gate output terminal 19, which is other than the one connected to the interchangeable source-drain electrode a 12.
When the signal input end A16 and the signal input end B17 are simultaneously input with high level, the gate electrode a10 and the gate electrode B11 are simultaneously at high level, when the interchangeable source drain electrode a12 and the interchangeable source drain electrode B13 are respectively connected with one end of the power voltage input end 18 and one end of the interchangeable N-type source drain electrode B19, the semiconductor film region 3 forms an electron channel in the interior under the coaction of the gate electrode a10 and the gate electrode B11 through the electric field effect, so that electrons can flow from one end with lower potential among the interchangeable source drain electrode a12 and the interchangeable source drain electrode B13 to one end with lower potential among the interchangeable N-type source drain electrode a4 and the interchangeable N-type source drain electrode B6, and flow to one end with higher potential among the interchangeable N-type source drain electrode a4 and the interchangeable N-type source drain electrode B6 through the interior of the semiconductor film region 3, and flow out from one end with higher potential among the interchangeable source drain electrode a12 and the interchangeable source drain electrode B13 at this time, and the double doped source drain electrode is in a state with low level output to the same gate drain electrode B6; when the signal input end A16 and the signal input end B17 are simultaneously input with low level, the gate electrode a10 and the gate electrode B11 are simultaneously at low level, and when the interchangeable source drain electrode a12 and the interchangeable source drain electrode B13 are respectively connected with one end of the power supply voltage input end 18 and one end of the interchangeable gate output end 19, the semiconductor film region 3 forms a hole channel internally under the coaction of the gate electrode a10 and the gate electrode B11 through the electric field effect, so that holes can flow from one end of the interchangeable source drain electrode a12 and the interchangeable source drain electrode B13, which is at a higher potential, to one end of the interchangeable P-type source drain region a5 and the interchangeable P-type source drain region B7, and flow to one end of the interchangeable P-type source drain region a5 and the interchangeable N-type source drain region B6 through the hole channel formed inside the semiconductor film region 3, and flow from one end of the interchangeable source drain electrode a12 and the interchangeable source drain electrode B13, which is at a lower potential, and the double doped source drain gate is at the same as the single crystal, which is at a high level output end of the interchangeable source drain region B7; when one of the signal input terminal a16 and the signal input terminal B17 inputs a high level and the other inputs a low level, and when the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13 are connected to one of the power supply voltage input terminal 18 and the exclusive-or gate output terminal 19, respectively, one of the gate electrode a10 and the gate electrode B11 is at a high level and the other is at a low level, one of the gate electrode a10 and the gate electrode B11 at a high level can block "holes" from the one of the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13 at a higher potential to the one of the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13 at a lower potential to the one of the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13 at a higher potential to the one of the two doped source-drain electrode and the exclusive-or gate output single crystal at a low level.
The circuit can realize the exclusive-OR gate logic by only one transistor with a double-doped source-drain structure, the structure is bilateral symmetry, the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode b13 can be interchanged with each other, and any one end of the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode b13 is connected with a power supply voltage input end 18, and the other end is connected with an exclusive-OR gate output end 19 to output the exclusive-OR gate.
The invention also provides a manufacturing method of the double-doped source-drain single-transistor exclusive-OR gate, which is not limited to the method, and can be realized on an SOI wafer silicon substrate by the following specific manufacturing steps:
step one: referring to fig. 7-9, an SOI wafer is provided, a silicon substrate 1 of the SOI wafer is arranged at the bottom, a substrate insulating layer 2 of the SOI wafer is arranged on the silicon substrate, a semiconductor film is arranged on the upper surface of the substrate insulating layer 2 of the SOI wafer, and a semiconductor film 3 is formed preliminarily through photoetching, etching and deposition processes;
step two: referring to fig. 10-14, an interchangeable N-type source drain region a4, an interchangeable P-type source drain region a5, an interchangeable N-type source drain region b6, and an interchangeable P-type source drain region b7 are preliminarily formed through an ion implantation process, respectively;
step three: referring to fig. 15-20, etching away the partial areas between the interchangeable N-type source drain area a4 and the interchangeable P-type source drain area a5 generated in the second step through an etching process, etching away the partial areas between the interchangeable N-type source drain area b6 and the interchangeable P-type source drain area b7 generated in the second step, further forming the interchangeable N-type source drain area a4, the interchangeable P-type source drain area a5, the interchangeable N-type source drain area b6 and the interchangeable P-type source drain area b7, reserving a space for the depletion-preventing isolation layer a14 and the depletion-preventing isolation layer b15, depositing an insulating medium layer on the basis of the second step through a deposition process, flattening until the semiconductor film 3 is exposed, forming the depletion-preventing isolation layer a14 and the depletion-preventing isolation layer b15, initially forming an insulating medium layer 8, etching away insulating medium layers on the left and right sides of the front surface and the rear surface of the semiconductor film 3 to expose the substrate insulating layer 2 of the SOI wafer, and further forming the insulating medium layer 8;
step four: referring to fig. 21-22, a gate electrode insulating layer is deposited on the basis of the third step by a deposition process, and then the gate electrode insulating layer 9 is preliminarily formed by planarization treatment until the semiconductor film 3 is exposed;
step five: referring to fig. 23 to 28, an insulating dielectric layer is deposited on the basis of the fourth step by a deposition process, and after planarization treatment, the middle portions on the left and right sides are etched by photolithography and etching processes until the gate electrode insulating layer 9 formed in the fourth step and the upper surfaces of the semiconductor thin film 3 between the upper and lower side portions of the gate electrode insulating layer 9 are exposed;
step six: referring to fig. 29-33, a gate electrode insulating layer is deposited on the basis of the fifth step through a deposition process, then planarized until the upper surface of the insulating dielectric layer 8 is exposed, then the upper and lower side portions of the left and right side portions of the gate electrode insulating layer 9 are removed through photolithography and etching processes until the substrate insulating layer 2 is exposed, then a metal, an alloy, polysilicon or a metal silicide is deposited through a deposition process, and then planarized until the gate electrode insulating layer 9 is exposed, thereby preliminarily forming a gate electrode a10 and a gate electrode b11;
step seven: referring to fig. 34 to 37, a gate electrode insulating layer is deposited on the basis of the step six through a deposition process, after planarization treatment, the middle parts on the left and right sides are etched through photolithography and etching processes until the upper surfaces of the gate electrode insulating layer 9, the gate electrode a10 and the gate electrode b11 formed in the step six are exposed;
step eight: referring to fig. 38-42, a metal, an alloy, polysilicon or a metal silicide is deposited on the basis of the seventh step by a deposition process, and then a planarization process is performed until the upper surface of the insulating dielectric layer 8 is exposed, so as to further form a gate electrode a10 and a gate electrode b11;
step nine: referring to fig. 43-50, by etching, on the basis of step eight, etching away a portion of the insulating dielectric layer 8 to expose the upper surfaces of the left sides of the interchangeable N-type source drain region a4 and the interchangeable P-type source drain region a5, and the upper surfaces of the right sides of the interchangeable N-type source drain region b6 and the interchangeable P-type source drain region b7;
step ten: referring to fig. 1-5, a metal, an alloy, polysilicon or a metal silicide is deposited on the basis of step nine by a deposition process, and then planarized until the upper surface of the insulating dielectric layer 8 is exposed, thereby forming the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode b13.
Claims (4)
1. Double doped source drain single transistor exclusive-or gate comprising a silicon substrate (1) of an SOI wafer, characterized in that: the SOI device comprises a silicon substrate (1) of an SOI wafer, wherein a substrate insulating layer (2) of the SOI wafer is arranged above the silicon substrate (1) of the SOI wafer, the substrate insulating layer (2) of the SOI wafer is an insulating material layer, and a semiconductor thin film region (3), an interchangeable N-type source drain region a (4), an interchangeable P-type source drain region a (5), an interchangeable N-type source drain region b (6), an interchangeable P-type source drain region b (7), an insulating medium layer (8), a gate electrode insulating layer (9), a gate electrode a (10) and a gate electrode b (11) are arranged above the substrate insulating layer (2) of the SOI wafer; the semiconductor film region (3) is made of semiconductor material, and the upper surface, the left side and the right side of the front side surface and the rear side surface of the semiconductor film region (3) are in contact with the gate electrode insulating layer (9); the upper surface and the central parts of the front and rear side surfaces of the semiconductor thin film region (3) are in contact with the insulating dielectric layer (8);
the interchangeable N-type source drain region a (4) and the interchangeable P-type source drain region a (5) are semiconductor regions doped with N-type impurities and P-type impurities respectively; the interchangeable N-type source drain region a (4) and the interchangeable P-type source drain region a (5) are simultaneously positioned at the left side of the semiconductor film region (3) and are in contact with the semiconductor film region (3); the front side surface of the interchangeable N-type source drain region a (4) and the rear side surface of the interchangeable P-type source drain region a (5) are in contact with the insulating medium layer (8); the back side surface of the interchangeable N-type source drain region a (4) and the front side surface of the interchangeable P-type source drain region a (5) are in contact with the depletion-preventing isolation layer a (14); the depletion-preventing isolation layer a (14) is made of insulating dielectric materials; the left side of the upper surfaces of the interchangeable N-type source drain region a (4) and the interchangeable P-type source drain region a (5) are in contact with the interchangeable source drain electrode a (12), and the right side of the upper surfaces of the interchangeable N-type source drain region a (4) and the interchangeable P-type source drain region a (5) are in contact with the insulating medium layer (8);
the interchangeable N-type source drain region b (6) and the interchangeable P-type source drain region b (7) are semiconductor regions doped with N-type impurities and P-type impurities respectively; the interchangeable N-type source drain region b (6) and the interchangeable P-type source drain region b (7) are simultaneously positioned on the right side of the semiconductor film region (3) and are in contact with the semiconductor film region (3); the front side surface of the interchangeable N-type source drain region b (6) and the rear side surface of the interchangeable P-type source drain region b (7) are in contact with the insulating medium layer (8); the back side surface of the interchangeable N-type source drain region b (6) and the front side surface of the interchangeable P-type source drain region b (7) are in contact with the depletion-preventing isolation layer b (15); the depletion-preventing isolation layer b (15) is made of insulating dielectric material; the right side of the upper surfaces of the interchangeable N-type source drain region b (6) and the interchangeable P-type source drain region b (7) are in contact with the interchangeable source drain electrode b (13), and the left side of the upper surfaces of the interchangeable N-type source drain region b (6) and the interchangeable P-type source drain region b (7) are in contact with the insulating medium layer (8);
the insulating medium layer (8) is made of insulating medium material; the gate electrode insulating layer (9) is made of insulating dielectric material, and the upper surface, the front side surface and the rear side surface of the left side part of the gate electrode insulating layer (9) are in contact with the gate electrode a (10); the upper surface and the front and rear side surfaces of the right side portion of the gate electrode insulating layer (9) are in contact with the gate electrode b (11); the gate electrode a (10) and the gate electrode b (11) are metal, alloy, polysilicon or metal silicide; the gate electrode a (10) is in contact with the upper surface and the front and rear side surfaces of the left side portion of the gate electrode insulating layer (9), the gate electrode a (10) is insulated from each other by the gate electrode insulating layer (9) and the semiconductor thin film region (3), and the gate electrode a (10) is insulated from the interchangeable source-drain electrode a (12) and the interchangeable source-drain electrode b (13) by the insulating dielectric layer (8); the gate electrode b (11) is in contact with the upper surface and the front and rear side surfaces of the right side portion of the gate electrode insulating layer (9), the gate electrode b (11) is insulated from each other by the gate electrode insulating layer (9) and the semiconductor thin film region (3), and the gate electrode b (11) is insulated from the interchangeable source-drain electrode a (12) and the interchangeable source-drain electrode b (13) by the insulating dielectric layer (8); the gate electrode a (10) and the gate electrode b (11) are insulated from each other by an insulating dielectric layer (8); the interchangeable source-drain electrode a (12) is metal, alloy or metal silicide, and the lower surface of the interchangeable source-drain electrode a (12) is contacted with the left sides of the upper surfaces of the interchangeable N-type source-drain region a (4) and the interchangeable P-type source-drain region a (5) to form ohmic type reverse barrier layer contact; the interchangeable source drain electrode b (13) is metal, alloy or metal silicide, and the lower surface of the interchangeable source drain electrode b (13) is contacted with the right side of the upper surfaces of the interchangeable N-type source drain region b (6) and the interchangeable P-type source drain region b (7) to form ohmic type reverse barrier layer contact.
2. A method of using the double doped source drain single transistor exclusive or gate according to claim 1, wherein: the gate electrode a (10) is connected with one of two signal input ends of the exclusive-or gate, namely, the signal input end A (16) and the signal input end B (17), and the gate electrode B (11) is connected with the other end of the two signal input ends of the exclusive-or gate, namely, the signal input end A (16) and the signal input end B (17) except the connection with the gate electrode a (10); the interchangeable source-drain electrode a (12) is connected with one end of a power supply voltage input end (18) and an exclusive-OR gate output end (19), and the interchangeable source-drain electrode b (13) is connected with the other end of the power supply voltage input end (18) and the exclusive-OR gate output end (19) except the connection with the interchangeable source-drain electrode a (12);
when a signal input end A (16) and a signal input end B (17) are simultaneously input with a high level, a gate electrode a (10) and a gate electrode B (11) are simultaneously at a high potential, and when an interchangeable source drain electrode a (12) and an interchangeable source drain electrode B (13) are respectively connected with one of a power supply voltage input end (18) and an exclusive OR gate output end (19), an electronic channel is formed in the semiconductor film region (3) under the combined action of the gate electrode a (10) and the gate electrode B (11) through an electric field effect, so that electrons can flow from one end of the interchangeable source drain electrode a (12) and the interchangeable source drain electrode B (13) which is at a lower potential to one end of the interchangeable source drain electrode a (4) and the interchangeable source drain electrode B (6) which is also at a lower potential, and flow from one end of the interchangeable source drain electrode a (4) and the interchangeable source drain electrode B (6) which are at a higher potential through the inner part of the semiconductor film region (3), and then flow from one end of the interchangeable source drain electrode a (12) and the interchangeable source drain electrode B (13) which is at a high potential to one end of the interchangeable source drain electrode B (19) which is at a high potential;
when a signal input end A (16) and a signal input end B (17) are simultaneously input with a low level, a gate electrode a (10) and a gate electrode B (11) are simultaneously at a low potential, and when an interchangeable source drain electrode a (12) and an interchangeable source drain electrode B (13) are respectively connected with one of a power supply voltage input end (18) and an exclusive OR gate output end (19), a semiconductor film region (3) forms a hole channel in the interior under the combined action of the gate electrode a (10) and the gate electrode B (11) through an electric field effect, so that holes can flow from one end of the interchangeable source drain electrode a (12) and the interchangeable source drain electrode B (13) which is at a higher potential to one end of the interchangeable P-type source drain electrode a (5) and the interchangeable P-type source drain electrode B (7) which is also at a higher potential, flow to one end of the interchangeable P-type source drain electrode a (5) and the exclusive OR gate output end (6) which is at a lower potential through the hole channel formed in the semiconductor film region (3), and then flow from one end of the interchangeable P-type source drain electrode a (12) and the interchangeable P-drain electrode B (13) which is at a high potential to one end of the interchangeable source drain electrode B (19) which is at a low potential;
when one of the signal input terminal a (16) and the signal input terminal B (17) inputs a high level and the other inputs a low level, and when the interchangeable source drain electrode a (12) and the interchangeable source drain electrode B (13) are respectively connected with one of the power supply voltage input terminal (18) and the exclusive or gate output terminal (19), one of the gate electrode a (10) and the gate electrode B (11) is at a high level and the other is at a low level, one of the gate electrode a (10) and the gate electrode B (11) at a high level can block "holes" from the one of the interchangeable source drain electrode a (12) and the interchangeable source drain electrode B (13) at a high potential by an electric field effect to the one of the interchangeable source drain electrode a (12) and the interchangeable source drain electrode B (13) at a low potential to the one of the interchangeable source drain electrode a (12) and the exclusive or gate electrode B (11) at a low potential by an electric field effect to the one of the interchangeable source drain electrode a (12) at a low potential to the one of the exclusive or gate electrode B (13) at a low potential to the one of the two doped source drain transistor and the exclusive or gate electrode B at a high potential to the exclusive or gate output terminal (19).
3. The method for using the double-doped source-drain single-transistor exclusive-or gate according to claim 2, wherein the method comprises the following steps: the double-doped source-drain single-transistor exclusive-OR gate structure is bilaterally symmetrical, the interchangeable source-drain electrode a (12) and the interchangeable source-drain electrode b (13) can be interchanged, namely, any one end of the interchangeable source-drain electrode a (12) and the interchangeable source-drain electrode b (13) is connected with a power supply voltage input end (18), and the other end of the interchangeable source-drain electrode a is connected with an exclusive-OR gate output end (19) to output the exclusive-OR gate.
4. A method of fabricating a double doped source drain single transistor xor gate according to claim 1, wherein: the specific manufacturing steps are as follows:
step one: providing an SOI wafer, wherein the silicon substrate (1) of the SOI wafer is arranged at the bottommost part, the substrate insulating layer (2) of the SOI wafer is arranged on the silicon substrate, the upper surface of the substrate insulating layer (2) of the SOI wafer is a semiconductor film, and a semiconductor film region (3) is formed preliminarily through photoetching, etching and deposition processes;
step two: respectively preliminarily forming an interchangeable N-type source drain region a (4), an interchangeable P-type source drain region a (5), an interchangeable N-type source drain region b (6) and an interchangeable P-type source drain region b (7) through an ion implantation process;
step three: etching away partial areas between the interchangeable N-type source drain area a (4) and the interchangeable P-type source drain area a (5) generated in the second step through an etching process, etching away partial areas between the interchangeable N-type source drain area b (6) and the interchangeable P-type source drain area b (7) generated in the second step, further forming the interchangeable N-type source drain area a (4), the interchangeable P-type source drain area a (5), the interchangeable N-type source drain area b (6) and the interchangeable P-type source drain area b (7), reserving space for the depletion-preventing isolation layer a (14) and the depletion-preventing isolation layer b (15), depositing an insulating medium layer on the basis of the second step through a deposition process, flattening until the semiconductor film area (3) is exposed, forming the depletion-preventing isolation layer a (14) and the depletion-preventing isolation layer b (15), initially forming an insulating medium layer (8), and etching away insulating medium layers at the left and right sides of the front surface and the rear surface of the semiconductor film area (3) to a substrate insulating layer (2) of an SOI wafer to further form the insulating medium layer (8);
step four: depositing a gate electrode insulating layer on the basis of the third step through a deposition process, and performing planarization treatment until the semiconductor film region (3) is exposed to initially form a gate electrode insulating layer (9);
step five: depositing an insulating medium layer on the basis of the fourth step through a deposition process, carrying out planarization treatment, and etching the middle parts of the left side and the right side through photoetching and etching processes until the upper surface of the semiconductor film region (3) between the gate electrode insulating layer (9) formed in the fourth step and the upper and lower side parts of the gate electrode insulating layer (9) is exposed;
step six: depositing a gate electrode insulating layer on the basis of the fifth step through a deposition process, flattening until the upper surface of the insulating dielectric layer (8) is exposed, removing the upper and lower side parts of the left and right side parts of the gate electrode insulating layer (9) until the substrate insulating layer (2) is exposed through photoetching and etching processes, depositing metal, alloy, polysilicon or metal silicide through a deposition process, flattening until the gate electrode insulating layer (9) is exposed, and preliminarily forming a gate electrode a (10) and a gate electrode b (11);
step seven: depositing a gate electrode insulating layer on the basis of the step six through a deposition process, carrying out planarization treatment, and etching the middle parts of the left side and the right side through photoetching and etching processes until the upper surfaces of the gate electrode insulating layer (9), the gate electrode a (10) and the gate electrode b (11) formed in the step six are exposed;
step eight: depositing metal, alloy, polysilicon or metal silicide on the basis of the step seven through a deposition process, and flattening until the upper surface of the insulating dielectric layer (8) is exposed, so as to further form a gate electrode a (10) and a gate electrode b (11);
step nine: etching away part of the insulating dielectric layer (8) on the basis of the step eight by an etching process until the upper surfaces of the left sides of the interchangeable N-type source drain region a (4) and the interchangeable P-type source drain region a (5) and the upper surfaces of the right sides of the interchangeable N-type source drain region b (6) and the interchangeable P-type source drain region b (7) are exposed;
step ten: depositing metal, alloy, polysilicon or metal silicide on the basis of the step nine through a deposition process, and flattening until the upper surface of the insulating dielectric layer (8) is exposed, thereby forming the interchangeable source drain electrode a (12) and the interchangeable source drain electrode b (13).
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000031362A (en) * | 1998-11-05 | 2000-06-05 | 김영환 | Semiconductor device and producing method thereof |
| WO2016201609A1 (en) * | 2015-06-15 | 2016-12-22 | 北京大学深圳研究生院 | Metal oxide thin-film transistor and display panel, and preparation methods for both |
| CN107785436A (en) * | 2017-10-31 | 2018-03-09 | 沈阳工业大学 | Source and drain resistive formula rectangular grid control U-shaped raceway groove bidirectional transistor and its manufacture method |
| CN107808905A (en) * | 2017-10-31 | 2018-03-16 | 沈阳工业大学 | Bilateral folds the double tunnelling type two-way admittance transistors of grid-control source and drain and its manufacture method |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000031362A (en) * | 1998-11-05 | 2000-06-05 | 김영환 | Semiconductor device and producing method thereof |
| WO2016201609A1 (en) * | 2015-06-15 | 2016-12-22 | 北京大学深圳研究生院 | Metal oxide thin-film transistor and display panel, and preparation methods for both |
| CN107785436A (en) * | 2017-10-31 | 2018-03-09 | 沈阳工业大学 | Source and drain resistive formula rectangular grid control U-shaped raceway groove bidirectional transistor and its manufacture method |
| CN107808905A (en) * | 2017-10-31 | 2018-03-16 | 沈阳工业大学 | Bilateral folds the double tunnelling type two-way admittance transistors of grid-control source and drain and its manufacture method |
Non-Patent Citations (1)
| Title |
|---|
| 一种基于深肖特基势垒辅助栅控制的隧穿场效应晶体管;马恺璐;靳晓诗;;微处理机(第04期);全文 * |
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