KR20000031362A - Semiconductor device and producing method thereof - Google Patents
Semiconductor device and producing method thereof Download PDFInfo
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- KR20000031362A KR20000031362A KR1019980047366A KR19980047366A KR20000031362A KR 20000031362 A KR20000031362 A KR 20000031362A KR 1019980047366 A KR1019980047366 A KR 1019980047366A KR 19980047366 A KR19980047366 A KR 19980047366A KR 20000031362 A KR20000031362 A KR 20000031362A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
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- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 5
- 230000005611 electricity Effects 0.000 abstract 1
- 239000012212 insulator Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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Abstract
Description
본 발명은 반도체 소자의 제조공정에 관한 것으로, 특히 저전압 동작시 회로의 성능향상과 소비전력을 줄이는데 적당한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device suitable for improving circuit performance and reducing power consumption during low voltage operation.
도 1은 일반적인 2-입력 낸드(NAND) 게이트를 나타낸 논리회로도이다.1 is a logic circuit diagram illustrating a typical two-input NAND gate.
도 1에 도시한 바와 같이, NAND 게이트는 병렬로 연결되는 2개의 피모스(PMOS) 트랜지스터와, 직렬로 연결되는 2개의 앤모스(NMOS) 트랜지스터로 구성된다.As shown in FIG. 1, the NAND gate includes two PMOS transistors connected in parallel and two NMOS transistors connected in series.
즉, 소오스 단자가 공통으로 Vdd 전원에 연결되고 각 게이트 전극에는 제 1 입력신호 및 제 2 입력신호가 인가되며 드레인 단자를 공통의 출력단으로 하는 제 1, 제 2 PMOS 트랜지스터(1,2)와, 상기 제 1, 제 2 PMOS 트랜지스터(1,2)의 공통 드레인 단자에 드레인 단자가 연결되며 게이트 전극에 제 1 입력신호가 인가되는 제 1 NMOS 트랜지스터(3)와, 상기 제 1 NMOS 트랜지스터(3)의 소오스 단자에 드레인 단자가 연결되고 게이트 전극에 제 2 입력신호가 인가되며 소오스 단자에 Vss 전원이 연결되는 제 2 NMOS 트랜지스터(4)로 구성된다.That is, the first and second PMOS transistors (1, 2) having a source terminal connected in common to a Vdd power source, a first input signal and a second input signal applied to each gate electrode, and having a drain terminal as a common output terminal; A first NMOS transistor 3 to which a drain terminal is connected to a common drain terminal of the first and second PMOS transistors 1 and 2 and a first input signal is applied to a gate electrode, and the first NMOS transistor 3 A drain terminal is connected to a source terminal of the second input signal, a second input signal is applied to the gate electrode, and a second NMOS transistor 4 having a Vss power source connected to the source terminal.
상기와 같이 구성된 NAND 게이트는 제 1, 제 2 입력신호의 조합에 의해 출력이 "1"로 존재할 확률이 3/4이고, "0"으로 존재할 확률이 1/4이다.The NAND gate configured as described above has a 3/4 probability that the output exists as "1" and a 1/4 probability that it exists as "0" by the combination of the first and second input signals.
따라서 제 1, 제 2 입력신호가 모두 "1"일때만 "0"이 출력되고, 나머지 경우에는 모두 "1"이 출력된다.Therefore, "0" is output only when both the first and second input signals are "1", and "1" is output in all other cases.
한편, 제 1, 제 2 NMOS 트랜지스터(3,4)가 직렬로 연결되므로 풀-다운 경로(Pull-Down Path)의 저항이 증가하는데 이를 예방하기 위해 NMOS 트랜지스터의 크기를 PMOS 트랜지스터의 크기와 일치시킨다.Meanwhile, since the first and second NMOS transistors 3 and 4 are connected in series, the resistance of the pull-down path increases, so that the size of the NMOS transistor matches the size of the PMOS transistor to prevent this. .
도 2는 일반적인 2-입력 노어(NOR) 게이트를 나타낸 논리회로도이다.2 is a logic circuit diagram illustrating a typical two-input NOR gate.
도 2에 도시한 바와 같이, NOR 게이트는 직렬로 연결되는 2개의 PMOS 트랜지스터와 병렬로 연결되는 2개의 NMOS 트랜지스터로 구성된다.As shown in Fig. 2, the NOR gate is composed of two NMOS transistors connected in parallel with two PMOS transistors connected in series.
즉, 소오스 단자가 Vdd 전원에 연결되며 게이트 전극에 제 1 입력신호가 인가되는 제 1 PMOS 트랜지스터(5)와, 상기 제 1 PMOS 트랜지스터(5)의 드레인 단자에 소오스 단자가 연결되고 게이트 전극에 제 2 입력신호가 인가되며 드레인 단자를 출력단으로 하는 제 2 PMOS 트랜지스터(6)와, 상기 제 2 PMOS 트랜지스터(6)의 드레인 단자에 드레인 단자가 공통으로 연결되고 각 게이트 전극에 제 1, 제 2 입력신호가 인가되며 소오스 단자가 공통으로 Vss 전원에 연결되는 제 1, 제 2 NMOS 트랜지스터(7,8)로 구성된다.In other words, a first PMOS transistor 5 having a source terminal connected to the Vdd power source and a first input signal applied to the gate electrode, and a source terminal connected to the drain terminal of the first PMOS transistor 5 connected to the gate electrode; A second input signal is applied and a second PMOS transistor 6 having a drain terminal as an output terminal, a drain terminal is commonly connected to the drain terminal of the second PMOS transistor 6, and first and second inputs are applied to each gate electrode. A signal is applied and consists of first and second NMOS transistors 7 and 8 whose source terminals are commonly connected to the Vss power supply.
상기와 같이 구성된 NOR 게이트는 제 1, 제 2 PMOS 트랜지스터(5,6)가 직렬로 연결되어 풀-업(Pull-Up) 경로를 형성하며, 제 1, 제 2 NMOS 트랜지스터(7,8)가 병렬연결되어 풀-다운(Pull-Down) 경로를 형성한다.The NOR gate configured as described above has the first and second PMOS transistors 5 and 6 connected in series to form a pull-up path, and the first and second NMOS transistors 7 and 8 are connected to each other. They are connected in parallel to form a pull-down path.
그리고 제 1, 제 2 입력신호의 조합에 의해 출력이 "1"로 존재할 확률이 1/4이고, "0"으로 존재할 확률이 3/4이다.The probability that the output exists as "1" is 1/4 by the combination of the first and second input signals, and the probability that it is present as "0" is 3/4.
따라서 제 1, 제 2 입력신호가 모두 "0"일 때만 "1"이 출력되고, 나머지 경우에는 모두 "1"이 출력된다.Therefore, "1" is output only when both the first and second input signals are "0", and "1" is output in all other cases.
한편, 제 1, 제 2 PMOS 트랜지스터(5,6)가 직렬로 연결되어 있으므로 풀-업 경로의 저항이 증가하기 때문에 NMOS 트랜지스터의 크기 보다 PMOS 트랜지스터의 사이즈를 4배 정도 크게 하여야만 대칭 교환(Symmetric Swting)이 가능하다.On the other hand, since the resistance of the pull-up path increases because the first and second PMOS transistors 5 and 6 are connected in series, the size of the PMOS transistor is increased by about four times the size of the NMOS transistor. Is possible.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자 및 그 제조방법을 설명하면 다음과 같다.Hereinafter, a conventional semiconductor device and a method of manufacturing the same will be described with reference to the accompanying drawings.
도 3은 종래 기술에 의한 도 1의 NAND 게이트 논리회로에서 직렬로 연결된 두 개의 NMOS 트랜지스터를 나타낸 구조단면도이다.3 is a structural cross-sectional view showing two NMOS transistors connected in series in the NAND gate logic circuit of FIG. 1 according to the prior art.
도 3에 도시한 바와같이 필드영역과 활성영역으로 정의된 반도체 기판(11)의 필드영역에 형성되는 필드 산화막(도면에 도시하지 않음)과, 상기 반도체 기판(11)의 활성영역상의 일정영역에 일정한 간격을 갖고 게이트 절연막(12)을 개재하여 형성되는 제 1, 제 2 게이트 전극(13a,13b)과, 상기 제 1, 제 2 게이트 전극(13a,13b)의 양측면에 형성되는 절연막 측벽(16a)과, 상기 제 1, 제 2 게이트 전극(13a,13b) 양측의 반도체 기판(11) 표면내에 LDD 구조로 형성되는 제 1, 제 2, 제 3 고농도 n형 불순물 영역(17a,17b,17c)을 포함하여 구성된다.As shown in FIG. 3, a field oxide film (not shown) formed in a field region of the semiconductor substrate 11 defined as a field region and an active region, and a predetermined region on an active region of the semiconductor substrate 11 are formed. First and second gate electrodes 13a and 13b formed at regular intervals through the gate insulating film 12 and the insulating film sidewalls 16a formed on both sides of the first and second gate electrodes 13a and 13b. ) And first, second and third high concentration n-type impurity regions 17a, 17b and 17c formed in the LDD structure in the surface of the semiconductor substrate 11 on both sides of the first and second gate electrodes 13a and 13b. It is configured to include.
도 4a 내지 도 4e는 종래 기술에 의한 도 1의 NAND 게이트의 논리회로에서 직렬로 연결된 두 개의 NMOS 트랜지스터의 제조방법을 나타낸 공정단면도이다.4A through 4E are cross-sectional views illustrating a method of manufacturing two NMOS transistors connected in series in the logic circuit of the NAND gate of FIG. 1 according to the prior art.
도 4a에 도시한 바와같이 활성영역과 필드영역으로 정의된 반도체 기판(11)의 필드영역에 필드 산화막(도면에는 도시하지 않음)을 형성하고, 상기 반도체 기판(11)의 활성영역에 게이트 절연막(12) 및 게이트 전극용 폴리 실리콘(13)을 형성한다.As shown in FIG. 4A, a field oxide film (not shown) is formed in a field region of the semiconductor substrate 11 defined as an active region and a field region, and a gate insulating film (not shown) is formed in the active region of the semiconductor substrate 11. 12) and polysilicon 13 for the gate electrode.
이어, 상기 폴리 실리콘(13)상에 포토레지스트(Photo Resist)(14)를 도포한 후, 노광 및 현상공정으로 포토레지스트(14)를 패터닝(Patterning)하여 게이트영역을 정의한다.Subsequently, the photoresist 14 is coated on the polysilicon 13, and then the photoresist 14 is patterned by an exposure and development process to define a gate region.
도 4b에 도시한 바와같이 상기 패터닝된 포토레지스트(14)를 마스크로 이용하여 상기 폴리 실리콘(13) 및 게이트 절연막(12)을 선택적으로 제거하여 제 1, 제 2 게이트 전극(13a,13b)을 형성한다.As shown in FIG. 4B, the polysilicon 13 and the gate insulating layer 12 are selectively removed by using the patterned photoresist 14 as a mask to remove the first and second gate electrodes 13a and 13b. Form.
도 4c에 도시한 바와같이 상기 포토레지스트(14)를 제거하고, 상기 제 1, 제 2 게이트 전극(13a,13b)을 마스크로 이용하여 상기 반도체 기판(11)의 전면에 저농도 n형 불순물 이온을 주입하여 상기 제 1, 제 2 게이트 전극(13a,13b)의 양측의 반도체 기판(11) 표면내에 LDD(Lightly Doped Drain) 영역(15)을 형성한다.As shown in FIG. 4C, the photoresist 14 is removed, and low concentration n-type impurity ions are formed on the entire surface of the semiconductor substrate 11 using the first and second gate electrodes 13a and 13b as masks. Implantation forms a lightly doped drain (LDD) region 15 in the surface of the semiconductor substrate 11 on both sides of the first and second gate electrodes 13a and 13b.
도 4d에 도시한 바와같이 상기 제 1, 제 2 게이트 전극(13a,13b)을 포함한 반도체 기판(11)의 전면에 절연막(16)을 형성한다.As shown in FIG. 4D, an insulating film 16 is formed on the entire surface of the semiconductor substrate 11 including the first and second gate electrodes 13a and 13b.
도 4e에 도시한 바와같이 상기 절연막(16)을 에치백(Etch Back)하여 상기 제 1, 제 2 게이트 전극(13a,13b)의 양측면에 절연막 측벽(16a)을 형성한다.As shown in FIG. 4E, the insulating film 16 is etched back to form insulating film sidewalls 16a on both sides of the first and second gate electrodes 13a and 13b.
이어, 상기 제 1, 제 2 게이트 전극(13a,13b) 및 절연막 측벽(16a)을 마스크로 이용하여 고농도 용 고농도 n형 불순물 이온을 주입하여 상기 제 1, 제 2 게이트 전극(13a,13b)의 양측의 반도체 기판(11) 표면내에 상기 LDD 영역(15)과 연결되는 제 1, 제 2, 제 3 고농도 n형 불순물 영역(17a,17b,17c)을 형성한다.Subsequently, a high concentration of high concentration n-type impurity ions are implanted using the first and second gate electrodes 13a and 13b and the insulating film sidewalls 16a as a mask to form the first and second gate electrodes 13a and 13b. First, second and third high concentration n-type impurity regions 17a, 17b and 17c connected to the LDD region 15 are formed in the surfaces of the semiconductor substrate 11 on both sides.
여기서 도면에는 도시하지 않았지만 도 2의 NOR 게이트의 논리회로에서 직렬로 연결된 두 개의 PMOS 트랜지스터도 도 3 및 도 4에 도시된 n형 불순물 대신에 p형 불순물을 주입하는 공정만 다르고 다른 공정이나 구조는 동일하다.Here, although not shown in the drawings, two PMOS transistors connected in series in the logic circuit of the NOR gate of FIG. 2 are also different from the process of implanting p-type impurities instead of the n-type impurities shown in FIGS. 3 and 4. same.
그러나 상기와 같은 종래의 반도체 소자 및 그 제조방법에 있어서 다음과 같은 문제점이 있었다.However, the above conventional semiconductor device and its manufacturing method have the following problems.
첫째, 직렬로 연결된 두 개의 트랜지스터가 동일한 트랜지스터를 이용하여 구성되기 때문에 저전력으로 동작할 경우 오프(Off)상태의 누설전류가 증가하여 전력소모가 늘어난다.First, since two transistors connected in series are configured using the same transistor, when operating at low power, the leakage current in the off state increases to increase power consumption.
둘째, 전력소모를 방지하기 위해서 문턱전압을 증가시킬 경우 오퍼레이팅(Operating) 상태에서 구동전류를 감소함으로써 트랜지스터의 동작속도를 감소시킨다.Second, when the threshold voltage is increased in order to prevent power consumption, the operating speed of the transistor is reduced by decreasing the driving current in the operating state.
셋째, 기판의 농도가 낮기 때문에 문턱전압을 낮춘상태에서 기판전압을 인가하여 오프상태의 누설전류를 감소시킬 수 없다.Third, because the concentration of the substrate is low, it is not possible to reduce the leakage current in the off state by applying the substrate voltage in a state where the threshold voltage is lowered.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 SOI소자와 벌크(Bulk)소자를 직렬로 연결하여 소자의 기판농도를 다르게 하고, 문턱전압은 같지만 기판전압의 변화에 따른 문턱전압의 변화정도를 다르게 하고, 전류 구동 특성을 개선하여 저전압 동작시 소자의 성능향상과 소비전력을 줄이도록 한 반도체 소자 및 그 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems by connecting the SOI device and the bulk device in series to vary the substrate concentration of the device, the threshold voltage is the same, but the degree of change in the threshold voltage according to the change in the substrate voltage The purpose of the present invention is to provide a semiconductor device and a method of manufacturing the same to improve the current driving characteristics and to reduce the performance and power consumption of the device during low voltage operation.
도 1은 일반적인 2-입력 낸드 게이트를 나타낸 논리회로도1 is a logic circuit diagram illustrating a typical two-input NAND gate.
도 2는 일반적인 2-입력 노어 게이트를 나타낸 논리회로도Figure 2 is a logic circuit diagram showing a typical two-input NOR gate
도 3은 종래 기술에 의한 도 1의 NAND 게이트 논리회로에서 직렬로 연결된 두 개의 NMOS 트랜지스터를 나타낸 구조단면도3 is a structural cross-sectional view showing two NMOS transistors connected in series in the NAND gate logic circuit of FIG. 1 according to the related art.
도 4a 내지 도 4e는 종래 기술에 의한 도 1의 NAND 게이트의 논리회로에서 직렬로 연결된 두 개의 NMOS 트랜지스터의 제조방법을 나타낸 공정단면도4A through 4E are cross-sectional views illustrating a method of manufacturing two NMOS transistors connected in series in a logic circuit of the NAND gate of FIG. 1 according to the related art.
도 5는 도 1의 NAND 게이트의 논리회로에서 직렬로 연결된 두 개의 NMOS 트랜지스터를 나타낸 본 발명의 구조단면도5 is a structural cross-sectional view of two NMOS transistors connected in series in the logic circuit of the NAND gate of FIG.
도 6a 내지 도 6h는 본 발명에 의한 도 1의 NAND 게이트의 논리회로에서 직렬로 연결된 두 개의 NMOS 트랜지스터의 제조방법을 나타낸 공정단면도6A through 6H are cross-sectional views illustrating a method of manufacturing two NMOS transistors connected in series in the logic circuit of the NAND gate of FIG. 1 according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
61 : 벌크 기판 62 : 절연층61 bulk substrate 62 insulation layer
63 : 반도체층 65a : 소자 격리영역63 semiconductor layer 65a device isolation region
66 : 제 1 게이트 전극 67 : 제 2 게이트 전극66: first gate electrode 67: second gate electrode
66a,66b : 제 1 소오스/드레인 불순물 영역66a, 66b: first source / drain impurity region
67a.67b : 제 2 소오스/드레인 불순물 영역67a.67b: second source / drain impurity region
69 : 사이드월 스페이서69: sidewall spacer
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자는 벌크 기판, 상기 기판상의 소정부위에 형성된 절연층, 상기 절연층상에 형성된 반도체층, 상기 절연층이 형성되지 않은 상기 기판상의 소정부위에 게이트 절연막을 개재하여 형성된 제 1 게이트 전극, 상기 반도체층상에 소정부위에 게이트 절연막을 개재하여 형성된 제 2 게이트 전극, 상기 제 1 게이트 전극 양측의 상기 기판내에 형성된 제 1 소오스/드레인 불순물 영역, 상기 제 2 게이트 전극 양측의 상기 반도체층내에 형성된 제 2 소오스/드레인 불순물 영역을 포함하여 구성되고, 본 발명의 반도체 소자 제조방법은 SOI기판의 반도체층과 절연층을 소정부분 제거하여 벌크소자가 형성될 영역의 벌크 기판을 노출시키는 공정, 상기 벌크 기판상에 상기 절연층과 식각선택비가 큰 절연막을 채우는 공정, 상기 SOI기판의 반도체층을 소정부분 제거하고, 상기 반도체층과 인접하지 않는 상기 벌크 기판을 소정깊이로 제거하는 공정, 상기 반도체층이 제거된 부분과 상기 벌크 기판이 소정깊이로 제거된 부분에 소자격리막을 형성하는 공정, 상기 절연막 제거하여 상기 벌크 기판을 노출시키는 공정, 상기 노출된 벌크 기판상의 소정부위에 제 1 게이트 전극을 형성하고, 상기 반도체층상의 소정부위에 제 2 게이트 전극을 형성하는 공정, 상기 제 1 게이트 전극 양측의 상기 기판내에 제 1 소오스/드레인 불순물 영역을 형성하고, 상기 제 2 게이트 전극 양측의 상기 반도체층내에 제 2 소오스/드레인 불순물 영역을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.A semiconductor device according to the present invention for achieving the above object is a bulk substrate, an insulating layer formed on a predetermined portion on the substrate, a semiconductor layer formed on the insulating layer, a gate on a predetermined portion on the substrate where the insulating layer is not formed A first gate electrode formed through an insulating film, a second gate electrode formed through a gate insulating film on a predetermined portion on the semiconductor layer, a first source / drain impurity region formed in the substrate on both sides of the first gate electrode, and the second And a second source / drain impurity region formed in the semiconductor layer on both sides of the gate electrode. The semiconductor device manufacturing method of the present invention removes a predetermined portion of the semiconductor layer and the insulating layer of the SOI substrate, thereby removing the portion of the region where the bulk element is to be formed. Exposing a bulk substrate; an insulating film having a large etching selectivity with the insulating layer on the bulk substrate A step of filling, removing a predetermined portion of the semiconductor layer of the SOI substrate, and removing the bulk substrate that is not adjacent to the semiconductor layer to a predetermined depth, wherein the portion from which the semiconductor layer is removed and the bulk substrate are removed to a predetermined depth Forming a device isolation film in a portion; removing the insulating film to expose the bulk substrate; forming a first gate electrode at a predetermined portion on the exposed bulk substrate; and forming a second gate electrode at a predetermined portion on the semiconductor layer. Forming a first source / drain impurity region in the substrate on both sides of the first gate electrode, and forming a second source / drain impurity region in the semiconductor layer on both sides of the second gate electrode. Characterized in that made.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자 및 그 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
도 5는 본 발명에 따른 반도체 소자의 구조단면도로써, 도 1에 도시된 NAND논리회로에서 직렬로 연결된 두 개의 NMOS 트랜지스터를 나타낸 것이다.FIG. 5 is a structural cross-sectional view of a semiconductor device according to the present invention, which shows two NMOS transistors connected in series in the NAND logic circuit shown in FIG. 1.
도 5에 도시한 바와 같이, 벌크 기판(61), 상기 기판(61)상의 소정부위에 형성된 절연층(62), 상기 절연층(62)상에 형성된 반도체층(63), 상기 절연층(62)이 형성되지 않은 상기 기판(61)상의 소정부위에 게이트 절연막을 개재하여 형성된 제 1 게이트 전극(66), 상기 반도체층(63)상에 소정부위에 게이트 절연막을 개재하여 형성된 제 2 게이트 전극(67), 상기 제 1 게이트 전극(66) 양측의 상기 기판(61)내에 형성된 제 1 소오스/드레인 불순물 영역(66a,66b), 상기 제 2 게이트 전극(67) 양측의 상기 반도체층(63)내에 형성된 제 2 소오스/드레인 불순물 영역(67a,67b)을 포함하여 구성된다.As shown in FIG. 5, a bulk substrate 61, an insulating layer 62 formed on a predetermined portion on the substrate 61, a semiconductor layer 63 formed on the insulating layer 62, and the insulating layer 62. ) Is a first gate electrode 66 formed on a predetermined portion on the substrate 61 without a gate insulating film, and a second gate electrode formed on the semiconductor layer 63 via a gate insulating film on a predetermined portion. 67, first source / drain impurity regions 66a and 66b formed in the substrate 61 on both sides of the first gate electrode 66, and in the semiconductor layer 63 on both sides of the second gate electrode 67. And the second source / drain impurity regions 67a and 67b formed.
여기서, 상기 벌크 기판(61)상에 형성된 제 1 게이트 전극(66)과, 제 1 소오스/드레인 불순물 영역(66a,66b)에 의해 벌크 소자가 구현되고, 상기 제 2 게이트 전극(67)과, 제 2 소오스/드레인 불순물 영역(67a,67b)에 의해 SOI소자가 구현된다.Here, a bulk device is implemented by the first gate electrode 66 and the first source / drain impurity regions 66a and 66b formed on the bulk substrate 61, the second gate electrode 67, The SOI element is implemented by the second source / drain impurity regions 67a and 67b.
이와 같이, 벌크 기판과 SOI기판상에 각각 벌크 소자와 SOI소자를 구성하는데, NAND 논리회로의 Vss와 NOR 논리회로의 Vdd에 인접한 소자는 벌크 기판상에 구성하고, 팬-인(FAN-IN) 또는 팬-아웃(FAN-OUT)과 연결되는 소자는 SOI기판상에 구성한다.As such, the bulk and SOI elements are formed on the bulk and SOI substrates, respectively. The elements adjacent to Vss of the NAND logic circuit and Vdd of the NOR logic circuit are configured on the bulk substrate, and are fan-in (FAN-IN). Alternatively, the device connected to the fan-out is configured on the SOI substrate.
이때, 벌크 소자와 SOI소자가 동일한 문턱전압을 갖도록 컨트롤한다.At this time, the bulk device and the SOI device are controlled to have the same threshold voltage.
이와 같이 구성된 본 발명의 반도체 소자 제조방법을 첨부된 도면을 참조하여 보다 상세히 설명하기로 한다.The semiconductor device manufacturing method of the present invention configured as described above will be described in more detail with reference to the accompanying drawings.
도 6a 내지 6i는 본 발명의 반도체 소자 제조방법을 설명하기 위한 공정단면도이다.6A to 6I are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.
도 6a에 도시한 바와 같이, 벌크 기판(61)상에 제 1 절연층(62)을 형성하고, 제 1 절연층(62)상에 반도체층(63)을 형성한다.As shown in FIG. 6A, the first insulating layer 62 is formed on the bulk substrate 61, and the semiconductor layer 63 is formed on the first insulating layer 62.
여기서, 제 1 절연층(62)은 실리콘 질화막을 적용한다.Here, the silicon nitride film is applied to the first insulating layer 62.
이후, 반도체층(63)상에 포토레지스트(도시하지 않음)를 도포한 후, 노광 및 현상공정으로 패터닝한 후, 도 6b에 도시한 바와 같이, 상기 반도체층(63) 및 제 1 절연층(62)을 차례로 식각하여 기판(61)의 표면을 소정부분 노출시켜 벌크 소자가 형성될 영역을 정의한다.Thereafter, a photoresist (not shown) is applied on the semiconductor layer 63, and then patterned by an exposure and development process, and as shown in FIG. 6B, the semiconductor layer 63 and the first insulating layer ( 62 is sequentially etched to expose a portion of the surface of the substrate 61 to define a region where a bulk element is to be formed.
이어서, 노출된 기판(61)을 포함한 반도체층(63)상에 제 2 절연층(64)을 형성한 후, 도 6c에 도시한 바와 같이, 평탄화 공정을 수행한다.Subsequently, after the second insulating layer 64 is formed on the semiconductor layer 63 including the exposed substrate 61, the planarization process is performed as shown in FIG. 6C.
상기 제 2 절연층(64)의 물질은 실리콘 산화막과 식각선택비가 큰 실리콘 질화막이다.The material of the second insulating layer 64 is a silicon nitride film and a silicon nitride film having a large etching selectivity.
이후, 도 6d에 도시한 바와 같이, 상기 제 1 절연층(62)이 노출되도록 반도체층(63)을 소정부분 제거하고, 동시에 상기 벌크 소자가 형성될 영역의 제 2 절연층(64)의 소정부위와 그 하부의 기판(61)을 소정깊이까지 제거한다.Thereafter, as shown in FIG. 6D, a predetermined portion of the semiconductor layer 63 is removed to expose the first insulating layer 62, and at the same time, a predetermined portion of the second insulating layer 64 in the region where the bulk element is to be formed. The part 61 and its lower substrate 61 are removed to a predetermined depth.
이때, 벌크 소자가 형성될 영역에서 기판(61)이 소정깊이까지 식각될 때, SOI소자가 형성될 영역에서는 상기 반도체층(63)만이 제거되는데, 이는 반도체층(63)과 상기 제 2 절연층(64) 및 기판(61)의 식각선택비가 크기 때문이다.At this time, when the substrate 61 is etched to a predetermined depth in the region where the bulk element is to be formed, only the semiconductor layer 63 is removed in the region where the SOI element is to be formed, which is the semiconductor layer 63 and the second insulating layer. This is because the etching selectivity of the 64 and the substrate 61 is large.
이어서, 기판(61)을 포함한 전면에 제 3 절연층(65)을 형성한 후, 평탄화 공정을 수행하면, 도 6e에 도시한 바와 같이, 상기 기판이 식각된 부분과 상기 반도체층(63)이 제거된 부분에 소자 격리영역(65a)이 형성된다.Subsequently, after the third insulating layer 65 is formed on the entire surface including the substrate 61, the planarization process is performed. As shown in FIG. 6E, the portion where the substrate is etched and the semiconductor layer 63 are formed. An element isolation region 65a is formed in the removed portion.
이어, 도 6f에 도시한 바와 같이, 상기 제 2 절연층(64)만을 선택적으로 식각하여 벌크소자가 형성될 기판(61)의 표면을 노출시킨다.6F, only the second insulating layer 64 is selectively etched to expose the surface of the substrate 61 on which the bulk device is to be formed.
그리고 반도체층(63)과 상기 노출된 기판(61)내에 채널 이온주입을 실시한다.Channel ion implantation is performed in the semiconductor layer 63 and the exposed substrate 61.
도 6g에 도시한 바와 같이, 게이트 절연물질과 게이트 전극 물질을 차례로 증착한 후, 상기 기판(61)상의 소정부위와 상기 반도체층(63)상의 소정부위에만 남도록 패터닝하여 제 1, 제 2 게이트 전극(66,67)을 형성한다.As shown in FIG. 6G, the gate insulating material and the gate electrode material are sequentially deposited, and then patterned so that only a predetermined portion on the substrate 61 and a predetermined region on the semiconductor layer 63 remain to form the first and second gate electrodes. (66,67).
그리고 제 1, 제 2 게이트 전극(66,67)을 마스크로 이용한 이온주입으로 LDD영역(68)들을 형성한다.The LDD regions 68 are formed by ion implantation using the first and second gate electrodes 66 and 67 as masks.
도 6h에 도시한 바와 같이, 상기 제 1, 제 2 게이트 전극(66,67)들의 양측면에 사이드월 스페이서(side spacer)(69)를 형성한 후, 고농도의 소오스/드레인용 불순물 이온주입을 실시하여 벌크 소자용 제 1 소오스/드레인 불순물 영역(66a,66b)과 SOI소자용 제 2 소오스/드레인 불순물 영역(67a,67b)을 형성한다.As shown in FIG. 6H, sidewall spacers 69 are formed on both sides of the first and second gate electrodes 66 and 67, and then high concentration source / drain impurity ions are implanted. The first source / drain impurity regions 66a and 66b for the bulk elements and the second source / drain impurity regions 67a and 67b for the SOI elements are formed.
여기서, 상기 제 1 게이트 전극(66)은 벌크 소자용 게이트 전극이고, 제 2 게이트 전극(67)은 SOI소자용 게이트 전극이다.Here, the first gate electrode 66 is a bulk electrode gate electrode, and the second gate electrode 67 is a SOI element gate electrode.
이와 같은 공정에 의해 벌크 소자와 SOI소자가 결합된 CMOS회로를 구현한다.By such a process, a CMOS circuit combining a bulk device and an SOI device is realized.
여기서, 상기 기판(61)에 형성된 제 1 소오스/드레인 불순물 영역(66a,66b)과 제 1 게이트 전극(66)에 의해 벌크 소자가 구현되는데, 상기 벌크 소자는 도 1에 도시된 NAND회로에서 접지전압단에 연결된 앤모스 트랜지스터로 사용하거나 또는 도 2에 도시된 NOR회로에서 전원전압단에 연결된 피모스 트랜지스터로 사용할 수 있다.Here, a bulk device is implemented by the first source / drain impurity regions 66a and 66b and the first gate electrode 66 formed on the substrate 61. The bulk device is grounded in the NAND circuit shown in FIG. It may be used as an NMOS transistor connected to a voltage terminal or as a PMOS transistor connected to a power supply voltage terminal in the NOR circuit shown in FIG. 2.
이상 상술한 바와 같이, 본 발명의 반도체 소자 및 그 제조방법은 다음과 같은 효과가 있다.As described above, the semiconductor device of the present invention and its manufacturing method have the following effects.
NAND회로의 앤모스 트랜지스터와 NOR회로의 피모스 트랜지스터를 직렬로 연결함에 있어서, NAND회로의 접지전압(Vss)단과 NOR회로의 전원전압(Vdd)에 가까이 위치한 소자를 벌크 기판상에 구성하고, 팬-인(FAN-IN)이나 팬-아웃(FAN-OUT)과 연결되는 SOI소자는 SOI기판상에 구성하여 상기 벌크 소자와 동일한 문턱전압을 갖도로 제작한다.In connecting the NMOS transistor PMOS transistor and the NOR circuit PMOS transistor in series, an element located near the ground voltage (Vss) terminal of the NAND circuit and the power supply voltage (Vdd) of the NOR circuit is formed on the bulk substrate, and the fan The SOI device connected to the FAN-IN or the FAN-OUT is fabricated on the SOI substrate to have the same threshold voltage as the bulk device.
따라서, NAND회의 앤모스 트랜지스터와 NOR회로의 피모스 트랜지스터를 구성하는 n개의 소자를 직렬로 구성하여 회로의 동작시는 로딩(loading)커패시턴스가 작은 SOI소자로 인해 고속으로 동작하고, 반면에 오프(off)상태에서는 Vdd혹은 Vss에 연결된 벌크 소자에 기판 전압을 인가하여 문턱전압을 높여주므로써, 누설전류를 감소시키므로 고속과 저전력을 동시에 만족할 수가 있다.Therefore, the NAND transistor NMOS transistor and the N element constituting the PMOS transistor of the NOR circuit are configured in series so that the operation of the circuit operates at high speed due to the SOI element having a small loading capacitance. In the off state, the substrate voltage is applied to the bulk device connected to Vdd or Vss to increase the threshold voltage, thereby reducing leakage current, thereby satisfying high speed and low power.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100434955B1 (en) * | 2001-11-28 | 2004-06-09 | 주식회사 하이닉스반도체 | CMOS of semiconductor device and method for manufacturing the same |
| CN113571586A (en) * | 2021-07-12 | 2021-10-29 | 沈阳工业大学 | Double-doped source-drain single-transistor XNOR gate and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100434955B1 (en) * | 2001-11-28 | 2004-06-09 | 주식회사 하이닉스반도체 | CMOS of semiconductor device and method for manufacturing the same |
| CN113571586A (en) * | 2021-07-12 | 2021-10-29 | 沈阳工业大学 | Double-doped source-drain single-transistor XNOR gate and manufacturing method thereof |
| CN113571586B (en) * | 2021-07-12 | 2023-09-19 | 沈阳工业大学 | Double-doped source-drain single transistor exclusive-or gate and manufacturing method thereof |
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