CN113571586A - Double-doped source-drain single-transistor XNOR gate and manufacturing method thereof - Google Patents
Double-doped source-drain single-transistor XNOR gate and manufacturing method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
Abstract
The invention discloses a double-doped source-drain single transistor XNOR gate and a manufacturing method thereof, wherein two subareas with donor doping and acceptor doping are formed on a source region and a drain region of the transistor, when two signal input ends input high level or low level simultaneously, the double-doped source-drain single transistor XNOR gate is in an electron conduction state or a hole conduction state, so that high level output is realized, when one of the two signal input ends is in high level and the other is in low level, the double-doped source-drain single transistor XNOR gate is in an electron blocking state and a hole blocking state, so that low level output is realized, and the double-doped source-drain single transistor can realize XNOR gate logic only through a single transistor per se, so that the complexity of the XNOR gate is greatly reduced.
Description
Technical Field
The invention relates to the technical field of CMOS integrated circuit design and manufacture, in particular to a double-doped source-drain single-transistor XNOR gate suitable for the high-integration low-power-consumption CMOS integrated circuit design and manufacture technology and a manufacture method thereof.
Background
Based on the existing CMOS field effect transistor technology, on the premise that the integration process is determined, the larger the number of transistors used in the design is, the larger the chip area required to be occupied for realizing the function is. The existing exclusive-or gate based on the prior art usually needs to be implemented by connecting an inverter composed of 2 transistors and utilizing an exclusive-or gate composed of 4 or more complementary metal oxide semiconductor field effect transistors, and negating the exclusive-or gate logic, so that at least 6 or more transistors are needed, the implementation of the exclusive-or gate logic by utilizing fewer transistors helps to further simplify the unit structure of the basic gate circuit of the integrated circuit, and more exclusive-or gates are implemented on the same integrated process technology and the same chip area to improve the integration level.
Disclosure of Invention
The invention aims to provide a double-doped source-drain single-transistor XNOR gate and a manufacturing method thereof, so that an integrated circuit can realize the logic function of the XNOR gate by using the minimum number of transistors, namely a single transistor.
In order to achieve the purpose, the invention provides the following technical scheme: the double-doped source-drain single-transistor XNOR gate comprises a silicon substrate of an SOI wafer, wherein a substrate insulating layer of the SOI wafer is arranged above the silicon substrate of the SOI wafer, the substrate insulating layer of the SOI wafer is an insulating material layer, and a semiconductor thin film region, an interchangeable N-type source-drain region a, an interchangeable P-type source-drain region a, an interchangeable N-type source-drain region b, an interchangeable P-type source-drain region b, an insulating medium layer, a gate electrode insulating layer, a gate electrode a and a gate electrode b are arranged above the substrate insulating layer of the SOI wafer; the semiconductor thin film region is made of semiconductor materials, and the left side and the right side of the upper surface and the front side and the rear side of the semiconductor thin film region are in mutual contact with the gate electrode insulating layer; the central parts of the upper surface and the front and back side surfaces of the semiconductor film region are in contact with the insulating medium layer;
the interchangeable N-type source drain region a and the interchangeable P-type source drain region a are semiconductor regions doped with N-type impurities and P-type impurities respectively; the interchangeable N-type source drain region a and the interchangeable P-type source drain region a are positioned on the left side of the semiconductor thin film region and are in contact with the semiconductor thin film region;
the front side surface of the interchangeable N-type source drain region a and the rear side surface of the interchangeable P-type source drain region a are in contact with the insulating medium layer; the back side surface of the interchangeable N-type source drain region a and the front side surface of the interchangeable P-type source drain region a are in mutual contact with the anti-depletion isolation layer a; the anti-depletion isolation layer a is made of an insulating dielectric material;
the left sides of the upper surfaces of the interchangeable N-type source drain region a and the interchangeable P-type source drain region a are mutually contacted with the interchangeable source drain electrode a, and the right sides of the upper surfaces of the interchangeable N-type source drain region a and the interchangeable P-type source drain region a are mutually contacted with the insulating medium layer;
the interchangeable N-type source drain region b and the interchangeable P-type source drain region b are semiconductor regions doped with N-type impurities and P-type impurities respectively; the interchangeable N-type source drain region b and the interchangeable P-type source drain region b are positioned on the right side of the semiconductor thin film region and are in contact with the semiconductor thin film region;
the front side surface of the interchangeable N-type source drain region b and the rear side surface of the interchangeable P-type source drain region b are in contact with the insulating medium layer; the back side surface of the interchangeable N-type source drain region b and the front side surface of the interchangeable P-type source drain region b are in contact with the depletion-preventing isolation layer b; the anti-depletion isolation layer b is made of an insulating dielectric material;
the front side surface and the rear side surface of the interchangeable N-type source drain region b and the interchangeable P-type source drain region b are mutually contacted with the insulating medium layer, the right side of the upper surface of the interchangeable N-type source drain region b and the interchangeable P-type source drain region b is mutually contacted with the interchangeable source drain electrode b, and the left side of the upper surface of the interchangeable N-type source drain region b and the interchangeable P-type source drain region b is mutually contacted with the insulating medium layer;
the insulating medium layer is made of insulating medium materials; the gate electrode insulating layer is made of an insulating dielectric material, and the upper surface and the front and back side surfaces of the left side part of the gate electrode insulating layer are in contact with the gate electrode a; the upper surface and front and rear side surfaces of the right portion of the gate electrode insulating layer and the gate electrode b are in contact with each other; the gate electrode a and the gate electrode b are metal, alloy, polycrystalline silicon or metal silicide; the gate electrode a is in mutual contact with the upper surface and the front and back side surfaces of the left side part of the gate electrode insulating layer, the gate electrode a is insulated and isolated from the semiconductor film region through the gate electrode insulating layer, and the gate electrode a is insulated and isolated from the interchangeable source drain electrode a and the interchangeable source drain electrode b through the insulating medium layer; the gate electrode b is in mutual contact with the upper surface and the front and back side surfaces of the right side part of the gate electrode insulating layer, the gate electrode b is insulated and isolated from the semiconductor film region through the gate electrode insulating layer, and the gate electrode b is insulated and isolated from the interchangeable source drain electrode a and the interchangeable source drain electrode b through the insulating medium layer; the gate electrode a and the gate electrode b are insulated and isolated from each other through an insulating medium layer; the interchangeable source drain electrode a is made of metal, alloy or metal silicide, the lower surface of the interchangeable source drain electrode a is in mutual contact with the left sides of the upper surfaces of the interchangeable N-type source drain region a and the interchangeable P-type source drain region a, and an ohmic type anti-blocking layer is formed for contact; the interchangeable source drain electrode b is made of metal, alloy or metal silicide, and the lower surface of the interchangeable source drain electrode b is in contact with the right sides of the upper surfaces of the interchangeable N-type source drain region b and the interchangeable P-type source drain region b to form ohmic type anti-blocking layer contact.
Compared with the prior art, the invention has the beneficial effects that:
1. the realized exclusive OR gate has simple structure
According to the double-doped source-drain single transistor XNOR gate and the manufacturing method thereof, the circuit can realize XNOR gate logic only by one transistor with the double-doped source-drain structure, so that the complexity of the XNOR gate structure is greatly simplified, and the integrated circuit integration level is easy to improve.
2. The logic transmission function of the bidirectional exclusive OR gate can be realized:
the double-doped source-drain single-transistor XNOR gate and the manufacturing method thereof have the structural characteristics of bilateral symmetry, the interchangeable source-drain electrode a and the interchangeable source-drain electrode b can be interchanged with each other, namely, any one end of the interchangeable source-drain electrode a and the interchangeable source-drain electrode b is connected with a power supply voltage input end, and the other end of the interchangeable source-drain electrode a and the interchangeable source-drain electrode b are connected with an output end of the XNOR gate to output the XNOR gate.
Drawings
FIG. 1 is a top view of a dual doped source drain single transistor XNOR gate of the present invention;
FIG. 2 is a cross-sectional view of the NOR gate of the double-doped source-drain single transistor of the present invention along the dotted line A of FIG. 1;
FIG. 3 is a cross-sectional view of the NOR gate of the dual-doped source-drain single transistor of the present invention along the dotted line B of FIG. 1;
FIG. 4 is a cross-sectional view of the NOR gate of the double-doped source-drain single transistor of the present invention along the dotted line C of FIG. 1;
FIG. 5 is a cross-sectional view of the NOR gate of the double-doped source-drain single transistor of the present invention along the dotted line D of FIG. 1;
FIG. 6 is a circuit diagram of a dual doped source drain single transistor XNOR gate of the present invention.
FIG. 7 is a top view of step one;
FIG. 8 is a cross-sectional view along dotted line A of step one;
FIG. 9 is a cross-sectional view taken along dotted line B of step one;
FIG. 10 is a top view of step two;
FIG. 11 is a cross-sectional view taken along dotted line A in step two;
FIG. 12 is a cross-sectional view taken along the dashed line B in step two;
FIG. 13 is a cross-sectional view taken along the dashed line C in step two;
FIG. 14 is a cross-sectional view taken along the dashed line D in step two;
FIG. 15 is a top view of step three;
FIG. 16 is a cross-sectional view taken along dotted line A of step three;
FIG. 17 is a cross-sectional view taken along dotted line B of step three;
FIG. 18 is a cross-sectional view taken along dotted line C of step three;
FIG. 19 is a cross-sectional view taken along dotted line D of step three;
FIG. 20 is a cross-sectional view taken along dotted line E of step three;
FIG. 21 is a top view of step four;
FIG. 22 is a cross-sectional view taken along dotted line A of step four;
FIG. 23 is a top view of step five;
FIG. 24 is a cross-sectional view taken along dotted line A of step five;
FIG. 25 is a cross-sectional view taken along dotted line B of step five;
FIG. 26 is a cross-sectional view taken along dotted line C of step five;
FIG. 27 is a cross-sectional view taken along dotted line D of step five;
FIG. 28 is a cross-sectional view taken along dashed line E of step five;
FIG. 29 is a top view of step six;
FIG. 30 is a sectional view taken along the dashed line A in step six;
FIG. 31 is a sectional view taken along the broken line B in step six;
FIG. 32 is a cross-sectional view taken along dotted line C of step six;
FIG. 33 is a cross-sectional view taken along dotted line D of step six;
FIG. 34 is a top view of step seven;
FIG. 35 is a cross-sectional view taken along dotted line A of step seven;
FIG. 36 is a cross-sectional view taken along dotted line B of step seven;
FIG. 37 is a cross-sectional view taken along dashed line C of step seven;
FIG. 38 is a top view of step eight;
FIG. 39 is a cross-sectional view taken along dotted line A of step eight;
FIG. 40 is a cross-sectional view taken along dotted line B of step eight;
FIG. 41 is a cross-sectional view taken along dotted line C of step eight;
FIG. 42 is a cross-sectional view taken along dashed line D of step eight;
FIG. 43 is a top view of step nine;
FIG. 44 is a cross-sectional view taken along dotted line A of step nine;
FIG. 45 is a cross-sectional view taken along dotted line B of step nine;
FIG. 46 is a cross-sectional view taken along dotted line C of step nine;
FIG. 47 is a cross-sectional view taken along dashed line D of step nine;
FIG. 48 is a cross-sectional view taken along dashed line E of step nine;
FIG. 49 is a cross-sectional view taken along dashed line E of step nine;
FIG. 50 is a cross-sectional view taken along dashed line E of step nine;
1. a silicon substrate of an SOI wafer; 2. a substrate insulating layer of an SOI wafer; 3. a semiconductor thin film region; 4. the N-type source drain region a can be exchanged; 5. the P-type source drain region a can be exchanged; 6. the N-type source drain region b can be exchanged; 7. the P-type source drain region b can be exchanged; 8. an insulating dielectric layer; 9. a gate electrode insulating layer; 10. a gate electrode a; 11. a gate electrode b; 12. the source electrode and the drain electrode a can be exchanged; 13. the source electrode and the drain electrode can be exchanged; 14. an anti-depletion isolation layer a; 15. an anti-depletion isolation layer b; 16. a signal input terminal A; 17. and a signal input terminal B; 18. a supply voltage input; 19. and an exclusive OR gate output terminal.
Detailed Description
Referring to fig. 1-5, the present invention provides a technical solution: the double-doped source-drain single transistor XNOR gate comprises a silicon substrate 1 of an SOI wafer, and is characterized in that: a substrate insulating layer 2 of the SOI wafer is arranged above a silicon substrate 1 of the SOI wafer, the substrate insulating layer 2 of the SOI wafer is an insulating material layer, and a semiconductor thin film region 3, an interchangeable N-type source-drain region a4, an interchangeable P-type source-drain region a5, an interchangeable N-type source-drain region b6, an interchangeable P-type source-drain region b7, an insulating medium layer 8, a gate electrode insulating layer 9, a gate electrode a10 and a gate electrode b11 are arranged above the substrate insulating layer 2 of the SOI wafer; the semiconductor thin film region 3 is made of a semiconductor material, and the left and right sides of the upper surface and the front and rear side surfaces of the semiconductor thin film region 3 are in contact with the gate electrode insulating layer 9; the upper surface and the central portions of the front and rear side surfaces of the semiconductor thin film region 3 are in contact with the insulating dielectric layer 8; the interchangeable N-type source drain region a4 and the interchangeable P-type source drain region a5 are semiconductor regions doped with N-type impurities and P-type impurities respectively; the interchangeable N-type source drain region a4 and the interchangeable P-type source drain region a5 are positioned on the left side of the semiconductor thin film region 3 and are in contact with the semiconductor thin film region 3; the front side surface of the interchangeable N-type source drain region a4 and the back side surface of the interchangeable P-type source drain region a5 are in contact with the insulating medium layer 8; the back side surface of the interchangeable N-type source drain region a4 and the front side surface of the interchangeable P-type source drain region a5 are in contact with the anti-depletion isolation layer a 14; the anti-depletion isolation layer a14 is an insulating dielectric material; the left sides of the upper surfaces of the interchangeable N-type source drain region a4 and the interchangeable P-type source drain region a5 are mutually contacted with the interchangeable source drain electrode a12, and the right sides of the upper surfaces of the interchangeable N-type source drain region a4 and the interchangeable P-type source drain region a5 are mutually contacted with the insulating medium layer 8; the interchangeable N-type source drain region b6 and the interchangeable P-type source drain region b7 are semiconductor regions doped with N-type impurities and P-type impurities respectively; the interchangeable N-type source drain region b6 and the interchangeable P-type source drain region b7 are positioned on the right side of the semiconductor thin film region 3 and are in contact with the semiconductor thin film region 3; the front side surface of the interchangeable N-type source drain region b6 and the back side surface of the interchangeable P-type source drain region b7 are in contact with the insulating medium layer 8; the back side surface of the interchangeable N-type source drain region b6 and the front side surface of the interchangeable P-type source drain region b7 are in contact with the anti-depletion isolation layer b 15; the anti-depletion isolation layer b15 is an insulating dielectric material; the right sides of the upper surfaces of the interchangeable N-type source drain region b6 and the interchangeable P-type source drain region b7 are mutually contacted with the interchangeable source drain electrode b13, and the left sides of the upper surfaces of the interchangeable N-type source drain region b6 and the interchangeable P-type source drain region b7 are mutually contacted with the insulating medium layer 8; the insulating medium layer 8 is made of insulating medium materials; the gate electrode insulating layer 9 is an insulating dielectric material, and the upper surface and front and rear side surfaces of the left side portion of the gate electrode insulating layer 9 and the gate electrode a10 are in contact with each other; the upper surface and front and rear side surfaces of the right portion of the gate electrode insulating layer 9 and the gate electrode b11 are in contact with each other; the gate electrode a10 and the gate electrode b11 are metal, alloy, polysilicon, or metal silicide; the gate electrode a10 is in contact with the upper surface and the front and rear side surfaces of the left side portion of the gate electrode insulating layer 9, the gate electrode a10 is insulated and isolated from the semiconductor thin film region 3 by the gate electrode insulating layer 9, and the gate electrode a10 is insulated and isolated from the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode b13 by the insulating dielectric layer 8; the gate electrode b11 is in contact with the upper surface and the front and rear side surfaces of the right side portion of the gate electrode insulating layer 9, the gate electrode b11 is insulated from the semiconductor thin film region 3 by the gate electrode insulating layer 9, and the gate electrode b11 is insulated from the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode b13 by the insulating dielectric layer 8; the gate electrode a10 and the gate electrode b11 are insulated and isolated from each other by an insulating dielectric layer 8; the interchangeable source-drain electrode a12 is made of metal, alloy or metal silicide, the lower surface of the interchangeable source-drain electrode a12 is in contact with the left sides of the upper surfaces of the interchangeable N-type source-drain region a4 and the interchangeable P-type source-drain region a5 to form ohmic-type anti-blocking layer contact; the interchangeable source-drain electrode b13 is made of metal, alloy or metal silicide, and the lower surface of the interchangeable source-drain electrode b13 is in contact with the right sides of the upper surfaces of the interchangeable N-type source-drain region b6 and the interchangeable P-type source-drain region b7 to form ohmic-type anti-blocking layer contact.
As shown in fig. 6, the present invention further provides a method for using a dual-doped source-drain single-transistor nor gate, in which a gate electrode a10 is connected to one of two signal input terminals of the nor gate, i.e., a signal input terminal a16 and a signal input terminal B17, while a gate electrode B11 is connected to the other of the two signal input terminals of the nor gate, i.e., the signal input terminal a16 and the signal input terminal B17, which is connected to the gate electrode a 10; the interchangeable source-drain electrode a12 is interconnected with one of the supply voltage input terminal 18 and the exclusive-or gate output terminal 19, while the interchangeable source-drain electrode b13 is interconnected with the other of the supply voltage input terminal 18 and the exclusive-or gate output terminal 19 than the interchangeable source-drain electrode a 12.
When the signal input terminal a16 and the signal input terminal B17 simultaneously input a high level, the gate electrode a10 and the gate electrode B11 are simultaneously at a high potential, and when the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13 are respectively connected to one of the power supply voltage input terminal 18 and the exclusive-or gate output terminal 19, the semiconductor thin film region 3, under the combined action of the gate electrode a10 and the gate electrode B11, internally forms an electron channel by an electric field effect, so that electrons can flow from the end of the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13, which is at a lower potential, to the end of the interchangeable N-type source-drain region a4 and the interchangeable N-type source-drain region B6, which is also at a lower potential, and flow through the electron channel formed inside the semiconductor thin film region 3 to the end of the interchangeable N-type source-drain region a4 and the interchangeable N-source-drain region B6, which is at a higher potential, and then flow from the end of the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13, which is at a higher potential, the same or gate of the double-doped source drain single transistor is in a low-resistance state at the moment, and a high level is output to an output end 19 of the same or gate; when the signal input terminal a16 and the signal input terminal B17 are simultaneously inputted with a low level, the gate electrode a10 and the gate electrode B11 are simultaneously at a low level, and when the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13 are respectively connected to one of the power supply voltage input terminal 18 and the or gate output terminal 19, the semiconductor thin film region 3 internally forms a hole channel by an electric field effect under the combined action of the gate electrode a10 and the gate electrode B11, so that holes can flow from the end of the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13 which are at a higher potential to the end of the interchangeable P-type source-drain region a5 and the interchangeable P-type source-drain region B7 which are also at a higher potential, and flow to the end of the interchangeable P-type source-drain region a5 and the interchangeable N-type source-drain region B6 which are at a lower potential through the hole channel formed inside the semiconductor thin film region 3, and then flow from the end of the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13 which are at a lower potential, the same or gate of the double-doped source drain single transistor is in a low-resistance state at the moment, and a high level is output to an output end 19 of the same or gate; when one of the signal input terminal a16 and the signal input terminal B17 is inputted with a high level and the other is inputted with a low level, and when the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13 are connected to one of the power supply voltage input terminal 18 and the exclusive-nor output terminal 19, respectively, one of the gate electrode a10 and the gate electrode B11 is at a high level and the other is at a low level, one of the gate electrode a10 and the gate electrode B11 at a high level may block "holes" from flowing from the one of the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13 at a higher potential to the one of the lower potential by electric field effect, one of the gate electrode a10 and the gate electrode B11 at a low level may block "electrons" from flowing from the one of the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode B13 at a lower potential to the one of the lower potential by electric field effect, and the double-doped source-drain single crystal transistor or the gate is in a high resistance state, a low level is output to the exclusive or gate output terminal 19.
The circuit can realize the same-OR gate logic only by one transistor with a double-doped source-drain structure, the structure is symmetrical left and right, the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode b13 can be interchanged with each other, any one end of the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode b13 is connected with the power supply voltage input end 18, and the other end of the interchangeable source-drain electrode a12 and the interchangeable source-drain electrode b13 are connected with the same-OR gate output end 19 to output the same-OR gate.
The invention also provides a manufacturing method of the double-doped source-drain single transistor XNOR gate, which is not limited by the method, and can be realized on the silicon substrate of the SOI wafer by the following specific manufacturing steps:
the method comprises the following steps: referring to fig. 7-9, providing an SOI wafer, wherein the bottom is a silicon substrate 1 of the SOI wafer, the upper surface of the silicon substrate is a substrate insulating layer 2 of the SOI wafer, and the upper surface of the substrate insulating layer 2 of the SOI wafer is a semiconductor film, and preliminarily forming a semiconductor film 3 through photolithography, etching and deposition processes;
step two: referring to fig. 10-14, an interchangeable N-type source/drain region a4, an interchangeable P-type source/drain region a5, an interchangeable N-type source/drain region b6, and an interchangeable P-type source/drain region b7 are initially formed by an ion implantation process, respectively;
step three: referring to fig. 15-20, by an etching process, etching away a partial region between the interchangeable N-type source drain region a4 and the interchangeable P-type source drain region a5 generated in the second step, etching away a partial region between the interchangeable N-type source drain region b6 and the interchangeable P-type source drain region b7 generated in the second step, further forming an interchangeable N-type source drain region a4, an interchangeable P-type source drain region a5, an interchangeable N-type source drain region b6, and an interchangeable P-type source drain region b7, reserving a space for the anti-depletion isolation layer a14 and the anti-depletion isolation layer b15, depositing an insulating dielectric layer on the basis of the second step by a deposition process, planarizing to expose the semiconductor film 3, forming an anti-depletion isolation layer a14 and an anti-depletion isolation layer b15, primarily forming an insulating dielectric layer 8, etching away the insulating dielectric layers on the left and right sides of the front and back surfaces of the semiconductor film 3 by an etching process until the substrate insulating layer 2 of the SOI wafer is exposed, further forming an insulating dielectric layer 8;
step four: referring to fig. 21 to 22, a gate insulating layer 9 is preliminarily formed by depositing a gate insulating layer on the basis of the third step through a deposition process and then performing a planarization process until the semiconductor thin film 3 is exposed;
step five: referring to fig. 23 to 28, an insulating dielectric layer is deposited on the basis of the fourth step by a deposition process, and after planarization treatment, the middle portions of the left and right sides are etched by photolithography and etching processes until the gate electrode insulating layer 9 formed in the fourth step and the upper surface of the semiconductor thin film 3 between the upper and lower side portions of the gate electrode insulating layer 9 are exposed;
step six: referring to fig. 29 to 33, a gate electrode insulating layer is deposited on the basis of the fifth step through a deposition process, and then a planarization process is performed until the upper surface of the insulating dielectric layer 8 is exposed, and then the upper and lower side portions of the left and right side portions of the gate electrode insulating layer 9 are removed through a photolithography process and an etching process until the substrate insulating layer 2 is exposed, and then a metal, an alloy, polysilicon, or a metal silicide is deposited through a deposition process, and then a planarization process is performed until the gate electrode insulating layer 9 is exposed, thereby preliminarily forming a gate electrode a10 and a gate electrode b 11;
step seven: referring to fig. 34 to 37, after the gate electrode insulating layer is deposited on the basis of the sixth step by a deposition process and is subjected to planarization treatment, the middle portions of the left and right sides are etched by photolithography and etching processes until the upper surfaces of the gate electrode insulating layer 9, the gate electrode a10 and the gate electrode b11 formed in the sixth step are exposed;
step eight: referring to fig. 38 to 42, a metal, an alloy, polysilicon or a metal silicide is deposited on the basis of step seven by a deposition process, and then a gate electrode a10 and a gate electrode b11 are further formed by a planarization process until the upper surface of the insulating dielectric layer 8 is exposed;
step nine: referring to fig. 43-50, by an etching process, a portion of the insulating dielectric layer 8 is etched on the basis of the eighth step until the upper surfaces of the left sides of the interchangeable N-type source/drain region a4 and the interchangeable P-type source/drain region a5, and the upper surfaces of the right sides of the interchangeable N-type source/drain region b6 and the interchangeable P-type source/drain region b7 are exposed;
step ten: referring to fig. 1-5, a deposition process is performed to deposit a metal, an alloy, a polysilicon or a metal silicide on the basis of step nine, and then a planarization process is performed until the upper surface of the insulating dielectric layer 8 is exposed, so as to form an interchangeable source/drain electrode a12 and an interchangeable source/drain electrode b 13.
Claims (4)
1. The double-doped source-drain single transistor XNOR gate comprises a silicon substrate (1) of an SOI wafer, and is characterized in that: a substrate insulating layer (2) of the SOI wafer is arranged above a silicon substrate (1) of the SOI wafer, the substrate insulating layer (2) of the SOI wafer is an insulating material layer, and a semiconductor thin film region (3), an interchangeable N-type source-drain region a (4), an interchangeable P-type source-drain region a (5), an interchangeable N-type source-drain region b (6), an interchangeable P-type source-drain region b (7), an insulating medium layer (8), a gate electrode insulating layer (9), a gate electrode a (10) and a gate electrode b (11) are arranged above the substrate insulating layer (2) of the SOI wafer; the semiconductor thin film region (3) is made of semiconductor materials, and the left side and the right side of the upper surface and the front and back side surfaces of the semiconductor thin film region (3) are mutually contacted with the gate electrode insulating layer (9); the upper surface and the central parts of the front and rear side surfaces of the semiconductor thin film region (3) are in contact with the insulating medium layer (8);
the interchangeable N-type source drain region a (4) and the interchangeable P-type source drain region a (5) are semiconductor regions doped with N-type impurities and P-type impurities respectively; the interchangeable N-type source drain region a (4) and the interchangeable P-type source drain region a (5) are positioned on the left side of the semiconductor thin film region (3) and are in contact with the semiconductor thin film region (3); the front side surface of the interchangeable N-type source drain region a (4) and the back side surface of the interchangeable P-type source drain region a (5) are in contact with the insulating medium layer (8); the back side surface of the interchangeable N-type source drain region a (4) and the front side surface of the interchangeable P-type source drain region a (5) are in contact with the anti-depletion isolation layer a (14); the anti-depletion isolation layer a (14) is made of an insulating dielectric material; the left sides of the upper surfaces of the interchangeable N-type source drain region a (4) and the interchangeable P-type source drain region a (5) are mutually contacted with the interchangeable source drain electrode a (12), and the right sides of the upper surfaces of the interchangeable N-type source drain region a (4) and the interchangeable P-type source drain region a (5) are mutually contacted with the insulating medium layer (8);
the interchangeable N-type source drain region b (6) and the interchangeable P-type source drain region b (7) are semiconductor regions doped with N-type impurities and P-type impurities respectively; the interchangeable N-type source drain region b (6) and the interchangeable P-type source drain region b (7) are positioned on the right side of the semiconductor thin film region (3) and are in contact with the semiconductor thin film region (3); the front side surface of the interchangeable N-type source drain region b (6) and the back side surface of the interchangeable P-type source drain region b (7) are in contact with the insulating medium layer (8); the back side surface of the interchangeable N-type source drain region b (6) and the front side surface of the interchangeable P-type source drain region b (7) are in contact with the anti-depletion isolation layer b (15); the anti-depletion isolation layer b (15) is made of an insulating dielectric material; the right sides of the upper surfaces of the interchangeable N-type source drain region b (6) and the interchangeable P-type source drain region b (7) are mutually contacted with the interchangeable source drain electrode b (13), and the left sides of the upper surfaces of the interchangeable N-type source drain region b (6) and the interchangeable P-type source drain region b (7) are mutually contacted with the insulating medium layer (8);
the insulating medium layer (8) is made of insulating medium materials; the gate electrode insulating layer (9) is made of an insulating dielectric material, and the upper surface and the front and back side surfaces of the left side part of the gate electrode insulating layer (9) are in contact with the gate electrode a (10); the upper surface and front and rear side surfaces of the right side portion of the gate electrode insulating layer (9) and the gate electrode b (11) are in contact with each other; the gate electrode a (10) and the gate electrode b (11) are metal, alloy, polycrystalline silicon or metal silicide; the gate electrode a (10) is mutually contacted with the upper surface and the front and back side surfaces of the left side part of the gate electrode insulating layer (9), the gate electrode a (10) is mutually insulated and isolated from the semiconductor thin film region (3) through the gate electrode insulating layer (9), and the gate electrode a (10) is mutually insulated and isolated from the interchangeable source drain electrode a (12) and the interchangeable source drain electrode b (13) through the insulating medium layer (8); the gate electrode b (11) is mutually contacted with the upper surface and the front and back side surfaces of the right part of the gate electrode insulating layer (9), the gate electrode b (11) is mutually insulated and isolated from the semiconductor thin film region (3) through the gate electrode insulating layer (9), and the gate electrode b (11) is mutually insulated and isolated from the interchangeable source drain electrode a (12) and the interchangeable source drain electrode b (13) through the insulating medium layer (8); the gate electrode a (10) and the gate electrode b (11) are insulated and isolated from each other through an insulating medium layer (8); the interchangeable source drain electrode a (12) is made of metal, alloy or metal silicide, the lower surface of the interchangeable source drain electrode a (12) is in mutual contact with the left sides of the upper surfaces of the interchangeable N-type source drain region a (4) and the interchangeable P-type source drain region a (5) to form ohmic type anti-blocking layer contact; the interchangeable source drain electrode b (13) is made of metal, alloy or metal silicide, and the lower surface of the interchangeable source drain electrode b (13) is in contact with the right sides of the upper surfaces of the interchangeable N-type source drain region b (6) and the interchangeable P-type source drain region b (7) to form ohmic-type reverse blocking layer contact.
2. A method for using the double-doped source-drain single-transistor exclusive-nor gate according to claim 1, wherein the method comprises the following steps: the gate electrode a (10) is connected to one of two signal input terminals of the nor gate, i.e., the signal input terminal a (16) and the signal input terminal B (17), while the gate electrode B (11) is connected to the other of the two signal input terminals of the nor gate, i.e., the signal input terminal a (16) and the signal input terminal B (17) other than the connection with the gate electrode a (10); the interchangeable source-drain electrode a (12) is connected with one end of the power supply voltage input end (18) and the exclusive-nor output end (19), and the interchangeable source-drain electrode b (13) is connected with the other end of the power supply voltage input end (18) and the exclusive-nor output end (19) which is connected with the interchangeable source-drain electrode a (12);
when a signal input end A (16) and a signal input end B (17) input high level simultaneously, a gate electrode a (10) and a gate electrode B (11) are at high potential simultaneously, and when an interchangeable source drain electrode a (12) and an interchangeable source drain electrode B (13) are connected with one end of a power supply voltage input end (18) and one end of an exclusive-nor gate output end (19) respectively, the semiconductor thin film region (3) can form an electron channel inside through an electric field effect under the combined action of the gate electrode a (10) and the gate electrode B (11), so that electrons can flow from one end of the interchangeable source drain electrode a (12) and the interchangeable source drain electrode B (13) which is at lower potential to one end of the interchangeable N-type source drain region a (4) and the interchangeable N-type source drain region B (6) which is also at lower potential, and form an electron channel inside the semiconductor thin film region (3) to flow to the interchangeable N-type source drain region a (4) and the interchangeable N-type source drain region B (6) The double-doped source-drain single-transistor AND gate is in a low-resistance state at the moment, and outputs a high level to an AND gate output end (19);
when a signal input end A (16) and a signal input end B (17) input low level simultaneously, a gate electrode a (10) and a gate electrode B (11) are at low level simultaneously, and when an interchangeable source drain electrode a (12) and an interchangeable source drain electrode B (13) are connected with one end of a power supply voltage input end (18) and one end of an exclusive-nor output end (19) respectively, a semiconductor thin film region (3) internally forms a hole channel through an electric field effect under the combined action of the gate electrode a (10) and the gate electrode B (11), so that holes can flow from one end of the interchangeable source drain electrode a (12) and the interchangeable source drain electrode B (13) which is at higher potential to one end of the interchangeable P-type source drain region a (5) and the interchangeable P-type source drain region B (7) which is also at higher potential, and flow to the interchangeable P-type source drain region a (5) and the interchangeable N-type source drain region B (6) through the hole channel formed in the semiconductor thin film region (3) The double-doped source-drain single-transistor AND gate is in a low-resistance state at the moment, and outputs a high level to an AND gate output end (19);
when one of the signal input terminal A (16) and the signal input terminal B (17) is inputted with a high level and the other is inputted with a low level, and when the interchangeable source-drain electrode a (12) and the interchangeable source-drain electrode B (13) are connected to one of the power supply voltage input terminal (18) and the XNOR gate output terminal (19), respectively, one of the gate electrode a (10) and the gate electrode B (11) is at a high level and the other is at a low level, the one of the gate electrode a (10) and the gate electrode B (11) which is at a high level may block "holes" from flowing from the one of the interchangeable source-drain electrode a (12) and the interchangeable source-drain electrode B (13) which is at a higher potential to the one of the interchangeable source-drain electrode a (12) and the interchangeable source-drain electrode B (13) which is at a lower potential by the electric field effect, and the one of the gate electrode a (10) and the gate electrode B (11) which is at a low level may block "electrons" from the one of the interchangeable source-drain electrode a (12) and the interchangeable source-drain electrode B (13) which is at a lower potential by the electric field effect One end of the double-doped source-drain single-transistor is flowed to the end with lower potential, the same OR gate of the double-doped source-drain single-transistor is in a high-impedance state at the moment, and low level is output to an output end (19) of the same OR gate.
3. The use method of the double-doped source-drain single-transistor XNOR gate of claim 2, characterized in that: the double-doped source-drain single transistor is bilaterally symmetrical to an exclusive OR gate structure, an interchangeable source-drain electrode a (12) and an interchangeable source-drain electrode b (13) can be interchanged with each other, namely, any one end of the interchangeable source-drain electrode a (12) and the interchangeable source-drain electrode b (13) is connected with a power supply voltage input end (18), and the other end of the interchangeable source-drain electrode a (12) and the interchangeable source-drain electrode b (13) are connected with an exclusive OR gate output end (19) to output an exclusive OR gate.
4. A method for manufacturing a double-doped source-drain single-transistor xnor gate according to claim 1, wherein: the specific manufacturing steps are as follows:
the method comprises the following steps: providing an SOI wafer, wherein the silicon substrate (1) of the SOI wafer is arranged at the lowest part, the substrate insulating layer (2) of the SOI wafer is arranged on the silicon substrate, the upper surface of the substrate insulating layer (2) of the SOI wafer is a semiconductor film, and the semiconductor film (3) is preliminarily formed through photoetching, etching and deposition processes;
step two: through an ion implantation process, an interchangeable N-type source drain region a (4), an interchangeable P-type source drain region a (5), an interchangeable N-type source drain region b (6) and an interchangeable P-type source drain region b (7) are respectively and preliminarily formed;
step three: etching partial areas between the interchangeable N-type source drain area a (4) and the interchangeable P-type source drain area a (5) generated in the second step by an etching process, etching partial areas between the interchangeable N-type source drain area b (6) and the interchangeable P-type source drain area b (7) generated in the second step, further forming the interchangeable N-type source drain area a (4), the interchangeable P-type source drain area a (5), the interchangeable N-type source drain area b (6) and the interchangeable P-type source drain area b (7), reserving spaces for the depletion-proof isolation layer a (14) and the depletion-proof isolation layer b (15), depositing an insulating medium layer on the basis of the second step by a deposition process, flattening to expose the semiconductor film (3), forming a depletion-proof isolation layer a (14) and a depletion-proof isolation layer b (15), and preliminarily forming an insulating medium layer (8), etching off the insulating dielectric layers on the left side and the right side of the front surface and the rear surface of the semiconductor film (3) through an etching process until the substrate insulating layer (2) of the SOI wafer is exposed, and further forming an insulating dielectric layer (8);
step four: depositing a gate electrode insulating layer on the basis of the third step by a deposition process, and performing planarization treatment until the semiconductor film (3) is exposed to preliminarily form a gate electrode insulating layer (9);
step five: depositing an insulating medium layer on the basis of the fourth step by a deposition process, and etching the middle parts of the left side and the right side by photoetching and etching processes after planarization treatment until the upper surfaces of the gate electrode insulating layer (9) formed in the fourth step and the semiconductor film (3) between the upper side part and the lower side part of the gate electrode insulating layer (9) are exposed;
step six: depositing a gate electrode insulating layer on the basis of the fifth step by a deposition process, performing planarization treatment until the upper surface of the insulating dielectric layer (8) is exposed, removing the upper and lower side parts of the left and right side parts of the gate electrode insulating layer (9) by photoetching and etching processes until the substrate insulating layer (2) is exposed, depositing metal, alloy, polycrystalline silicon or metal silicide by the deposition process, performing planarization treatment until the gate electrode insulating layer (9) is exposed, and preliminarily forming a gate electrode a (10) and a gate electrode b (11);
step seven: depositing a gate electrode insulating layer on the basis of the sixth step by a deposition process, and etching the middle parts of the left side and the right side by photoetching and etching processes after planarization treatment until the upper surfaces of the gate electrode insulating layer (9), the gate electrode a (10) and the gate electrode b (11) formed in the sixth step are exposed;
step eight: depositing metal, alloy, polycrystalline silicon or metal silicide on the basis of the step seven through a deposition process, and then performing planarization treatment until the upper surface of the insulating dielectric layer (8) is exposed to further form a gate electrode a (10) and a gate electrode b (11);
step nine: etching off part of the insulating dielectric layer (8) on the basis of the eighth step by an etching process until the upper surfaces of the left sides of the interchangeable N-type source drain region a (4) and the interchangeable P-type source drain region a (5) and the upper surfaces of the right sides of the interchangeable N-type source drain region b (6) and the interchangeable P-type source drain region b (7) are exposed;
step ten: and depositing metal, alloy, polycrystalline silicon or metal silicide on the basis of the step nine through a deposition process, and performing planarization treatment until the upper surface of the insulating medium layer (8) is exposed to form an interchangeable source/drain electrode a (12) and an interchangeable source/drain electrode b (13).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113299758A (en) * | 2021-05-24 | 2021-08-24 | 华东师范大学 | Source-drain double-doped reconfigurable field effect transistor |
| CN116705605A (en) * | 2023-06-20 | 2023-09-05 | 中国科学院上海微系统与信息技术研究所 | Silicon-based gallium nitride HEMT device and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000031362A (en) * | 1998-11-05 | 2000-06-05 | 김영환 | Semiconductor device and producing method thereof |
| WO2016201609A1 (en) * | 2015-06-15 | 2016-12-22 | 北京大学深圳研究生院 | Metal oxide thin-film transistor and display panel, and preparation methods for both |
| CN107785436A (en) * | 2017-10-31 | 2018-03-09 | 沈阳工业大学 | Source and drain resistive formula rectangular grid control U-shaped raceway groove bidirectional transistor and its manufacture method |
| CN107808905A (en) * | 2017-10-31 | 2018-03-16 | 沈阳工业大学 | Bilateral folds the double tunnelling type two-way admittance transistors of grid-control source and drain and its manufacture method |
-
2021
- 2021-07-12 CN CN202110784870.2A patent/CN113571586B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000031362A (en) * | 1998-11-05 | 2000-06-05 | 김영환 | Semiconductor device and producing method thereof |
| WO2016201609A1 (en) * | 2015-06-15 | 2016-12-22 | 北京大学深圳研究生院 | Metal oxide thin-film transistor and display panel, and preparation methods for both |
| CN107785436A (en) * | 2017-10-31 | 2018-03-09 | 沈阳工业大学 | Source and drain resistive formula rectangular grid control U-shaped raceway groove bidirectional transistor and its manufacture method |
| CN107808905A (en) * | 2017-10-31 | 2018-03-16 | 沈阳工业大学 | Bilateral folds the double tunnelling type two-way admittance transistors of grid-control source and drain and its manufacture method |
Non-Patent Citations (1)
| Title |
|---|
| 马恺璐;靳晓诗;: "一种基于深肖特基势垒辅助栅控制的隧穿场效应晶体管", 微处理机, no. 04 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113299758A (en) * | 2021-05-24 | 2021-08-24 | 华东师范大学 | Source-drain double-doped reconfigurable field effect transistor |
| CN116705605A (en) * | 2023-06-20 | 2023-09-05 | 中国科学院上海微系统与信息技术研究所 | Silicon-based gallium nitride HEMT device and preparation method thereof |
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|---|---|
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