CN116705605A - Silicon-based gallium nitride HEMT device and preparation method thereof - Google Patents
Silicon-based gallium nitride HEMT device and preparation method thereof Download PDFInfo
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- CN116705605A CN116705605A CN202310736872.3A CN202310736872A CN116705605A CN 116705605 A CN116705605 A CN 116705605A CN 202310736872 A CN202310736872 A CN 202310736872A CN 116705605 A CN116705605 A CN 116705605A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 142
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 142
- 239000010703 silicon Substances 0.000 title claims abstract description 142
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 68
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 62
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 187
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 99
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 98
- 239000002131 composite material Substances 0.000 claims abstract description 77
- 238000009413 insulation Methods 0.000 claims abstract description 49
- 238000005468 ion implantation Methods 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000002513 implantation Methods 0.000 claims description 28
- 238000000137 annealing Methods 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 13
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 12
- 229910052799 carbon Inorganic materials 0.000 claims description 12
- 230000007547 defect Effects 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 206010040844 Skin exfoliation Diseases 0.000 claims 1
- 239000010408 film Substances 0.000 description 32
- 239000010409 thin film Substances 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The disclosure relates to a silicon-based gallium nitride HEMT device and a preparation method thereof, wherein the method comprises the following steps: ion implantation is carried out on the N-type conductive silicon carbide substrate; performing insulation treatment on the surface of the N-type conductive silicon carbide substrate subjected to ion implantation to obtain an N-type conductive silicon carbide substrate subjected to insulation treatment; obtaining a silicon substrate; bonding the silicon substrate and the N-type conductive silicon carbide substrate subjected to insulation treatment, and stripping the bonded composite substrate to obtain a composite silicon-based substrate; performing insulation treatment on the surface of the composite silicon-based substrate to obtain the composite silicon-based substrate after insulation treatment; a gallium nitride film is epitaxially grown on the surface of the composite silicon-based substrate after the insulation treatment; and preparing an HEMT device layer on the surface of the gallium nitride film to obtain the silicon-based gallium nitride HEMT device. The preparation method of the silicon-based gallium nitride HEMT device can reduce the preparation cost and enlarge the size of the silicon-based gallium nitride HEMT device.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, in particular to a silicon-based gallium nitride HEMT device and a preparation method thereof.
Background
The gallium nitride power device has lower energy loss, smaller volume, higher working voltage and higher power and working frequency under the same working voltage and power conditions compared with the silicon-based semiconductor power device which is dominant in the current market due to the wide forbidden band characteristic of gallium nitride. The current industry is relatively mature gallium nitride film preparation technology and is simultaneously feasible by Metal Organic Chemical Vapor Deposition (MOCVD) epitaxy technology. The substrates commonly used in the industry today are silicon carbide, sapphire and single crystal silicon.
Current technology for gallium nitride radio frequency devices is achieved by heteroepitaxy of high quality gallium nitride device layers on semi-insulating silicon carbide with <0001> crystal orientation. However, the semi-insulating silicon carbide is not only high in cost and difficult to apply on a large scale, but also difficult to grow, cut, grind and polish, and difficult to expand to 8 or even 12 inches, which greatly hinders the cost reduction of the gallium nitride radio frequency device.
Disclosure of Invention
The disclosure provides a silicon-based gallium nitride HEMT device and a preparation method thereof, and the technical scheme of the disclosure is as follows:
according to a first aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a silicon-based gallium nitride HEMT device, including:
obtaining an N-type conductive silicon carbide substrate;
performing ion implantation on the N-type conductive silicon carbide substrate to obtain an N-type conductive silicon carbide substrate after ion implantation; the N-type conductive silicon carbide substrate after ion implantation sequentially comprises a silicon carbide film, a defect layer formed by ion implantation and a residual silicon carbide substrate;
performing insulation treatment on the surface of the N-type conductive silicon carbide substrate subjected to ion implantation to obtain an N-type conductive silicon carbide substrate subjected to insulation treatment; the N-type conductive silicon carbide substrate after the insulation treatment sequentially comprises a first insulation layer, a silicon carbide film, a defect layer and a residual silicon carbide substrate;
obtaining a silicon substrate; the silicon substrate is a high-resistance silicon substrate or an intrinsic silicon substrate;
bonding the silicon substrate with the N-type conductive carbon silicon substrate subjected to insulation treatment and the insulation treatment silicon substrate, and stripping the bonded composite substrate to obtain a composite silicon substrate; the composite silicon-based substrate sequentially comprises a silicon substrate, a first insulating layer and a silicon carbide film;
performing insulation treatment on the surface of the composite silicon-based substrate to obtain the composite silicon-based substrate after insulation treatment;
a gallium nitride film is epitaxially grown on the surface of the composite silicon-based substrate after the insulation treatment;
and preparing an HEMT device layer on the surface of the gallium nitride film to obtain the silicon-based gallium nitride HEMT device.
In some possible embodiments, ion implanting an N-type conductive silicon carbide substrate comprises:
and (3) performing ion implantation on the N-type conductive silicon carbide substrate by using at least one implantation element of hydrogen and helium, wherein the implantation dosage is 1E16/cm 2-1E 18/cm2, and the implantation energy is 20 keV-500 keV.
In some possible embodiments, the insulating treatment of the surface of the N-type conductive silicon carbide substrate after ion implantation includes:
and (3) performing inversion doping on the surface of the N-type conductive silicon carbide substrate subjected to ion implantation by using at least one implantation element of boron and aluminum, wherein the implantation dosage is 1E 16-1E 19/cm < 2 >, and the implantation energy is 5-30 keV.
In some possible embodiments, bonding the silicon substrate with the N-type conductive silicon carbide substrate after the insulation treatment, and peeling off the bonded composite substrate to obtain a composite silicon-based substrate, before performing the insulation treatment on the surface of the composite silicon-based substrate, further including:
annealing the composite silicon-based substrate to activate the first insulating layer, wherein the annealing temperature is 1300-1370 ℃ and the annealing time is 3-6 h; wherein the annealing time length and the annealing temperature are in inverse relation.
In some possible embodiments, before annealing the composite silicon-based substrate row to activate the first insulating layer, further comprising:
performing carbon film protection on the composite silicon-based substrate; the thickness of the carbon film is 100-1000 nm, and the thickness of the carbon film and the annealing temperature and the annealing air pressure are in inverse proportion.
In some possible embodiments, after annealing the composite silicon-based substrate to activate the first insulating layer, further comprising:
and removing the carbon film remained on the surface of the annealed composite silicon-based substrate by dry etching.
In some possible embodiments, after the obtaining of the silicon substrate, before bonding the silicon substrate to the N-type conductive silicon carbide substrate after the insulating treatment, the method further comprises:
and (3) performing ion implantation on the surface of the silicon substrate by using at least one implantation element of boron and aluminum, wherein the implantation dosage is 1E 16-1E 19/cm < 2 >, and the implantation energy is 5-30 keV.
In some possible embodiments, after the bonded composite substrate is subjected to a lift-off treatment to obtain a composite silicon-based substrate, the insulating treatment is performed on the surface of the composite silicon-based substrate, and before the insulating-treated composite silicon-based substrate is obtained, the method further includes:
and (3) polishing the surface of the composite silicon-based substrate to remove the silicon carbide film with the thickness of 100-300 nm on the surface, thereby obtaining the polished composite silicon-based substrate.
In some possible embodiments, performing insulation treatment on the surface of the composite silicon-based substrate to obtain an insulation-treated composite silicon-based substrate, including:
h ion implantation is carried out on the surface of the composite silicon-based substrate, and a second insulating layer is formed on the surface of the silicon carbide film, so that the composite silicon-based substrate after insulating treatment is obtained; the composite silicon-based substrate after the insulation treatment comprises a silicon substrate, a first insulation layer, a silicon carbide film and a second insulation layer in sequence.
According to a second aspect of the embodiments of the present disclosure, a silicon-based gallium nitride HEMT device is provided, and the silicon-based gallium nitride HEMT device is prepared by the preparation method of the silicon-based gallium nitride HEMT device.
The technical scheme provided by the embodiment of the disclosure at least brings the following beneficial effects:
according to the preparation method of the silicon-based gallium nitride HEMT device, on one hand, the cost of the substrate required for preparing the gallium nitride HEMT device can be reduced by transferring the high-quality N-type conductive silicon carbide film to the low-cost silicon substrate, and the high-quality N-type conductive silicon carbide substrate can be recycled, so that the utilization rate of materials can be improved; on the other hand, because the N-type conductive silicon carbide substrate has larger wafer size, the growth diameter expansion of gallium nitride can be realized to 8 inches by performing first insulation treatment on the N-type conductive silicon carbide film and then performing second insulation treatment on the surface of the grown gallium nitride, which is beneficial to improving the preparation yield of the silicon-based gallium nitride HEMT device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure and do not constitute an undue limitation on the disclosure.
Fig. 1 is a flow chart illustrating a method of fabricating a silicon-based gallium nitride HEMT device according to an example embodiment;
fig. 2A-2H are schematic diagrams illustrating a fabrication process of a silicon-based gallium nitride HEMT device according to an example embodiment.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings.
It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the foregoing figures are used for distinguishing between similar first objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the disclosure described herein may be capable of operation in sequences other than those illustrated or described herein. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples consistent with some aspects of the present disclosure as detailed in the accompanying claims.
The embodiment of the disclosure provides a preparation method of a silicon-based gallium nitride HEMT device, which can realize low-cost preparation of the gallium nitride HEMT device, can expand the size to 8 inches, and can further improve the yield of the device.
Referring to fig. 1 and fig. 2A to fig. 2I, fig. 1 is a schematic flow chart of a method for manufacturing a silicon-based gallium nitride HEMT device according to an embodiment of the disclosure, and fig. 2A to fig. 2I are schematic flow charts of a method for manufacturing a silicon-based gallium nitride HEMT device according to an embodiment of the disclosure;
as shown in fig. 1, a method for manufacturing a silicon-based gallium nitride HEMT device according to an embodiment of the present disclosure may include the following steps:
s101: and obtaining the N-type conductive silicon carbide substrate.
Specifically, as shown in fig. 2A, a SiC silicon carbide substrate 201 is first obtained; the SiC substrate 201 is an N-type conductive high quality single crystal silicon carbide substrate having a larger wafer size than a semi-insulating silicon carbide substrate, thereby facilitating growth expansion of GaN to 8 inches.
S103: and carrying out ion implantation on the N-type conductive silicon carbide substrate to obtain the N-type conductive silicon carbide substrate after ion implantation.
The N-type conductive silicon carbide substrate after ion implantation sequentially comprises a silicon carbide film, a defect layer formed by ion implantation and a residual silicon carbide substrate.
Optionally, at least one of hydrogen and helium is used for ion implantation of the N-type conductive silicon carbide substrate, wherein the implantation dosage is 1E16/cm 2-1E 18/cm2, and the implantation energy is 20 keV-500 keV.
Specifically, as shown in fig. 2B, the SiC substrate 201 is subjected to H ion implantation to obtain an SiC substrate 201a after the H ion implantation; the SiC substrate 201a after ion implantation includes, in order from top to bottom, a SiC thin film 2011, a defect layer 2012, and a remaining SiC substrate 2013.
S105: and performing insulation treatment on the surface of the N-type conductive silicon carbide substrate subjected to ion implantation to obtain the N-type conductive silicon carbide substrate subjected to insulation treatment.
The N-type conductive silicon carbide substrate after the insulation treatment sequentially comprises a first insulation layer, a silicon carbide film, a defect layer and a residual silicon carbide substrate.
Optionally, S105 may specifically include: and (3) performing inversion doping on the surface of the N-type conductive silicon carbide substrate subjected to ion implantation by using at least one implantation element of boron and aluminum, wherein the implantation dosage is 1E 16-1E 19/cm < 2 >, and the implantation energy is 5-30 keV.
Specifically, as shown in fig. 2C, the surface of the SiC substrate 201a is subjected to inversion doping using Al ions, and a first insulating layer 2014 is formed on the surface, thereby obtaining an inversion doped SiC substrate 201b. Here, in order to perform insulation treatment on the surface of the conductive SiC film 2011, the purpose of inversion doping is to implement an insulation state of the bonding surface, so that the impedance of the SiC film 2014 can be improved, and the downward leakage of the power of the upper HEMT device layer is avoided.
S107: a silicon substrate is obtained.
Specifically, as shown in fig. 2D, a Si substrate 202 is obtained; the Si substrate 202 may be a high-resistance silicon substrate or an intrinsic silicon substrate.
Optionally, after step S107 and before step S109, the method of the embodiment of the disclosure may further include the following steps:
s108: and (3) performing ion implantation on the surface of the silicon substrate by using at least one implantation element of boron and aluminum, wherein the implantation dosage is 1E 16-1E 19/cm < 2 >, and the implantation energy is 5-30 keV.
In step S108, the purpose of ion implantation is also to achieve an insulating state of the bonding surface; in particular, when ion implantation is performed on the surface of the silicon substrate, the same implantation elements as those used when the SiC substrate is doped inversely as described above may be used to achieve the optimum insulating effect.
S109: bonding the silicon substrate and the N-type conductive silicon carbide substrate subjected to insulation treatment, and stripping the bonded composite substrate to obtain the composite silicon-based substrate.
The composite silicon-based substrate sequentially comprises a silicon substrate, a first insulating layer and a silicon carbide film.
Specifically, in this step, as shown in fig. 2E, the Si substrate 202 and the SiC substrate 201b after the inversion doping are directly bonded in a vacuum environment, so as to obtain a composite substrate 300; and then stripping the composite substrate 300, specifically removing the defect layer 2012 to enable the rest of the SiC substrate to fall off from the composite substrate 300, so as to obtain a composite silicon-based substrate 400, wherein the composite silicon-based substrate 400 sequentially comprises the Si substrate 202, the first insulating layer 2014 and the SiC film 2011 from bottom to top.
Here, the remaining SiC substrate 2013 after the peeling can also be subjected to recovery processing by the following recovery step for subsequent use in the preparation of other devices. Specifically, the recovering step may include: carrying out thermal oxidation on the residual silicon carbide substrate after stripping, and carrying out wet oxidation for 2-5 hours in a pure oxygen environment at 1300 ℃; and then removing the oxide layer by using HF, and removing the silicon carbide film with the thickness of not more than 500nm on the surface of the silicon carbide substrate by using fine polishing.
Optionally, after step S109, before step S111, the method of the embodiment of the disclosure may further include:
s100: annealing the composite silicon-based substrate to activate the first insulating layer, wherein the annealing temperature is 1300-1370 ℃ and the annealing time is 3-6 h; wherein the annealing time length and the annealing temperature are in inverse relation.
Further, before annealing treatment, carbon film protection can be carried out on the composite silicon-based substrate; the thickness of the carbon film is 100-1000 nm, and the thickness of the carbon film and the annealing temperature and the annealing air pressure are in inverse proportion. Correspondingly, after annealing treatment is carried out on the composite silicon-based substrate, the carbon film remained on the surface of the composite silicon-based substrate is removed by dry etching.
Optionally, before the next step S111, polishing treatment may be further performed on the surface of the composite silicon substrate, to obtain a polished composite silicon substrate. Here, considering that the SiC film 2011 on the surface may be damaged at the time of peeling, the SiC film 2011 having a certain thickness on the surface may be removed by polishing, and the thickness may be in the range of 100 to 300 nm.
S111: and performing insulation treatment on the surface of the composite silicon-based substrate to obtain the composite silicon-based substrate after insulation treatment.
Specifically, as shown in fig. 2F, the surface of the composite silicon substrate 400 is subjected to H ion implantation, and a second insulating layer 203 is formed on the surface of the SiC thin film 2011, so as to obtain an insulating-treated composite silicon substrate 400a; the insulation-treated composite silicon-based substrate 400a includes, in order, the Si substrate 202, the first insulating layer 2014, the SiC thin film 2011, and the second insulating layer 203.
The surface of the composite silicon substrate is insulated by adopting an H ion implantation mode, and the inversion doped element implantation is not performed, so that the element contamination of the inversion doped element to the GaN epitaxial process can be avoided.
S113: and (3) extending a gallium nitride film on the surface of the composite silicon-based substrate after the insulation treatment.
Specifically, as shown in fig. 2G, a GaN thin film 204 is epitaxially grown on the surface of the processed composite silicon-based substrate 400 a. Wherein the thickness of the GaN thin film 204 is 10-20 μm.
S115: and preparing an HEMT device layer on the surface of the gallium nitride film to obtain the silicon-based gallium nitride HEMT device.
Specifically, as shown in fig. 2H, when preparing the HEMT device layer 205, firstly, a GaN channel layer 2051 and Al are sequentially deposited on the surface of the GaN thin film 204 x Ga x The N barrier layer 2052 and the dielectric layer 2053, and then a source electrode, a gate electrode and a drain electrode are formed on the dielectric layer 2053, so that the preparation of the HEMT device layer 205 is completed, and finally the silicon-based gallium nitride HEMT device is obtained.
According to the preparation method of the silicon-based gallium nitride HEMT device, on one hand, the cost of the substrate required for preparing the gallium nitride HEMT device can be reduced by transferring the high-quality N-type conductive silicon carbide film to the low-cost silicon substrate, and the high-quality N-type conductive silicon carbide substrate can be recycled, so that the utilization rate of materials can be improved; on the other hand, because the N-type conductive silicon carbide substrate has larger wafer size, the growth diameter expansion of gallium nitride can be realized to 8 inches by performing first insulation treatment on the N-type conductive silicon carbide film and then performing second insulation treatment on the surface of the grown gallium nitride, which is beneficial to improving the preparation yield of the silicon-based gallium nitride HEMT device.
In addition, the embodiment of the disclosure also provides a silicon-based gallium nitride HEMT device, which is prepared by the preparation method of the silicon-based gallium nitride HEMT device.
It should be noted that, the silicon-based gallium nitride HEMT device and the preparation method of the silicon-based gallium nitride HEMT device according to the embodiment of the disclosure are based on the same application conception.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. The preparation method of the silicon-based gallium nitride HEMT device is characterized by comprising the following steps of:
obtaining an N-type conductive silicon carbide substrate;
performing ion implantation on the N-type conductive silicon carbide substrate to obtain an N-type conductive silicon carbide substrate after ion implantation; the N-type conductive silicon carbide substrate after ion implantation sequentially comprises a silicon carbide film, a defect layer formed by ion implantation and a residual silicon carbide substrate;
performing insulation treatment on the surface of the N-type conductive silicon carbide substrate subjected to ion implantation to obtain an N-type conductive silicon carbide substrate subjected to insulation treatment; the N-type conductive silicon carbide substrate after the insulation treatment sequentially comprises a first insulation layer, the silicon carbide film, the defect layer and the residual silicon carbide substrate;
obtaining a silicon substrate; the silicon substrate is a high-resistance silicon substrate or an intrinsic silicon substrate;
bonding the silicon substrate and the N-type conductive silicon carbide substrate subjected to the insulation treatment, and stripping the bonded composite substrate to obtain a composite silicon-based substrate; the composite silicon-based substrate sequentially comprises the silicon substrate, the first insulating layer and the silicon carbide film;
performing insulation treatment on the surface of the composite silicon-based substrate to obtain an insulated composite silicon-based substrate;
a gallium nitride film is epitaxially grown on the surface of the composite silicon-based substrate after the insulation treatment;
and preparing an HEMT device layer on the surface of the gallium nitride film to obtain the silicon-based gallium nitride HEMT device.
2. The method for manufacturing a silicon-based gallium nitride HEMT device according to claim 1, wherein the ion implantation of the N-type conductive silicon carbide substrate comprises:
and (3) performing ion implantation on the N-type conductive silicon carbide substrate by using at least one implantation element of hydrogen and helium, wherein the implantation dosage is 1E16/cm 2-1E 18/cm2, and the implantation energy is 20 keV-500 keV.
3. The method for manufacturing a silicon-based gallium nitride HEMT device according to claim 1, wherein the insulating treatment of the surface of the N-type conductive silicon carbide substrate after ion implantation comprises:
and (3) performing inversion doping on the surface of the N-type conductive silicon carbide substrate subjected to ion implantation by using at least one implantation element of boron and aluminum, wherein the implantation dosage is 1E 16-1E 19/cm < 2 >, and the implantation energy is 5-30 keV.
4. The method for manufacturing a silicon-based gallium nitride HEMT device according to claim 1 or 3, wherein the bonding of the silicon substrate and the N-type conductive silicon carbide substrate after the insulation treatment is performed, and the peeling treatment is performed on the bonded composite substrate to obtain a composite silicon-based substrate, and before the insulation treatment is performed on the surface of the composite silicon-based substrate, the method further comprises:
annealing the composite silicon-based substrate to activate the first insulating layer, wherein the annealing temperature is 1300-1370 ℃ and the annealing time is 3-6 h; wherein the annealing time length and the annealing temperature are in inverse relation.
5. The method of manufacturing a silicon-based gallium nitride HEMT device according to claim 4, further comprising, prior to annealing the composite silicon-based substrate to activate the first insulating layer:
performing carbon film protection on the composite silicon-based substrate; the thickness of the carbon film is 100-1000 nm, and the thickness of the carbon film is in inverse proportion to the annealing temperature and the annealing air pressure.
6. The method of manufacturing a silicon-based gallium nitride HEMT device according to claim 5, further comprising, after the annealing the composite silicon-based substrate to activate the first insulating layer:
and removing the carbon film remained on the surface of the annealed composite silicon-based substrate by dry etching.
7. The method for manufacturing a silicon-based gallium nitride HEMT device according to claim 1, wherein after the obtaining the silicon substrate, before the bonding the silicon substrate and the insulating-treated N-type conductive silicon carbide substrate, further comprises:
and (3) performing ion implantation on the surface of the silicon substrate by using at least one implantation element of boron and aluminum, wherein the implantation dosage is 1E 16-1E 19/cm < 2 >, and the implantation energy is 5-30 keV.
8. The method for manufacturing a silicon-based gallium nitride HEMT device according to claim 1, wherein after the bonded composite substrate is subjected to lift-off treatment to obtain a composite silicon-based substrate, the method further comprises, before the insulating treatment is performed on the surface of the composite silicon-based substrate to obtain the insulating-treated composite silicon-based substrate:
and polishing the surface of the composite silicon-based substrate to remove the silicon carbide film with the thickness of 100-300 nm, thereby obtaining the polished composite silicon-based substrate.
9. The method for preparing a silicon-based gallium nitride HEMT device according to claim 8, wherein the insulating treatment is performed on the surface of the composite silicon-based substrate to obtain the composite silicon-based substrate after the insulating treatment, comprising:
h ion implantation is carried out on the surface of the composite silicon-based substrate, and a second insulating layer is formed on the surface of the silicon carbide film, so that the composite silicon-based substrate after the insulating treatment is obtained; the composite silicon-based substrate after the insulation treatment comprises a silicon substrate, the first insulation layer, the silicon carbide film and the second insulation layer in sequence.
10. A silicon-based gallium nitride HEMT device, characterized in that the device is prepared by the preparation method of the silicon-based gallium nitride HEMT device according to any one of claims 1 to 9.
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| Publication number | Priority date | Publication date | Assignee | Title |
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008034637A (en) * | 2006-07-28 | 2008-02-14 | Fuji Xerox Co Ltd | Surface-emitting semiconductor laser and its manufacturing method |
| US20090168825A1 (en) * | 2007-12-26 | 2009-07-02 | Sony Corporation | Light-emitting element assembly and method for manufacturing the same |
| US20110097873A1 (en) * | 2008-06-20 | 2011-04-28 | Tien-Hsi Lee | Method for producing thin film |
| US20140217422A1 (en) * | 2012-03-30 | 2014-08-07 | Hitachi, Ltd. | Field effect silicon carbide transistor |
| KR20180063576A (en) * | 2016-12-02 | 2018-06-12 | 주식회사 루미스탈 | Nitride Semiconductor Device having Semi-insulating Layer and Method for manufacturing thereof |
| US20190035901A1 (en) * | 2015-11-12 | 2019-01-31 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences | Fluorinated graphene passivated algan/gan-based hemt device and manufacturing method |
| CN109686656A (en) * | 2018-11-13 | 2019-04-26 | 中国科学院上海微系统与信息技术研究所 | A kind of preparation method of the heterogeneous integrated carborundum films structure of silicon substrate |
| CN111540710A (en) * | 2020-05-11 | 2020-08-14 | 中国科学院上海微系统与信息技术研究所 | Preparation method of high-heat-conductivity gallium nitride high-power HEMT device |
| US20200266292A1 (en) * | 2019-02-19 | 2020-08-20 | AZ Power, Inc | Composite substrates of conductive and insulating or semi-insulating silicon carbide for gallium nitride devices |
| CN113571586A (en) * | 2021-07-12 | 2021-10-29 | 沈阳工业大学 | Double-doped source-drain single-transistor XNOR gate and manufacturing method thereof |
| CN114975096A (en) * | 2022-03-31 | 2022-08-30 | 北京清芯昇能半导体有限公司 | Bonding material and preparation method thereof, and semiconductor device |
| US20230009774A1 (en) * | 2021-07-06 | 2023-01-12 | Huawei Technologies Co., Ltd. | Composite substrate, composite substrate preparation method, semiconductor device, and electronic device |
-
2023
- 2023-06-20 CN CN202310736872.3A patent/CN116705605B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008034637A (en) * | 2006-07-28 | 2008-02-14 | Fuji Xerox Co Ltd | Surface-emitting semiconductor laser and its manufacturing method |
| US20090168825A1 (en) * | 2007-12-26 | 2009-07-02 | Sony Corporation | Light-emitting element assembly and method for manufacturing the same |
| US20110097873A1 (en) * | 2008-06-20 | 2011-04-28 | Tien-Hsi Lee | Method for producing thin film |
| US20140217422A1 (en) * | 2012-03-30 | 2014-08-07 | Hitachi, Ltd. | Field effect silicon carbide transistor |
| US20190035901A1 (en) * | 2015-11-12 | 2019-01-31 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences | Fluorinated graphene passivated algan/gan-based hemt device and manufacturing method |
| KR20180063576A (en) * | 2016-12-02 | 2018-06-12 | 주식회사 루미스탈 | Nitride Semiconductor Device having Semi-insulating Layer and Method for manufacturing thereof |
| CN109686656A (en) * | 2018-11-13 | 2019-04-26 | 中国科学院上海微系统与信息技术研究所 | A kind of preparation method of the heterogeneous integrated carborundum films structure of silicon substrate |
| US20200266292A1 (en) * | 2019-02-19 | 2020-08-20 | AZ Power, Inc | Composite substrates of conductive and insulating or semi-insulating silicon carbide for gallium nitride devices |
| CN111540710A (en) * | 2020-05-11 | 2020-08-14 | 中国科学院上海微系统与信息技术研究所 | Preparation method of high-heat-conductivity gallium nitride high-power HEMT device |
| US20230009774A1 (en) * | 2021-07-06 | 2023-01-12 | Huawei Technologies Co., Ltd. | Composite substrate, composite substrate preparation method, semiconductor device, and electronic device |
| CN113571586A (en) * | 2021-07-12 | 2021-10-29 | 沈阳工业大学 | Double-doped source-drain single-transistor XNOR gate and manufacturing method thereof |
| CN114975096A (en) * | 2022-03-31 | 2022-08-30 | 北京清芯昇能半导体有限公司 | Bonding material and preparation method thereof, and semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117476763A (en) * | 2023-12-28 | 2024-01-30 | 深圳天狼芯半导体有限公司 | E-HEMT with low leakage current and preparation method |
| CN117476763B (en) * | 2023-12-28 | 2024-05-28 | 深圳天狼芯半导体有限公司 | E-HEMT with low leakage current and preparation method |
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|---|---|
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