CN112530803B - Preparation method of GaN-based HEMT device - Google Patents

Preparation method of GaN-based HEMT device Download PDF

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CN112530803B
CN112530803B CN202011410376.1A CN202011410376A CN112530803B CN 112530803 B CN112530803 B CN 112530803B CN 202011410376 A CN202011410376 A CN 202011410376A CN 112530803 B CN112530803 B CN 112530803B
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layer
based hemt
hemt device
single crystal
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CN112530803A (en
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欧欣
石航宁
游天桂
伊艾伦
徐文慧
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off

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Abstract

The invention provides a preparation method of a GaN-based HEMT device, which can transfer a homoepitaxial high-quality AlGaN/GaN structure on a self-supporting GaN single crystal substrate to the supporting substrate, and grow a source electrode, a drain electrode and a gate electrode to obtain the high-performance GaN-based HEMT device after simply processing and removing a residual layer on the surface; the self-supporting GaN single crystal substrate has no loss and can be recycled, so that the cost is greatly reduced; according to the material characteristics of different supporting substrates, the heterogeneous integration of the GaN-based HEMT device and the supporting substrate can be realized, different advantages of the GaN-based HEMT device are exerted, the performance of the GaN-based HEMT device is improved, and the GaN-based HEMT device can stably work for a long time in a high-frequency and high-power state; the method can be applied to the preparation of N-polarity-face GaN-based HEMT devices and Ga-polarity-face GaN-based HEMT devices, and the application range is expanded.

Description

Preparation method of GaN-based HEMT device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a GaN-based HEMT device.
Background
Gallium Nitride (GaN) is a third-generation semiconductor material, and has been widely studied and applied due to its characteristics of large forbidden bandwidth (3.4eV), high breakdown field strength, excellent thermal conductivity, and large electron saturation velocity. The High Electron Mobility Transistor (HEMT) based on the AlGaN/GaN heterojunction has spontaneous polarization and piezoelectric polarization effects, can generate High-density two-dimensional Electron gas without doping, has small scattering on electrons and High Mobility, and can be applied to High-frequency and High-power electronic devices with excellent performance.
The GaN material is usually prepared by epitaxial growth on a foreign substrate, and the more common foreign substrates include Si (111) substrate, SiC substrate, sapphire substrate, etc., however, there are problems of non-negligible lattice mismatch and thermal mismatch between the foreign substrate and GaN, which will cause defects and Dislocation Density of the heteroepitaxial GaN to be very high, and the Threading Dislocation Density (TDD) usually reaches 108cm-2. High defect and high dislocation density can reduce the two-dimensional electron gas density of AlGaN/GaN heterojunction and increase the inverseThe leakage current is reduced, the service life of the GaN device is shortened, the reliability of the GaN device is influenced, and the epitaxial GaN material is easy to crack and warp due to thermal mismatch, so that the performance of the GaN device is seriously influenced by the existing method for preparing the GaN material by adopting a hetero-epitaxial method.
GaN materials with high quality and low dislocation defect density can be obtained by homoepitaxy on a self-supporting GaN single crystal substrate, so that the performance of the obtained AlGaN/GaN HEMT can be greatly improved. Dislocation density of the self-supporting GaN single crystal substrate can be as low as 105cm-2The AlGaN/GaN HEMT device based on the homoepitaxy of the self-supporting GaN single crystal substrate has the advantages of strong reliability, long service life, high two-dimensional electron gas density and excellent performance. However, the self-supporting GaN single crystal substrate has not been commercialized in a large scale, and one of the biggest obstacles is that the self-supporting GaN single crystal substrate is high in cost and price, and a high-quality 2-inch self-supporting GaN single crystal substrate is sold at a price of tens of thousands of yuan, which greatly hinders large-scale application, thereby limiting the application of manufacturing high-performance GaN-based HEMT devices.
Therefore, it is necessary to provide a method for manufacturing a GaN-based HEMT device.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a GaN-based HEMT device, which is used to solve the problems of poor device performance and high device manufacturing cost encountered in the prior art for manufacturing the GaN-based HEMT device.
In order to achieve the above and other related objects, the present invention provides a method for manufacturing a GaN-based HEMT device, comprising the steps of:
providing a GaN single crystal wafer having a polished surface;
sequentially forming a GaN buffer layer, a GaN channel layer, an AlN insert layer, an AlGaN barrier layer and a GaN cap layer on the polished surface of the GaN single crystal wafer;
performing ion implantation on the surface of the GaN cap layer, and forming a defect layer at the preset depth of the GaN buffer layer;
forming a first bonding dielectric layer on the surface of the GaN cap layer;
providing a support substrate;
forming a second bonding medium layer on the surface of the supporting substrate;
bonding the first bonding medium layer and the second bonding medium layer;
carrying out annealing treatment, and stripping along the defect layer to form a damaged layer;
carrying out surface treatment to remove the damaged layer and the GaN buffer layer;
forming an electrode in contact with the GaN channel layer, the electrode including a source electrode, a drain electrode, and a gate electrode.
Optionally, the thickness of the GaN buffer layer ranges from 100nm to 10 μm; the thickness range of the GaN channel layer is 50 nm-200 nm; the AlN insert layer is 0.1 nm-2 nm thick; the thickness range of the AlGaN barrier layer is 5 nm-35 nm; the thickness of the GaN cap layer is 1 nm-3 nm.
Optionally, the AlGaN barrier layer is AlxGa1-xAnd N layers, wherein x is more than 0 and less than 1.
Optionally, the ion implantation comprises one or a combination of H ion implantation and He ion implantation; when H ion implantation is adopted, the implantation energy of the H ions comprises 7 keV-1.1 MeV, and the implantation dosage comprises 1 x 1017ions/cm2～1×1018ions/cm2。
Optionally, the predetermined depth of the GaN buffer layer is 50nm to 10 μm.
Optionally, the support substrate comprises one of a silicon single crystal wafer, a silicon wafer whose surface is silicon oxide, a silicon carbide single crystal wafer, a diamond wafer, a sapphire wafer, and a metal piece; the metal sheet comprises one of an Ag metal sheet, a Cu metal sheet, an Au metal sheet and an Al metal sheet.
Optionally, the first bonding dielectric layer includes one of nano-silicon, silicon oxide, aluminum oxide and silicon nitride, and the second bonding dielectric layer includes one of nano-silicon, silicon oxide, aluminum oxide and silicon nitride; the thickness range of the first bonding medium layer is 1 nm-10 mu m, and the thickness range of the second bonding medium layer is 1 nm-10 mu m.
Optionally, the annealing treatment includes performing in an atmosphere formed by at least one of vacuum, nitrogen, argon, hydrogen, ammonia, and hydrogen chloride, wherein the annealing temperature includes 300 ℃ to 800 ℃, and the annealing time includes 1min to 24 h.
Optionally, the surface treatment method includes one of high temperature annealing, chemical mechanical polishing, wet etching and ion beam etching.
Optionally, the step of forming the electrode comprises:
sequentially forming Ti/Al/Ni/Au on the GaN channel layer, and annealing in a nitrogen atmosphere to form an ohmic contact source electrode and an ohmic contact drain electrode which are in contact with the GaN channel layer;
and sequentially forming Ni/Au on the GaN channel layer, and forming a Schottky contact gate electrode which is in contact with the GaN channel layer.
Optionally, the GaN-based HEMT device includes an N-polar-plane GaN-based HEMT device or a Ga-polar-plane GaN-based HEMT device.
As described above, according to the method for manufacturing a GaN-based HEMT device of the present invention, a high quality AlGaN/GaN structure homoepitaxially grown on a self-supporting GaN single crystal substrate can be transferred to the supporting substrate, and after a residual layer on the surface is removed by simple processing, a source, a drain, and a gate electrode are grown to obtain a high performance GaN-based HEMT device; the self-supporting GaN single crystal substrate has no loss and can be recycled, so that the cost is greatly reduced; according to the material characteristics of different supporting substrates, the heterogeneous integration of the GaN-based HEMT device and the supporting substrate can be realized, different advantages of the GaN-based HEMT device are exerted, the performance of the GaN-based HEMT device is improved, and the GaN-based HEMT device can stably work for a long time in a high-frequency and high-power state; furthermore, the method can be applied to the preparation of N-polar surface GaN-based HEMT devices and Ga-polar surface GaN-based HEMT devices so as to expand the application range.
Drawings
Fig. 1 shows a process flow diagram for fabricating a GaN-based HEMT device in the present invention.
FIG. 2 is a schematic view showing the structure of a GaN single crystal wafer provided in the present invention.
FIG. 3 is a schematic structural diagram of the GaN buffer layer, GaN channel layer, AlN insert layer, AlGaN barrier layer and GaN cap layer formed in the present invention.
FIG. 4 is a schematic view of a structure after ion implantation is performed to form a defect layer in the present invention.
Fig. 5 is a schematic structural diagram illustrating the formation of a first bonding dielectric layer according to the present invention.
Fig. 6 is a schematic structural diagram illustrating a second bonding medium layer formed on a supporting substrate according to the present invention.
Fig. 7 is a schematic structural diagram of the bonded first and second bonding dielectric layers according to the present invention.
FIG. 8 is a schematic view of the structure after annealing and stripping in the present invention.
FIG. 9 is a schematic view showing a structure of the present invention after surface treatment.
Fig. 10 is a schematic view showing a structure after electrodes are formed in the present invention.
Description of the element reference numerals
100 GaN single crystal wafer
100a polished surface
200 GaN buffer layer
201 defective layer
211. 212 damage layer
202. 203 residual GaN buffer layer
300 GaN channel layer
400 AlN insert layer
500 AlGaN barrier layer
600 GaN cap layer
701 first bonding dielectric layer
702 second bonding dielectric layer
800 support substrate
901 source electrode
902 drain electrode
903 gate electrode
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, the invention provides a method for manufacturing a GaN-based HEMT device, which can transfer a homoepitaxial high-quality AlGaN/GaN structure on a self-supporting GaN single crystal substrate to the supporting substrate, and grow a source, a drain and a gate electrode after simply processing and removing a residual layer on the surface to obtain the high-performance GaN-based HEMT device; the self-supporting GaN single crystal substrate has no loss and can be recycled, so that the cost is greatly reduced; according to the material characteristics of different supporting substrates, the heterogeneous integration of the GaN-based HEMT device and the supporting substrate can be realized, different advantages of the GaN-based HEMT device are exerted, the performance of the GaN-based HEMT device is improved, and the GaN-based HEMT device can stably work for a long time in a high-frequency and high-power state; furthermore, the method can be applied to the preparation of N-polar surface GaN-based HEMT devices and Ga-polar surface GaN-based HEMT devices so as to expand the application range.
Referring to fig. 2 to 10, the manufacturing method of the GaN-based HEMT device may specifically include the following steps:
first, referring to fig. 2, a GaN single crystal wafer 100 having a polished surface 100a is provided, and the size, thickness, and crystal orientation of the GaN single crystal wafer 100 may be selected as desired without being unduly limited thereto.
Next, referring to fig. 3, a GaN buffer layer 200, a GaN channel layer 300, an AlN insertion layer 400, an AlGaN barrier layer 500, and a GaN cap layer 600 are sequentially formed on the polished surface 100a of the GaN single crystal wafer 100.
By way of example, the thickness of the GaN buffer layer 200 ranges from 100nm to 10 μm, such as a value in any range of 100nm, 500nm, 1 μm, 5 μm, 10 μm, and the like; the thickness range of the GaN channel layer 300 is 50nm to 200nm, such as any value within the ranges of 80nm, 100nm, 150nm, 200nm, and the like; the AlGaN barrier layer 500 has a thickness in a range of 5nm to 35nm, for example, a thickness in any range of 5nm, 10nm, 20nm, 25nm, 30nm, 35nm, or the like; the thickness of the GaN cap layer 600 is 1nm to 3nm, such as a value in any range of 1nm, 2nm, 3nm, and the like.
Illustratively, the AlN insert layer 400 has a thickness of 0.1nm to 2nm, such as a value in any range of 0.1nm, 0.5nm, 1.5nm, 2nm, etc., preferably 1nm to 1.2nm, such as a value in any range of 1nm, 1.1nm, 1.2nm, etc.
Specifically, the AlN insertion layer 400 can improve the effective conduction band offset of the GaN channel layer 300 and the AlGaN barrier layer 500, so as to form a deeper and narrower quantum well, which is beneficial to improving the electron density of the channel; on the other hand, the two-dimensional electron gas can be inhibited from permeating into the AlGaN barrier layer 500, so that the channel electron mobility is improved, but when the AlN insertion layer 400 is too thick, as the lattice mismatch degree between the AIN material and the GaN material is high, which is about 2.4%, the too thick AlN insertion layer 400 introduces a great stress to the AlGaN barrier layer 500, so that the epitaxial quality of the AlGaN barrier layer 500 is reduced, and the mobility is reduced. Therefore, the AlN insertion layer 400 preferably has a thickness of 1 nm.
As an example, the AlGaN barrier layer 500 is AlxGa1-xAnd the N layer, wherein x is more than 0 and less than 1, and the value of x can be any range of values such as 0.25, 0.3, 0.5, 0.8 and the like.
Next, as shown in fig. 4, ion implantation is performed from the surface of the GaN cap layer 600 to form a defect layer 201 at a predetermined depth of the GaN buffer layer 200.
As an example, the ion implantation includes one or a combination of H ion implantation and He ion implantation; when H ion implantation is employed, the implantation energy of the H ions includes values in any range of 7keV to 1.1MeV, such as 7keV, 10keV, 50keV, 100keV, 1MeV, 1.1MeV, and the like, and the implantation dose includes 1 × 1017ions/cm2～1×1018ions/cm2E.g. 1X 1017ions/cm2、3×1017ions/cm2、5×1017ions/cm2、1×1018ions/cm2And the like in any range.
As an example, the predetermined depth of the GaN buffer layer 200 is 50nm to 10 μm, such as a thickness of 50nm, 1 μm, 5 μm, 10 μm, or any range of values.
Specifically, the arrows in fig. 4 indicate the direction of ion implantation. In one example, a single type ion implantation, which may include H ion implantation or He ion implantation, may be performed from the surface of the GaN cap layer 600. When the implanted ions are H ions, the H ions may damage the lattice formation of the GaN buffer layer 200 at the predetermined depth, that is, form the defect layer 201, and when annealing, the H ions migrate and gather in the defect layer 201 and generate pressure, and during a subsequent lift-off process, the GaN buffer layer 200 may realize lift-off at the defect layer 201, wherein the depth of forming the defect layer 201 is determined by the energy of ion implantation, and whether lift-off is determined by the dose of ion implantation. When the implanted ions are He ions, the He ions form the defect layer 201 at a preset depth in the GaN buffer layer 200, during annealing, the He ions migrate and gather in the defect layer 201 and generate pressure, and in a subsequent stripping process, the GaN buffer layer 200 can be stripped at the defect layer 201. In another example, co-implantation of two types of ions may also be performed from the surface of the GaN cap layer 600, that is, the implanted ions are He ions and H ions, where the He ions implanted first may be used to form a larger empty volume defect as described above, and the H ions implanted later may be captured by the larger empty volume defect formed by the He ion implantation, so as to increase the pressure inside the empty volume defect, and through the annealing process, the defect is more likely to grow, and finally a crack that can separate the GaN buffer layer 200 is formed, thereby promoting the GaN buffer layer 200 to be peeled at the defect layer 201, and effectively promoting the GaN buffer layer 200 to be peeled under the condition of a lower ion implantation dose, that is, effectively reducing the total ion implantation dose, thereby shortening the fabrication cycle and saving the production cost.
Next, referring to fig. 5, a first bonding dielectric layer 701 is formed on the surface of the GaN cap layer 600.
As an example, the first bonding dielectric layer 701 includes one of nano silicon, silicon oxide, aluminum oxide, and silicon nitride to form a good bonding property with the GaN cap layer 600; the thickness of the first bonding dielectric layer 701 includes a value in any range of 1nm to 10 μm, such as 1nm, 10nm, 50nm, 1 μm, 5 μm, 10 μm, and the like.
Next, referring to fig. 6, a supporting substrate 800 is provided, and a second bonding dielectric layer 702 is formed on a surface of the supporting substrate 800.
As an example, the second bonding dielectric layer 702 includes one of nano silicon, silicon oxide, aluminum oxide, and silicon nitride to form good bonding performance with the supporting substrate 800; the thickness of the second bonding dielectric layer 702 includes a value in any range of 1nm to 10 μm, such as 1nm, 10nm, 50nm, 1 μm, 5 μm, 10 μm, and the like.
Specifically, the second bonding dielectric layer 702 can form a good bonding performance with the supporting substrate 800, wherein the second bonding dielectric layer 702 and the first bonding dielectric layer 701 are preferably made of the same material, so as to further improve the subsequent bonding effect between the first bonding dielectric layer 701 and the second bonding dielectric layer 702 and improve the device quality.
As an example, the support substrate 800 includes one of a silicon single crystal wafer, a silicon wafer whose surface is silicon oxide, a silicon carbide single crystal wafer, a diamond wafer, a sapphire wafer, and a metal sheet; the metal sheet comprises one of an Ag metal sheet, a Cu metal sheet, an Au metal sheet and an Al metal sheet.
Next, referring to fig. 7, the first bonding dielectric layer 701 and the second bonding dielectric layer 702 are bonded.
Specifically, based on the selection of the materials of the first bonding dielectric layer 701 and the second bonding dielectric layer 702, in the bonding process, a structure with a good bonding effect can be formed by using a currently mature bonding technology, such as dielectric layer bonding, surface activation bonding, and the like. When the first bonding medium layer 701 and the second bonding medium layer 702 both adopt nano-silicon, surface activation bonding may be adopted, for example, the surface of the to-be-bonded piece is activated by argon ions, then a nano-silicon layer is deposited on the surfaces of the two to-be-bonded pieces, and then the nano-silicon layer is activated by argon ions, so that the two to-be-bonded pieces are bonded together under pressure. When the first bonding dielectric layer 701 is made of one of silicon oxide, aluminum oxide and silicon nitride, and the second bonding dielectric layer 702 is made of one of silicon oxide, aluminum oxide and silicon nitride, dielectric layer bonding may be adopted, for example, a bonding dielectric layer is deposited on the surfaces of two pieces to be bonded, and then a bonding dielectric layer is activated by one of nitrogen plasma, oxygen plasma and argon plasma, so that the two pieces to be bonded are bonded together by pressurization, and preferably, the first bonding dielectric layer 701 and the second bonding dielectric layer 702 have the same material, so as to further improve the bonding effect. Furthermore, the whole process of surface activation bonding needs to be carried out in a vacuum environment, the requirement on process conditions is high, but extremely strong bonding strength can be obtained, and the bonding of the dielectric layer can be carried out in air, so that the process is simple, but the bonding strength is relatively low, and the surface activation bonding can be selected according to the requirement in specific application.
Next, referring to fig. 8, annealing is performed to perform peeling along the defect layer 201.
By way of example, the annealing treatment includes performing under an atmosphere formed by at least one of vacuum, nitrogen, argon, hydrogen, ammonia, and hydrogen chloride, wherein the annealing temperature includes a value in any range of 300 ℃ to 800 ℃, such as 300 ℃, 400 ℃, 500 ℃, 600 ℃, 800 ℃, and the like, and the annealing time includes a value in any range of 1min to 24h, such as 1min, 30min, 1h, 6h, 24h, and the like.
Specifically, since the first bonding dielectric layer 701 and the second bonding dielectric layer 702 can form good bonding, during annealing, implanted H or/and He ions migrate and gather, so that defects grow to be stripped, and the residual GaN buffer layer 202, the residual GaN buffer layer 203, the damaged layer 211 and the damaged layer 212 are formed.
Next, referring to fig. 9, a surface treatment is performed to remove the damaged layer 211 and the remaining GaN buffer layer 202.
As an example, the surface treatment method includes one of high temperature annealing, chemical mechanical polishing, wet etching and ion beam etching, which may be selected as needed, and the damaged layer 211 and the residual GaN buffer layer 202 may be removed by the surface treatment. Further, the damaged layer 212 and the GaN buffer layer 203 remaining may be surface-treated, and the free-standing GaN single crystal wafer 100 may be recovered without loss for recycling, thereby reducing the cost.
Next, referring to fig. 10, electrodes including a source electrode 901, a drain electrode 902, and a gate electrode 903 are formed in contact with the GaN channel layer 300.
As an example, the step of forming the electrode includes:
sequentially forming Ti/Al/Ni/Au on the GaN channel layer 300, and annealing in a nitrogen atmosphere to form an ohmic contact source electrode and an ohmic contact drain electrode which are in contact with the GaN channel layer 300;
Ni/Au is sequentially formed on the GaN channel layer 300 to form a schottky contact gate electrode in contact with the GaN channel layer 300.
As an example, the GaN-based HEMT device includes an N-polarity-face GaN-based HEMT device or a Ga-polarity-face GaN-based HEMT device. When the GaN-based HEMT device is an N-polar surface GaN-based HEMT device, the GaN-based HEMT device is prepared by adopting a Ga-surface GaN single crystal wafer, and the GaN-based HEMT device with the N-polar surface can be finally obtained after peeling transfer (turnover inversion) so as to be beneficial to manufacturing a low-resistance ohmic contact electrode, and the barrier layer below the two-dimensional electron gas channel can be used as a back barrier so as to be beneficial to avoiding a short channel effect, so that the GaN-based HEMT device with high performance can be obtained. Of course, the GaN-based HEMT device may also be a Ga-polar-plane GaN-based HEMT device as required, and details are not described here.
The invention is further described below by means of specific examples.
Example one
As shown in FIG. 2, a Ga-face-polished GaN single-crystal wafer 100 having a diameter of 2 inches and a thickness of 350 μm and having a (0001) crystal orientation was first provided.
As shown in FIG. 3, a 2 μm thick GaN buffer layer 200, a 100nm thick GaN channel layer 300, a 1nm thick AlN insert layer 400,25nm thick AlXGa1-XAn N-barrier layer 500, where x is 0.25, 2nm thick GaN cap layer 600; forming a first composite structure.
Referring to FIG. 4, H-ion implantation is performed on the first composite structure from the GaN cap layer 600 direction, wherein the H-ion implantation energy is 35keV and the dosage is 2.5 × 1017ions/cm2The implantation angle was 7 °. H ions are implanted to a preset depth to form an ion implantation defect layer 201, the defect layer 201 is formed in the GaN buffer layer 200, a residual GaN buffer layer 202 is arranged above the defect layer 201, and a residual GaN buffer layer 203 is arranged below the defect layer 201 to form a second composite structure.
As shown in fig. 5 and fig. 6, a silicon single crystal wafer with a diameter of 2 inches and a thickness of 500 μm and a (001) crystal orientation is provided as a supporting substrate 800, bonding dielectric layers are respectively deposited on the surfaces of the second composite structure and the silicon single crystal wafer to form a first bonding dielectric layer 701 on the surface of the GaN cap layer 600 in the second composite structure, and a second bonding dielectric layer 702 on the surface of the silicon single crystal wafer, wherein the bonding dielectric layers are silicon oxide and have a thickness of 1 μm.
As shown in fig. 7, the bonding medium layers are activated and bonded using nitrogen plasma to form a third composite structure.
As shown in fig. 8, the third composite structure is annealed in a nitrogen atmosphere at 450 ℃ for 6h, so that the third composite structure is peeled along the defect layer 201. Wherein the defect layer 201 forms a damaged layer 211 and a damaged layer 212, resulting in a fourth composite structure.
As shown in fig. 9, the fourth composite structure is surface-treated by a Chemical Mechanical Polishing (CMP) process to remove the damaged layer 211 and the remaining GaN buffer layer 202, thereby obtaining a fifth composite structure. It should be understood that the GaN single crystal wafer 100 can be recycled after surface treatment to remove the damaged layer 212 and the residual GaN buffer layer 203 on the surface, thereby greatly reducing the cost.
As shown in fig. 10, Ti/Al/Ni/Au was sequentially grown on the GaN channel layer 300 by electron beam evaporation to a thickness of 20nm/100nm/25nm/50nm in sequence, and annealed at 870 ℃ for 30 seconds in a nitrogen atmosphere to form an ohmic contact source electrode and an ohmic contact drain electrode in contact with the GaN channel layer 300; and growing Ni/Au on the GaN channel layer 300 by electron beam evaporation in sequence, wherein the thicknesses of the Ni/Au are 50nm/150nm in sequence, and forming a Schottky contact gate electrode which is in contact with the GaN channel layer 300 to obtain the GaN-based HEMT device with the N-polar surface.
The GaN-based HEMT device can realize the heterogeneous integration of the AlGaN/GaN HEMT and the silicon single crystal wafer supporting substrate, and can subsequently realize the single-chip heterogeneous integration of the GaN photoelectric/electronic device and the Si CMOS integrated circuit.
Example two
As shown in FIG. 2, a Ga-face-polished GaN single-crystal wafer 100 having a size of 1cm × 1cm and a thickness of 300 μm in the (0001) crystal orientation was first provided.
As shown in FIG. 3, a 10 μm thick GaN buffer layer 200, a 150nm thick GaN channel layer 300, a 1nm thick AlN insert layer 400, and a 30nm thick Al layer were sequentially grown on the polished surface 100a of the GaN single crystal wafer 100 by a Metal Organic Chemical Vapor Deposition (MOCVD) processXGa1-XN-barrier layer 500, where x is 0.25, 2nm thick GaN cap layer 600, constitutes a first composite structure.
As shown in fig. 4, H ion implantation is performed on the first composite structure from the direction of the GaN cap layer 600, wherein the H ion implantation energy is 75keV and the dose is 3.5 × 1017ions/cm2The implantation angle was 7 °. H ions are implanted to a preset depth to form an ion implantation defect layer 201, the defect layer 201 is formed in the GaN buffer layer 200, a residual GaN buffer layer 202 is arranged above the defect layer 201, and a residual GaN buffer layer 203 is arranged below the defect layer 201 to form a second composite structure.
As shown in fig. 5 and fig. 6, a diamond wafer with a size of 1cm × 1cm and a thickness of 200 μm is provided as a supporting substrate 800, bonding dielectric layers are respectively deposited on the surfaces of the second composite structure and the diamond wafer, so as to form a first bonding dielectric layer 701 on the surface of the GaN cap layer 600 in the second composite structure, and form a second bonding dielectric layer 702 on the surface of the diamond wafer, wherein the bonding dielectric layers are all made of nano silicon and have a thickness of 6 nm.
And as shown in fig. 7, activating the bonding medium layer by using argon plasma, and bonding the bonding medium layer to form a third composite structure.
As shown in fig. 8, the third composite structure is annealed in an argon atmosphere at 550 ℃ for 4 hours, so that the third composite structure is peeled along the defect layer 201. Wherein the defect layer 201 forms a damaged layer 211 and a damaged layer 212, resulting in a fourth composite structure.
As shown in fig. 9, the fourth composite structure is surface-treated by a Chemical Mechanical Polishing (CMP) process to remove the damaged layer 211 and the remaining GaN buffer layer 202, thereby obtaining a fifth composite structure. It should be understood that the GaN single crystal wafer 100 can be recycled after surface treatment to remove the damaged layer 212 and the residual GaN buffer layer 203 on the surface, thereby greatly reducing the cost.
As shown in fig. 10, Ti/Al/Ni/Au is sequentially grown on the GaN channel layer 300 by electron beam evaporation to a thickness of 20nm/130nm/50nm/150nm, and annealed at 890 ℃ for 30 seconds in a nitrogen atmosphere to form an ohmic contact source electrode and an ohmic contact drain electrode in contact with the GaN channel layer 300; and growing Ni/Au on the GaN channel layer 300 by electron beam evaporation in sequence, wherein the thicknesses of the Ni/Au are 50nm/150nm in sequence, and forming a Schottky contact gate electrode which is in contact with the GaN channel layer 300 to obtain the GaN-based HEMT device with the N-polar surface.
The GaN-based HEMT device can realize the heterogeneous integration of the AlGaN/GaN HEMT and the diamond wafer supporting substrate, the diamond wafer supporting substrate can provide a high-quality heat dissipation environment for the HEMT device, the performance of the HEMT device is greatly improved, the GaN-based HEMT device with an N polar surface is beneficial to manufacturing a low-resistance ohmic contact electrode, and a barrier layer below a two-dimensional electron gas channel can be used as a back barrier, so that the short channel effect is avoided, and the GaN-based HEMT device with high performance can be obtained.
EXAMPLE III
As shown in FIG. 2, a Ga-face polished GaN single crystal wafer 100 having a diameter of 2 inches and a thickness of 300 μm and having a (0001) crystal orientation was first provided.
As shown in FIG. 3, a 5 μm thick GaN buffer layer 200, a 50nm thick GaN channel layer 300, a 1nm thick AlN insert layer 400, and a 20nm thick Al layer were sequentially grown on the polished surface 100a of the GaN single crystal wafer 100 by a Metal Organic Chemical Vapor Deposition (MOCVD) processXGa1-XAn N-barrier layer 500, where x is 0.25, 3nm thick GaN cap layer 600; forming a first composite structure.
Performing H ion implantation on the first composite structure from the GaN cap layer direction, wherein the H ion implantation energy is 150keV and the dosage is 5 × 1017ions/cm2The implantation angle was 7 °. H ions are implanted to a preset depth to form an ion implantation defect layer 201, the defect layer 201 is formed in the GaN buffer layer 200, a residual GaN buffer layer 202 is arranged above the defect layer 201, and a residual GaN buffer layer 203 is arranged below the defect layer 201 to form a second composite structure.
As shown in fig. 5 and 6, a silicon carbide single crystal wafer with a diameter of 2 inches and a thickness of 350 μm is provided as a supporting substrate 800, bonding dielectric layers are respectively deposited on the surfaces of the second composite structure and the silicon carbide single crystal wafer, so as to form a first bonding dielectric layer 701 on the surface of the GaN cap layer 600 in the second composite structure, and form a second bonding dielectric layer 702 on the surface of the silicon single crystal wafer, wherein the bonding dielectric layers are both made of silicon oxide and have a thickness of 500 nm.
As shown in fig. 7, the bonding dielectric layers are activated and bonded using oxygen plasma to form a third composite structure.
As shown in fig. 8, the third composite structure is annealed in a vacuum atmosphere at 600 ℃ for 5 hours, so that the third composite structure is peeled off along the defect layer 201. Wherein the defect layer 201 forms a damaged layer 211 and a damaged layer 212, resulting in a fourth composite structure.
As shown in fig. 9, the fourth composite structure is surface-treated by a Chemical Mechanical Polishing (CMP) process to remove the damaged layer 211 and the remaining GaN buffer layer 202, thereby obtaining a fifth composite structure. It should be understood that the GaN single crystal wafer 100 can be recycled after surface treatment to remove the damaged layer 212 and the residual GaN buffer layer 203 on the surface, thereby greatly reducing the cost.
As shown in fig. 10, Ti/Al/Ni/Au was sequentially grown on the GaN channel layer 300 by electron beam evaporation to a thickness of 20nm/100nm/25nm/50nm in sequence, and annealed at 870 ℃ for 30 seconds in a nitrogen atmosphere to form an ohmic contact source electrode and an ohmic contact drain electrode in contact with the GaN channel layer 300; and growing Ni/Au on the GaN channel layer 300 by electron beam evaporation in sequence, wherein the thicknesses of the Ni/Au are 50nm/150nm in sequence, and forming a Schottky contact gate electrode which is in contact with the GaN channel layer 300 to obtain the GaN-based HEMT device with the N-polar surface.
The GaN-based HEMT device can realize the heterogeneous integration of the AlGaN/GaN HEMT and the silicon carbide single crystal wafer supporting substrate, the silicon carbide single crystal wafer supporting substrate can provide a high-quality heat dissipation environment for the HEMT device, the performance of the HEMT device is greatly improved, the GaN-based HEMT device with an N polar surface is beneficial to manufacturing a low-resistance ohmic contact electrode, and a barrier layer below a two-dimensional electron gas channel can be used as a back barrier, so that the short channel effect is avoided, and the GaN-based HEMT device with high performance can be obtained.
In summary, the method for preparing the GaN-based HEMT device of the present invention can transfer the homoepitaxial high quality AlGaN/GaN structure on the self-supporting GaN single crystal substrate to the supporting substrate, and after the residual layer on the surface is removed by simple processing, the high performance GaN-based HEMT device can be obtained by growing the source, drain and gate electrodes; the self-supporting GaN single crystal substrate has no loss and can be recycled, so that the cost is greatly reduced; according to the material characteristics of different supporting substrates, the heterogeneous integration of the GaN-based HEMT device and the supporting substrate can be realized, different advantages of the GaN-based HEMT device are exerted, the performance of the GaN-based HEMT device is improved, and the GaN-based HEMT device can stably work for a long time in a high-frequency and high-power state; furthermore, the method can be applied to the preparation of N-polar surface GaN-based HEMT devices and Ga-polar surface GaN-based HEMT devices so as to expand the application range.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A preparation method of a GaN-based HEMT device is characterized by comprising the following steps:
providing a GaN single crystal wafer having a polished surface;
sequentially forming a GaN buffer layer, a GaN channel layer, an AlN insert layer, an AlGaN barrier layer and a GaN cap layer on the polished surface of the GaN single crystal wafer;
performing ion implantation on the surface of the GaN cap layer to form a defect layer at a preset depth of the GaN buffer layer, wherein the thickness range of the GaN buffer layer is 100 nm-10 mu m, and the preset depth of the GaN buffer layer is 50 nm-10 mu m;
forming a first bonding dielectric layer on the surface of the GaN cap layer;
providing a support substrate;
forming a second bonding medium layer on the surface of the supporting substrate;
bonding the first bonding medium layer and the second bonding medium layer;
carrying out annealing treatment, and stripping along the defect layer to form a damaged layer;
carrying out surface treatment to remove the damaged layer and the GaN buffer layer;
forming an electrode in contact with the GaN channel layer, the electrode including a source electrode, a drain electrode, and a gate electrode.
2. The method for manufacturing a GaN-based HEMT device according to claim 1, wherein: the thickness range of the GaN channel layer is 50 nm-200 nm; the AlN insert layer is 0.1 nm-2 nm thick; the thickness range of the AlGaN barrier layer is 5 nm-35 nm; the thickness of the GaN cap layer is 1 nm-3 nm.
3. The method for manufacturing a GaN-based HEMT device according to claim 1, wherein: the AlGaN barrier layer is AlxGa1-xAnd N layers, wherein x is more than 0 and less than 1.
4. The method for manufacturing a GaN-based HEMT device according to claim 1, wherein: the ion implantation comprises one or a combination of H ion implantation and He ion implantation; when H ion implantation is adopted, the implantation energy of the H ions comprises 7 keV-1.1 MeV, and the implantation dosage comprises 1 x 1017ions/cm2～1×1018ions/cm2。
5. The method for manufacturing a GaN-based HEMT device according to claim 1, wherein: the support substrate comprises one of a silicon single crystal wafer, a silicon wafer with a silicon oxide surface, a silicon carbide single crystal wafer, a diamond wafer, a sapphire wafer and a metal sheet; the metal sheet comprises one of an Ag metal sheet, a Cu metal sheet, an Au metal sheet and an Al metal sheet.
6. The method for manufacturing a GaN-based HEMT device according to claim 1, wherein: the first bonding medium layer comprises one of nano silicon, silicon oxide, aluminum oxide and silicon nitride, and the second bonding medium layer comprises one of nano silicon, silicon oxide, aluminum oxide and silicon nitride; the thickness range of the first bonding medium layer is 1 nm-10 mu m, and the thickness range of the second bonding medium layer is 1 nm-10 mu m.
7. The method for manufacturing a GaN-based HEMT device according to claim 1, wherein: the annealing treatment comprises the step of carrying out the annealing treatment under the atmosphere formed by at least one of vacuum, nitrogen, argon, hydrogen, ammonia and hydrogen chloride, wherein the annealing temperature comprises 300-800 ℃, and the annealing time comprises 1 min-24 h.
8. The method for manufacturing a GaN-based HEMT device according to claim 1, wherein: the surface treatment method comprises one of high-temperature annealing, chemical mechanical polishing, wet etching and ion beam etching.
9. The method for manufacturing a GaN-based HEMT device according to claim 1, wherein: the step of forming the electrode comprises:
sequentially forming Ti/Al/Ni/Au on the GaN channel layer, and annealing in a nitrogen atmosphere to form an ohmic contact source electrode and an ohmic contact drain electrode which are in contact with the GaN channel layer;
and sequentially forming Ni/Au on the GaN channel layer to form a Schottky contact gate electrode in contact with the GaN channel layer.
10. The method for manufacturing a GaN-based HEMT device according to any one of claims 1 to 9, characterized in that: the GaN-based HEMT device comprises an N-polarity-face GaN-based HEMT device or a Ga-polarity-face GaN-based HEMT device.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465745A (en) * 2013-09-24 2015-03-25 瑞萨电子株式会社 Method Of Manufacturing A Semiconductor Device And The Semiconductor Device
CN106504988A (en) * 2016-11-30 2017-03-15 陕西科技大学 A kind of diamond heat-sink substrate GaN HEMTs preparation methods
CN111540684A (en) * 2020-05-11 2020-08-14 中国科学院上海微系统与信息技术研究所 Microelectronic device of diamond-based heterogeneous integrated gallium nitride thin film and transistor and preparation method thereof

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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465745A (en) * 2013-09-24 2015-03-25 瑞萨电子株式会社 Method Of Manufacturing A Semiconductor Device And The Semiconductor Device
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CN111540684A (en) * 2020-05-11 2020-08-14 中国科学院上海微系统与信息技术研究所 Microelectronic device of diamond-based heterogeneous integrated gallium nitride thin film and transistor and preparation method thereof

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