CN106449663B - Semiconductor-on-insulator structure and method of fabrication - Google Patents
Semiconductor-on-insulator structure and method of fabrication Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Abstract
The invention discloses a semiconductor-on-insulator structure and a preparation method thereof. The method comprises the following steps: (1) sequentially forming an antimonide transition layer and an antimonide semiconductor layer on the upper surface of the substrate so as to obtain a first complex; (2) performing ion implantation treatment on the first complex, wherein the implanted ions contain hydrogen ions; (3) carrying out bonding treatment on the first composite and a substrate so as to obtain a second composite, wherein the upper surface of the substrate is provided with an insulating layer, and the insulating layer is in contact with the antimonide semiconductor layer in the bonding treatment; and (4) subjecting the second composite to a peeling treatment so as to obtain a third composite and the semiconductor-on-insulator structure, respectively. The method has simple operation steps and lower requirements on instruments and equipment, and can avoid the limitation on a semiconductor-on-insulator structure caused by undersize of a wafer when the antimonide wafer is used for preparation.
Description
Technical Field
The present invention relates to the field of semiconductor technology and semiconductor manufacturing, and in particular, to semiconductor-on-insulator structures and methods of fabrication.
Background
With the development of semiconductor technology, the feature size of metal-oxide-semiconductor field effect transistor (MOSFET) is continuously reduced and its operation speed is continuously increased. However, silicon integrated circuits based on Moore's law have been rapidly developed for decades, and for Si-based materials per se, current MOSFET devices have been approaching the dual physical and technological limits. Thus, to further improve the performance of MOSFET devices, those skilled in the art have proposed various methods to improve the performance of MOSFET devices. For example, a III-V antimonide semiconductor material, with SiO2The Semiconductor-on-insulator (SOI) structure formed by directly bonding the Si sheets of the insulating layer is a Semiconductor material with high electron and hole mobility, and has a good application prospect. For example, GaSb materials and SiO2The Si pieces of the insulating layer are bonded to form a GaSbOI (GaSb-on-insulator) structure. The structure not only has high electron mobility, but also has high hole mobility, and the materials such as GaSb can avoid the limitation that the materials cannot be applied to Si-based MOSFET elements and circuits because the materials are not easy to integrate with Si wafers.
However, the current semiconductor-on-insulator structure and the method for fabricating the same still remain to be improved.
Disclosure of Invention
The present invention is made based on the discovery and recognition by the inventors of the following facts and problems:
the existing semiconductor-on-insulator fabrication technology is the Smart-cut (Smart-cut) technology, i.e., hydrogen ions are implanted into a III-V antimonide semiconductor wafer, and then the III-V antimonide semiconductor wafer is combined with a silicon oxide (SiO)2And directly bonding the Si sheets on the surface layer of the insulating oxide, and then realizing stripping by high-temperature annealing to form the semiconductor-on-insulator structure. However, the wafer diameter of current III-V antimonide semiconductor wafers is not large. For example, current commercially available GaSb polished wafers are approximately 2 inches in diameter, and thus it is difficult to obtain larger diameter (e.g., 8-12 inches) semiconductor-on-insulator structures using the smart-cut technique described above, while the current mainstream Si wafers are 8-12 inches in diameter, and thus the prepared semiconductor-on-insulator structures are difficult to directly replace Si-based semiconductor structures for MOSFET devices. Moreover, the smart cut technology cannot easily obtain a semiconductor-on-insulator structure with a very thin antimonide layer (less than 100nm), and advanced device structures often require the thickness of the antimonide film in the semiconductor-on-insulator film to be less than 100 nm.
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
In one aspect of the invention, a method of fabricating a semiconductor-on-insulator structure is presented. According to an embodiment of the invention, the method comprises: (1) sequentially forming an antimonide transition layer and an antimonide semiconductor layer on the upper surface of the substrate so as to obtain a first complex; (2) performing ion implantation treatment on the first complex, wherein the implanted ions contain hydrogen ions; (3) carrying out bonding treatment on the first composite and a substrate so as to obtain a second composite, wherein the upper surface of the substrate is provided with an insulating layer, and the insulating layer is in contact with the antimonide semiconductor layer in the bonding treatment; and (4) subjecting the second composite to a lift-off process so as to obtain a third composite and the semiconductor-on-insulator structure, respectively. The method has simple operation steps and lower requirements on instruments and equipment, and can avoid the limitation on the size of a semiconductor structure on an insulator caused by the undersize of a wafer when the antimonide wafer is used for preparation.
According to an embodiment of the present invention, the antimonide transition layer and the antimonide semiconductor layer are each independently formed of a group III-V antimonide semiconductor material.
According to an embodiment of the invention, the III-V antimonide semiconductor material is MSb, wherein M is at least one of Ga, In, and Al.
According to an embodiment of the invention, the III-V antimonide semiconductor material is GaSb, InSb, AlSb, InxGa1-xSb、AlyGa1-ySb、InzAl1-zSb and InmAlnGa1-m-nAt least one of Sb, wherein x, y, z, m and n are each independently greater than 0 and less than 1.
According to an embodiment of the present invention, the antimonide semiconductor layer and the antimonide transition layer are each independently formed by epitaxial growth. This can further improve the quality of the formed antimonide semiconductor layer.
According to an embodiment of the present invention, in the step (1), a substrate transition layer is formed on an upper surface of the substrate in advance before the formation of the antimonide transition layer. The antimonide semiconductor layer and the substrate transition layer have a better interface state, the substrate transition layer can reduce the defect density of heterogeneous external delay and prevent substrate elements (such as Si) from diffusing to the surface and entering the antimonide transition layer, and therefore the quality of a finally formed semiconductor-on-insulator structure can be further improved.
According to an embodiment of the invention, the thickness of the substrate transition layer is not less than 1 micrometer. Thereby, the quality of the base transition layer can be further improved.
According to the embodiment of the present invention, in the step (1), before the formation of the antimonide semiconductor layer, an ion adsorption layer is formed on the upper surface of the antimonide transition layer in advance. Thus, the ion-adsorbing layer can improve the adsorption and aggregation ability of the implanted hydrogen ions, and the implantation dose of the hydrogen ions required for the stripping treatment can be advantageously reduced.
According to an embodiment of the present invention, the ion-adsorbing layer comprises the group III-V antimonide semiconductor material described above, the group III-V antimonide semiconductor material in the ion-adsorbing layer having a different lattice constant than the group III-V antimonide semiconductor material in the antimonide transition layer and the antimonide semiconductor layer. This can further improve the adsorption and aggregation ability of the ion-adsorbing layer with respect to the implanted hydrogen ions.
According to an embodiment of the present invention, the thickness of the ion adsorption layer is 2 to 50 nm.
According to an embodiment of the present invention, in the step (4), the peeling treatment is performed in the ion adsorption layer.
According to an embodiment of the present invention, the substrate and the base are each independently formed of silicon.
According to an embodiment of the present invention, the step (1) further comprises: and forming a first passivation layer on the upper surface of the antimonide semiconductor layer. This can further improve the interface state between the antimonide semiconductor layer and the insulating layer (oxide).
According to an embodiment of the present invention, further comprising: and forming a second passivation layer on the upper surface of the semiconductor-on-insulator structure. Thereby, the performance of the semiconductor-on-insulator structure can be further improved.
According to an embodiment of the present invention, the implantation doses of the ion implantation process are: 0.5X 1016/cm2～1×1017/cm2. The method provided by the invention can realize stripping treatment under the injection dosage, and is greatly reduced compared with the existing intelligent stripping technology, thereby being beneficial to reducing the production cost.
According to the embodiment of the invention, the temperature of the first complex is 200-600 ℃ during the ion implantation treatment. Thereby, the implantation dose is advantageously further reduced.
According to an embodiment of the present invention, in the semiconductor-on-insulator structure, the thickness of the antimonide semiconductor layer is less than 100 nm. Thereby, the performance of the semiconductor-on-insulator structure is advantageously further improved.
According to an embodiment of the present invention, after step (1) and before step (2), the upper surface of the first composite body is subjected to polishing treatment and/or annealing treatment in advance. Therefore, a flat upper surface is obtained, and the bonding quality of the subsequent bonding process can be improved.
According to the embodiment of the invention, the annealing treatment is carried out in a hydrogen-containing atmosphere at 600-1100 ℃. This can improve the effect of the annealing treatment.
According to an embodiment of the present invention, the lift-off process comprises an anneal at a temperature of 200-600 degrees Celsius.
According to an embodiment of the invention, the method further comprises: after the step (4), performing polishing treatment and/or annealing treatment on the surface of the semiconductor-on-insulator structure. Thereby, the surface flatness of the obtained semiconductor-on-insulator structure can be further improved.
According to an embodiment of the invention, the method further comprises: and (3) recycling the third complex, and returning the third complex to the step (2) for ion implantation treatment. Thus, the third composite can be recycled, so that the production cost can be saved, the production efficiency can be improved, and the production time can be shortened.
According to an embodiment of the present invention, before returning the third complex to step (2), the following processing is performed on the third complex in advance: polishing and/or annealing the upper surface of the third composite body; and forming the antimonide semiconductor layer on the upper surface of the third composite. This can further enhance the effect of recycling the third complex.
In another aspect of the invention, the invention is directed to a semiconductor-on-insulator structure. According to an embodiment of the present invention, the semiconductor-on-insulator structure is formed by the method described above. The semiconductor-on-insulator structure thus has all the features and advantages of the semiconductor-on-insulator structure obtained by the method described above, which will not be described in detail herein.
According to an embodiment of the present invention, the diameter of the antimonide semiconductor layer in the semiconductor-on-insulator structure is not less than 6 inches. Since the semiconductor-on-insulator structure is formed using the method described above, the size of the antimonide semiconductor layer in the semiconductor-on-insulator structure may not be limited by the size of the antimonide wafer.
Drawings
FIG. 1 is a schematic flow chart of a method of fabricating a semiconductor-on-insulator structure according to one embodiment of the present invention;
FIG. 2 is a schematic flow chart of a method of fabricating a semiconductor-on-insulator structure according to another embodiment of the present invention;
FIG. 3 is a schematic flow chart of a method of fabricating a semiconductor-on-insulator structure according to yet another embodiment of the present invention;
FIG. 4 is a schematic flow chart diagram of a method of fabricating a semiconductor-on-insulator structure according to yet another embodiment of the present invention;
FIG. 5 is a schematic flow chart diagram of a method of fabricating a semiconductor-on-insulator structure according to yet another embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a semiconductor-on-insulator structure according to one embodiment of the present invention; and
figure 7 is a schematic structural diagram of a semiconductor-on-insulator structure according to another embodiment of the present invention.
Description of the drawings:
1000: a first composite body; 2000: a second composite; 3000: a third complex; 4000: a semiconductor-on-insulator structure;
100: a substrate; 200: an antimonide transition layer; 300: an antimonide semiconductor layer; 400: an ion adsorption layer; 500: a substrate; 600: an insulating layer;
700: an antimonide semiconductor layer in a semiconductor-on-insulator structure; 800: the antimonide semiconductor layer remains in the third composite; 10: a base transition layer; 20: a first passivation layer; 30: a second passivation layer; 1A: a residual ion adsorption layer in the semiconductor-on-insulator structure; 1B: the ion-adsorbing layer remains in the third composite.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the description of the present invention, it is to be understood that the terms "upper", "lower", and the like, indicate orientations or positional relationships based on those shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the present invention, the term "Semiconductor-on-insulator structure" particularly refers to a structure (Semiconductor on insulator) having a group III-V antimonide Semiconductor material on the upper surface of an insulating layer. The semiconductor-on-insulator structure includes a group III-V antimonide semiconductor material, an insulating layer, and a substrate. That is, when the group III-V antimonide semiconductor material is GaSb, the semiconductor-on-insulator structure is a GaSbOI structure; when the III-V antimonide semiconductor material is InSb, the semiconductor-on-insulator structure is an InSbOI structure; when the III-V antimonide semiconductor material is AlSb, the semiconductor-on-insulator structure is an AlSbOI structure.
In one aspect of the invention, a method of fabricating a semiconductor-on-insulator structure is presented. According to an embodiment of the invention, with reference to fig. 1, the method comprises:
s1: forming a first composite
According to an embodiment of the present invention, in this step, an antimonide transition layer and an antimonide semiconductor layer are formed in this order on the upper surface of the substrate so as to obtain a first composite body. According to an embodiment of the present invention, antimonyThe compound transition layer and the antimonide semiconductor layer are formed of III-V antimonide semiconductor materials. The materials for forming the antimonide transition layer and the antimonide semiconductor layer are respectively and independently selected from III-V antimonide semiconductor materials, namely, the materials of the antimonide transition layer and the antimonide semiconductor layer can be the same or different. According to an embodiment of the present invention, the III-V antimonide semiconductor material may be MSb, wherein M is at least one of Ga, In, and Al. That is, the III-V antimonide semiconductor material may be GaSb, InSB, or AlSb, or may be a ternary antimonide or a quaternary antimonide composed of Ga, In, Al, and Sb. When MSb is a ternary or quaternary antimonide, the atomic ratio of the sum of a plurality of IIIA group elements constituting the ternary antimonide or quaternary antimonide to Sb element is 1: 1. For example, according to the embodiment of the present invention, MSb may be GaSb, InSb or AlSb, or InxGa1-xSb、AlyGa1-ySb or InzAl1-zSb or InmAlnGa1-m-nAnd (5) Sb. Wherein x, y, z, m and n are each independently greater than 0 and less than 1. According to an embodiment of the present invention, the substrate may be a silicon substrate. The antimonide transition layer can play a role in reducing diffusion of Si in the substrate to the surface, relieving lattice mismatch, reducing defects and the like. According to a specific embodiment of the present invention, the antimonide transition layer may be a non-strained transition layer, which may have a thickness of 1-3 microns. The antimonide semiconductor layer in the first composite is indirectly formed on the upper surface of the substrate, and thus the lateral dimension of the antimonide semiconductor layer may be equal to the dimension of the substrate. The antimonide semiconductor layer will provide the finally prepared semiconductor-on-insulator structure with group III-V antimonide semiconductor material in a subsequent step, so that the size of the resulting semiconductor-on-insulator structure can be made without being limited by the smaller size of conventional group III-V antimonide wafers.
According to some embodiments of the present invention, the antimonide transition layer and the antimonide semiconductor layer may be formed independently of each other by epitaxial growth. This can further improve the quality of the formed antimonide transition layer and antimonide semiconductor layer. The epitaxy may be conventional metalorganic chemical vapor deposition (MOCVD), or Molecular Beam Epitaxy (MBE), among others. The quality and the thickness of the antimonide semiconductor layer can be well controlled by the epitaxial growth technology, the cost of the MOCVD epitaxial growth technology is low, required equipment is easy to obtain, and the production cost is favorably reduced.
According to an embodiment of the present invention, in order to further improve the quality of the interface between the substrate and the antimonide semiconductor layer, a substrate transition layer may be formed on the upper surface of the substrate in advance before the formation of the antimonide transition layer. According to an embodiment of the present invention, the substrate transition layer may include at least one of a germanium transition layer and an arsenide transition layer. That is, the base transition layer may contain at least one of Ge and arsenide. For example, the base transition layer may be a germanium transition layer or a GaAs transition layer, or the base transition layer may further include a germanium sublayer and a GaAs sublayer, wherein the germanium sublayer is disposed on an upper surface of the base and the GaAs sublayer is disposed on an upper surface of the germanium sublayer. According to an embodiment of the present invention, the thickness of the base transition layer may be 1 μm or more. Compared with silicon, the lattice constants of germanium, gallium arsenide and gallium antimonide are closer, and the germanium and the gallium arsenide serving as the transition layer can play a role in reducing the defect density in the transition layer. In addition, the substrate transition layer may also serve to hinder diffusion of substrate elements (e.g., Si) into the antimonide transition layer. Optimally, the interface quality of the transition layer and the silicon substrate is easier to control by taking germanium as the transition layer, and the crystal defect density in each transition layer and the antimonide semiconductor layer is reduced. In particular, the substrate transition layer may also be formed by epitaxial growth. For example, the base transition layer may be formed using low temperature epitaxial growth. The inventor finds through a large number of experiments that when Ge is used as the base transition layer, the misfit dislocation between the Si substrate and the Ge can be effectively controlled through low-temperature epitaxy at the temperature lower than 450 ℃, so that the quality of the formed base transition layer can be further improved, and the subsequent epitaxy quality of the antimonide semiconductor layer is further improved.
The specific thicknesses and epitaxial growth conditions of the base transition layer, the antimonide transition layer and the antimonide semiconductor layer formed in this step are not particularly limited according to embodiments of the present invention, and can be adjusted by those skilled in the art according to the specific requirements of the finally-formed semiconductor-on-insulator structure. The inventors have found through a lot of experiments that it is advantageous to control the threading dislocation on the surface of the base transition layer by properly increasing the thickness of the base transition layer, thereby forming a base transition layer with low threading dislocation density. According to an embodiment of the present invention, the thickness of the base transition layer may be 1 μm or more.
In order to further improve the quality of the first composite body formed in this step and improve the performance of the finally obtained semiconductor-on-insulator structure, according to an embodiment of the present invention, before forming the antimonide semiconductor layer, the method may further include:
an ion adsorption layer is formed on the upper surface of the antimonide transition layer in advance. That is, an ion-adsorbing layer is formed between the antimonide transition layer and the antimonide semiconductor layer. In particular, the ion-adsorbing layer may be formed of an antimonide material having strain. According to embodiments of the present invention, the ion-adsorbing layer may be formed of a group III-V antimonide semiconductor material as described above, the group III-V antimonide semiconductor material in the ion-adsorbing layer having a different lattice constant than the group III-V antimonide semiconductor material in the antimonide transition layer and the antimonide semiconductor layer. Specifically, the group III-V antimonide semiconductor material In the ion adsorption layer may be MSb, where M is at least one of Ga, In, and Al. That is, the ion adsorption layer may be formed of GaSb, InSB, or AlSb, or may be formed of a ternary antimonide or a quaternary antimonide composed of Ga, In, Al, and Sb. When MSb is a ternary or quaternary antimonide, the atomic ratio of the sum of a plurality of IIIA group elements in the ternary antimonide or quaternary antimonide to Sb element is 1: 1. For example, according to embodiments of the present invention, MSb may be GaSb, InSb, AlSb, InxGa1-xSb、AlyGa1-ySb、InzAl1-zSb and InmAlnGa1-m-nAt least one of Sb, wherein x, y, z, m and n are each independently greater than 0 and less than 1. Meanwhile, the material of the ion adsorption layer, the antimonide transition layer and the antimonide semiconductor layer isHave different lattice constants in order to introduce strain in the ion-adsorbing layer. For example, when the antimonide transition layer is formed of GaSb, the ion adsorption layer may be InxGa1-xSb, and the antimonide semiconductor layer may be formed of GaSb, AlGaSb or InpGa1-pSb formation (x ≠ p), that is, the ion-adsorbing layer and the antimonide transition layer and the antimonide semiconductor layer may be made of materials having different elemental compositions, or may be made of materials having the same elemental composition (but in which the elemental contents are different). The thickness of the ion adsorption layer may be 2 to 50 nm. According to further embodiments of the present invention, the ion adsorption layer may have a thickness of 10-30 nm. The inventors have intensively studied and found a large number of experiments that the ion adsorption layer formed of the above material has a strong adsorption and aggregation function for hydrogen ions. In the subsequent steps, the stripping treatment is realized by implanting hydrogen ions, so that the adsorption and aggregation capability of the implanted hydrogen ions can be improved by using the ion adsorption layer, the implantation dosage of the hydrogen ions required by the stripping treatment can be reduced, and the production cost can be reduced. In addition, the ion adsorption layer can effectively control the stripping position in the subsequent stripping treatment, and the semiconductor-on-insulator structure with the thickness of the ultrathin antimonide semiconductor layer is realized. In the conventional smart cut technology, the ion implantation dosage required for antimonide cut is large (about 5X 10 is required for hydrogen ion implantation dosage)16/cm2～3×1017/cm2) The implantation energy is high (when ions are implanted, large ion beam current and large implantation dosage are easily obtained under the high implantation energy; accordingly, in order to obtain a high implantation dose, high implantation energy is often required, resulting in a large implantation depth), the depth of ion implantation is often 100nm or more, and the thickness of the finally obtained antimonide semiconductor layer is more than 100 nm. After the ion adsorption layer is adopted, the ion implantation dosage required for stripping is reduced (the hydrogen ion implantation dosage can be reduced to 5 × 10)16/cm2It can even be reduced to 0.5 × 1016/cm2) The implantation energy can also be reduced, the implanted hydrogen ions are accumulated in the ion-adsorbing layer, the thickness and the final thickness of the antimonide semiconductor layer in the first composite bodyThe film thickness of the antimonide semiconductor material in the semiconductor-on-insulator structure obtained is uniform, so that the semiconductor-on-insulator structure with the thickness of the antimonide semiconductor layer smaller than 100nm can be easily obtained. When ion implantation is performed, normal temperature ion implantation or high temperature ion implantation may be adopted, i.e. the temperature of the first complex is 200-. When high temperature ion is implanted, hydrogen ions are easier to diffuse into the ion adsorption layer, the aggregation degree of the hydrogen ions in the ion adsorption layer is increased, the reduction of the ion implantation dosage is facilitated, and the cost is reduced.
According to the embodiment of the invention, in order to further improve the effect of the bonding treatment and improve the bonding quality, before the subsequent ion implantation treatment, the polishing treatment and/or the annealing treatment can be performed on the upper surface of the first composite body in advance. Thereby, it is advantageous to obtain a flat upper surface, so that the bonding quality can be improved. According to an embodiment of the present invention, the annealing process may be performed in an atmosphere containing hydrogen gas at 600-1000 ℃. The annealing temperature is related to the composition of the antimonide semiconductor material, with the highest temperature required for AlSb and the lowest temperature required for InSb. When annealing, the annealing temperature can not exceed the melting point of the antimonide semiconductor layer. High-temperature annealing (such as 600-1000 ℃) in hydrogen atmosphere can effectively promote surface atom migration of the antimonide semiconductor material, reduce the roughness of the surface of the antimonide semiconductor layer and improve the bonding quality. Preferably, the upper surface of the first composite is treated with a polishing process to obtain a flat surface. After polishing, the first composite surface needs to be cleaned to obtain a clean surface.
According to an embodiment of the present invention, referring to fig. 5, in order to improve the quality of the interface between the antimonide semiconductor layer and the insulating layer in the semiconductor-on-insulator structure, a first passivation layer 20 may be formed on the upper surface of the first composite 1000 in advance before a subsequent ion implantation process is performed. Since, in the subsequent steps, the antimonide semiconductor layer 300 in the first composite 1000 needs to be brought into contact with the insulating layer 600 by bonding to form the semiconductor-on-insulator structure 4000, but the antimonide semiconductor layer 400 is in contact with the oxide (insulating layer)Layer 600) is often of less than ideal interface quality. Accordingly, the first passivation layer 20 can be used to improve the quality of the interface between the antimonide semiconductor layer and the insulating layer, thereby improving the electrical performance of a device having a semiconductor-on-insulator structure. The material forming the first passivation layer may be selected according to actual circumstances, for example, according to an embodiment of the present invention, when the antimonide semiconductor layer is composed of GaSb, AlGaSb, InGaSb, etc., the first passivation layer 20 may be sulfide or Al2O3. The thickness of the first passivation layer may be 0.5-10 nm. Optimally, the first passivation layer is a sulfide with a thickness of 0.5-2 nm. The sulfide may be formed by surface sulfurization of antimonide, and the sulfurization may be performed by low-temperature annealing in sulfur-containing atmosphere or soaking in solution containing sulfur ions, while Al is used2O3As the first passivation layer, it may be formed by a method such as Atomic Layer Deposition (ALD).
S2: ion implantation process
According to an embodiment of the invention, in this step, the first complex is subjected to an ion implantation treatment, the implanted ions containing hydrogen ions. In this step, the specific method for performing ion implantation is not particularly limited, and a person skilled in the art can select a familiar method or technique to perform ion implantation according to the actual situation. When ion implantation is performed, normal temperature ion implantation or high temperature ion implantation may be adopted, i.e. the temperature of the first complex is 200-. According to the specific embodiment of the invention, the implanted ions can be H ions, H/He ion co-implantation or H/Ar co-implantation. The implantation dosage of the hydrogen ions can be reduced by co-implanting He or Ar ions and the hydrogen ions, and increasing the pressure of hydrogen bubbles formed by gathering the hydrogen ions by the He or Ar ions. According to an embodiment of the present invention, the implantation dose of the ion implantation process may be 0.5 × 1016/cm2～1×1017/cm2. The ions implanted in this step will accumulate in the antimonide semiconductor layer, so that the subsequent lift-off treatment step can be carried out to lift off in the antimonide semiconductor layer, thereby realizing the preparation of the semiconductor-on-insulator structure. As previously mentioned, when there is ion adsorption in the first complexDuring the layer attaching, due to the adsorption and aggregation of the ion adsorption layer on the H ions, the implantation dosage of the ion implantation treatment can be greatly reduced, and the subsequent stripping process is also carried out in the ion adsorption layer. According to the embodiment of the present invention, when the first composite has the ion-adsorbing layer, the implantation dose of the ion implantation process can be reduced to 5 × 1016/cm2Or below, and has an ion adsorption layer, and the implantation dosage of the ion implantation treatment can be reduced to 0.5 × 1016/cm2. The method provided by the invention can realize stripping treatment under the injection dosage, and is greatly reduced compared with the existing intelligent stripping technology, thereby being beneficial to reducing the production cost.
S3: forming a second composite
According to an embodiment of the present invention, in this step, the first complex subjected to the ion implantation process and the substrate are subjected to a bonding process so as to obtain a second complex. Specifically, the upper surface of the substrate has an insulating layer, and in the bonding process, the insulating layer is in contact with the antimonide semiconductor layer. According to a specific embodiment of the present invention, the substrate may be a silicon substrate, and the insulating layer may be silicon dioxide, hafnium oxide, aluminum oxide, or the like. The substrate and the insulating layer are the substrate and the insulating layer in the finally formed semiconductor-on-insulator structure, and therefore, it can be understood by those skilled in the art that during the bonding process, the previously formed first composite needs to be inverted so that the antimonide semiconductor layer on the upper surface of the first composite is bonded with the insulating layer of the substrate. The specific operation steps and bonding conditions of the bonding process are not particularly limited, and may be selected by those skilled in the art according to the actual circumstances.
S4: stripping treatment
According to an embodiment of the invention, in this step the second composite is subjected to a lift-off treatment in order to obtain a third composite and a semiconductor-on-insulator structure, respectively. Specifically, the stripping process may include a conventional anneal at a temperature of 200-600 degrees Celsius, or a microwave anneal at a temperature of less than 300 degrees Celsius (e.g., 200-300 degrees Celsius). The higher the temperature, the shorter the time required to implant ions to form bubbles. In the conventional annealing process, a lower annealing temperature (e.g., 200-400 degrees Celsius) may be used when He or Ar ions are co-implanted with hydrogen ions, and a higher annealing temperature (e.g., 400-600 degrees Celsius) may be used when only hydrogen ions are implanted. In the above-mentioned peeling treatment, the hydrogen-containing ions injected in advance will form a gas in the above-mentioned annealing process, thereby realizing peeling of the second composite. As described above, in the ion implantation process, the implanted ions are present in the antimonide semiconductor layer or the ion adsorption layer, and therefore, the exfoliation treatment is also performed in the antimonide semiconductor layer or the ion adsorption layer. Specifically, the above-described exfoliation treatment occurs in the antimonide semiconductor layer, near the interface between the antimonide semiconductor layer and the antimonide transition layer; alternatively, the above-mentioned peeling treatment is performed in the ion-adsorbing layer, near the interface between the ion-adsorbing layer and the antimonide semiconductor layer. This makes it possible to peel and divide the second composite into two parts. Referring to fig. 3, the peeled second composite 2000 is divided into: semiconductor-on-insulator structure 4000 (formed from substrate 500, insulating layer 600, and antimonide semiconductor layer 700 in the semiconductor-on-insulator structure), and third composite 3000 (formed from remaining antimonide semiconductor layer 800, antimonide transition layer 200, and base 100 in the third composite), according to some embodiments of the present invention, when lift-off occurs in close proximity to the interface between the antimonide semiconductor layer and the antimonide transition layer, the resulting third composite 3000 may be free of remaining antimonide semiconductor layer 800 (not shown). As will be understood by those skilled in the art, when the first composite contains a substrate transition layer and an ion adsorption layer, referring to fig. 4, a third composite 3000 formed after the lift-off process is composed of the substrate 100, the substrate transition layer 10, the antimonide transition layer 200 and the remaining ion adsorption layer 1B in the third composite, and the formed semiconductor-on-insulator structure 4000 has the remaining ion adsorption layer 1A on the surface; also, when the first composite body surface contains the first passivation layer 20, referring to fig. 5, the semiconductor-on-insulator structure 4000 formed after the lift-off is composed of the substrate 500, the insulating layer 600, the first passivation layer 20, the antimonide semiconductor layer 700 in the semiconductor-on-insulator structure, and the residual ion adsorption layer 1A of the surface.
According to an embodiment of the present invention, the thickness of the antimonide semiconductor layer 700 (formed by the exfoliation treatment of the antimonide semiconductor layer or the ion-adsorbing layer in the first composite) in the finally formed semiconductor-on-insulator structure 4000 is less than 100 nm. According to the embodiment of the present invention, when the ion-adsorbing layer is provided in the first composite, on the one hand, adsorption and aggregation of the implanted hydrogen ions can be achieved by the ion-adsorbing layer, and on the other hand, exfoliation can be achieved in the ion-adsorbing layer near the interface by utilizing the feature that the ion-adsorbing layer preferentially adsorbs H ions at the interface with the antimonide semiconductor layer of the first composite. Thus, the thickness of the antimonide semiconductor layer in the semiconductor-on-insulator structure formed after the exfoliation can be controlled by controlling the thickness of the antimonide semiconductor layer formed in the first composite. The thickness of the antimonide semiconductor layer in the first composite body can be controlled through epitaxial growth, so that when the antimonide semiconductor layer in the first composite body is thin, stripping can be still achieved at the interface of the antimonide semiconductor layer and the ion adsorption layer of the first composite body. In the conventional Smart-cut process, the depth of ion implantation is above 100nm at the minimum, so that the thickness of the antimonide semiconductor layer of the semiconductor-on-insulator structure obtained by the Smart-cut process is about 100nm at the minimum. In the present invention, a semiconductor-on-insulator structure with an antimonide semiconductor layer thickness of less than 50nm or even less than 30nm can be obtained. According to the embodiment of the invention, in order to further improve the performance of the obtained semiconductor-on-insulator structure, the ion adsorption layer remained on the surface of the semiconductor-on-insulator film can be removed.
According to an embodiment of the present invention, after the semiconductor-on-insulator structure is formed, a second passivation layer may be further formed on an upper surface of the antimonide semiconductor layer of the semiconductor-on-insulator structure. According to an embodiment of the present invention, the second passivation layer may be sulfide or Al2O3The thickness is 0.5-10 nm. The sulfide may be formed by sulfurizing the surface of antimonide, while Al is used2O3As the second passivation layer, it may be formed by Atomic Layer Deposition (ALD) or the like. The second passivation layer and the first passivation layer may be made of the same material or different materials. Optimally, the second passivation layer is a sulfide thin film with the thickness of 0.5-2 nm. And the interface performance between the sulfide and the oxide insulating layer is obviously superior to that between GaSb, InSb or AlSb and the oxide insulating layer. Thereby, the performance of the semiconductor-on-insulator structure can be further improved. According to the embodiment of the present invention, when the first composite has the ion adsorption layer therein, the surface of the semiconductor-on-insulator structure formed also has the residual ion adsorption layer. The remaining ion-adsorbing layer may or may not be removed before the second passivation layer is formed. The resulting semiconductor-on-insulator structure is shown in fig. 6 or fig. 7.
According to an embodiment of the present invention, the method may further include performing a polishing treatment and/or an annealing treatment on the surface of the obtained semiconductor-on-insulator thin film. That is, the semiconductor-on-insulator structure may be subjected to at least one of a polishing process and an annealing process. Namely: the semiconductor-on-insulator structure is subjected to polishing treatment and annealing treatment in sequence, or the semiconductor-on-insulator structure is subjected to separate polishing treatment or annealing treatment. Thereby, the surface flatness of the obtained semiconductor-on-insulator structure can be further improved. According to the embodiment of the invention, the annealing treatment can be performed in a hydrogen-containing atmosphere at 600-1000 ℃, and the high-temperature annealing in the hydrogen atmosphere can effectively promote the atom migration on the surface of the antimonide semiconductor layer, reduce the roughness of the surface of the antimonide semiconductor layer and further improve the surface flatness of the semiconductor-on-insulator structure. It can be understood by those skilled in the art that the polishing treatment and/or the annealing treatment can improve the surface flatness of the semiconductor-on-insulator structure and remove the ion adsorption layer remaining on the surface. Therefore, according to an embodiment of the present invention, the above-described polishing treatment and/or annealing treatment may be performed before forming the second passivation layer 30, so as to form the semiconductor-on-insulator structure as shown in fig. 7.
According to an embodiment of the invention, referring to fig. 2, the method further comprises:
recycling of the third Complex
According to embodiments of the present invention, a third composite may also be obtained by removing the semiconductor-on-insulator structure after the lift-off process. Returning the third composite to the ion implantation process in step S2 allows the remaining antimonide semiconductor layer in the third composite to be reused, thereby avoiding the need to prepare the first composite once for each semiconductor-on-insulator structure produced. As described above, when there is no ion-adsorbing layer in the first composite, the exfoliation treatment is performed in the antimonide semiconductor layer. Thus, a part of the antimonide semiconductor layer remains on the surface of the third composite formed after the separation. In this case, the third composite may be used as the first composite by directly returning to the step of ion implantation treatment, or may be used as the first composite by continuing epitaxy on the surface of the antimonide semiconductor layer to thicken the antimonide semiconductor layer and returning to the step of ion implantation treatment; when the first composite contains an ion-adsorbing layer, the upper surface of the third composite formed after the separation is the ion-adsorbing layer, and in this case, the antimonide semiconductor layer can be formed again directly on the upper surface of the ion-adsorbing layer, and then the semiconductor layer is returned to the ion implantation treatment step and used as the first composite. Therefore, the third complex can be repeatedly utilized, on one hand, the production cost can be saved, on the other hand, only one substrate is needed to carry out primary layer growth, and a plurality of semiconductor-on-insulator structures can be obtained, so that the production efficiency can be improved, and the production time can be shortened.
According to an embodiment of the present invention, before returning the third complex to the ion implantation process, the following processes may be performed on the third complex in advance to improve the efficiency and effect of the subsequent processes:
and polishing and/or annealing the upper surface of the third composite body. According to the embodiment of the invention, the annealing treatment can be performed in a hydrogen-containing atmosphere at 600-1000 ℃, and the high-temperature annealing in the hydrogen atmosphere can effectively promote the surface atom migration and reduce the roughness of the surface of the antimonide semiconductor layer. The processing is beneficial to obtaining a relatively flat surface, so that the bonding quality of subsequent bonding processing can be improved.
Specifically, referring to fig. 3, the above method may first form an antimonide semiconductor layer 200 on the upper surface of the substrate 100 as a first composite 1000 by techniques including, but not limited to, epitaxial growth. Performing ion implantation treatment on the first complex 1000; subsequently, a substrate 500 (which may be SiO on the top surface) having an insulating layer 600 on the top surface is provided2The Si substrate of (1) and then bonding the substrate 500 and the first composite 1000 so that the insulating layer 600 is in contact with the antimonide semiconductor layer 300 to form a second composite 2000; in the subsequent lift-off process, the second composite 2000 is lifted off along the lift-off boundary shown in the figure, and a semiconductor-on-insulator structure 4000 (including the substrate 500, the insulating layer 600, and the antimonide semiconductor layer 700 in the semiconductor-on-insulator structure formed by lift-off) and a third composite 3000 are formed. The third composite 3000 includes the substrate 100, the antimonide transition layer 200, and the remaining antimonide semiconductor layer 800 in the third composite. The third complex 3000 is returned to the ion implantation step and processed, and the third complex can be reused. It will be appreciated by those skilled in the art that when the remaining antimonide semiconductor layer 800 of the third composite 3000 is insufficient, the antimonide semiconductor layer (not shown) may need to be formed again on the surface of the third composite 3000 before ion implantation is performed.
According to other embodiments of the present invention, referring to fig. 4, the above method may also first form a first composite 1000 comprising the substrate transition layer 10 and the ion-adsorbing layer 400. Performing ion implantation treatment on the first complex 1000; subsequently, a substrate 500 having an insulating layer 600 on the upper surface is provided, and then the substrate 500 and the first composite 1000 are bonded so that the insulating layer 600 is in contact with the antimonide semiconductor layer 300 to form a second composite 2000; in the subsequent stripping process, the second composite 2000 is stripped along the realized stripping boundary (in the ion-adsorbing layer 300) shown in the figure, forming a semiconductor-on-insulator structure 4000 (including the substrate 500, the insulating layer 600, the antimonide semiconductor layer 700 in the semiconductor-on-insulator structure formed by stripping, and the residual ion-adsorbing layer 1A), and a third composite 3000. The third composite 3000 includes a substrate 100, a substrate transition layer 10, and a residual ion adsorption layer 1B. After the antimonide semiconductor layer is newly formed on the surface of the third composite 3000, the third composite 3000 may be returned to the ion implantation step for processing, thereby realizing recycling of the third composite.
In summary, the method has at least one of the following advantages:
(1) the operation steps are simple, and the requirements on instruments and equipment are low;
(2) the stripping can be realized under a smaller ion implantation dosage, which is beneficial to reducing the production cost of the semiconductor structure on the insulator;
(3) the limitation on the size of the semiconductor-on-insulator structure caused by the preparation of the antimonide semiconductor material wafer can be avoided, and the large-size semiconductor-on-insulator structure is obtained;
(4) the preparation of the semiconductor-on-insulator structure for preparing the antimonide semiconductor layer with the thickness of 50nm or less can be realized by introducing the ion adsorption layer;
(5) the substrate and other structures are recycled, the production cost is reduced, and the preparation period is shortened.
In another aspect of the invention, the invention is directed to a semiconductor-on-insulator structure. According to an embodiment of the present invention, the semiconductor-on-insulator structure is formed by the method described above. The semiconductor-on-insulator structure thus has all the features and advantages of the semiconductor-on-insulator structure obtained by the method described above, which will not be described in detail herein.
According to an embodiment of the present invention, the diameter of the antimonide semiconductor layer in the semiconductor-on-insulator structure is not less than 6 inches. Since the semiconductor-on-insulator structure is formed by the method described above, the size of the antimonide semiconductor layer in the semiconductor-on-insulator structure can be unlimited by the size of the wafer of antimonide semiconductor material, and a semiconductor-on-insulator structure with a size of 8-12 inches or more can be formed.
The semiconductor-on-insulator structure proposed by the present invention can be used for the fabrication of semiconductor devices such as a metal-oxide-semiconductor field effect transistor. Therefore, the metal-oxide-semiconductor field effect transistor has at least one of the advantages of excellent performance, simple and convenient preparation and the like.
The present invention is illustrated below by way of specific examples, which are intended to be illustrative only and not to limit the scope of the present invention in any way, and unless otherwise specified, conditions or steps not specifically recited are generally conventional and reagents and materials used therein may be commercially available. Among them, the antimonide epitaxial growth apparatus used a metallorganic chemical vapor deposition system of the AIX 2800G4-TM type manufactured by Aixtron corporation.
Example one
(1) By utilizing a metal organic chemical vapor deposition technology, trimethyl gallium (TMG), trimethyl indium and trimethyl antimony are used as gas sources, an 8-inch silicon polished wafer is used as a substrate, a GaSb antimonide transition layer is formed by epitaxy, the substrate temperature during epitaxy is 640 ℃, and the GaSb antimonide transition layer with the thickness of about 3 microns is formed. Then, in the same equipment, the temperature is reduced to 600 ℃, and a GaSb antimonide semiconductor layer with the thickness of about 200nm is formed. And polishing and cleaning the surface of the wafer to improve the flatness of the gallium antimonide surface and facilitate subsequent bonding. Thus, a first complex is obtained.
(2) Hydrogen ion implantation is carried out on the first complex body, and the implantation dosage is 1 multiplied by 1017/cm2The implantation depth was 120 nm.
(3) Another 8-inch silicon polished wafer is used as a substrate, and SiO with the thickness of 10nm is formed on the surface of the substrate through thermal oxidation at 1000 DEG C2An insulating layer. Bonding the first composite with a substrate to obtain a second composite (comprising a substrate/GaSb antimonide transition layer/GaSb antimonide semiconductor layer/SiO)2Insulating layer/Si substrate). Wherein, SiO2The insulating layer is in contact with the GaSb antimonide semiconductor layer.
(4) Annealing at 500 deg.C under nitrogen atmosphere 1In the hour, smart cut was achieved at the site of hydrogen ion implantation, resulting in a third composite (comprising Si substrate/GaSb antimonide transition layer/remaining GaSb antimonide semiconductor layer) and semiconductor-on-insulator structure (comprising Si substrate/SiO substrate)2Insulating layer/GaSb antimonide semiconductor layer). And polishing and cleaning the obtained semiconductor structure on the insulator, and improving the surface flatness of the GaSb antimonide semiconductor layer.
Example two
(1) GeH by using reduced pressure chemical vapor deposition technology4As a gas source, an 8-inch silicon polished wafer is used as a substrate, a substrate transition layer formed by Ge is formed by epitaxy, the substrate temperature in epitaxy is 400 ℃ for 30 minutes, a Ge epitaxial seed layer with the thickness of about 30nm is formed, the threading dislocation density is controlled, and then the temperature is raised to 750 ℃, and the substrate transition layer (the transition layer contains the Ge epitaxial seed layer) with the thickness of about 1.5 microns is formed.
(2) By utilizing a metal organic chemical vapor deposition technology, trimethyl gallium (TMG), trimethyl indium and trimethyl antimony are used as gas sources, a GaSb antimonide transition layer is formed on the surface of a substrate transition layer in an epitaxial mode, the substrate temperature is 640 ℃ in the epitaxial mode, and the GaSb antimonide transition layer with the thickness of about 1.5 microns is formed. And polishing and cleaning the surface of the wafer to improve the flatness of the gallium antimonide surface and facilitate subsequent bonding. And continuously utilizing the metal organic chemical vapor deposition technology, raising the temperature to 600 ℃, and forming an InGaSb ion adsorption layer with the thickness of about 20 nm. And then in the same equipment, the temperature is raised to 650 ℃, and a GaSb antimonide semiconductor layer with the thickness of about 50nm is formed. Thus, a first complex is obtained.
(3) Hydrogen ion implantation is carried out on the first complex body, and the implantation dosage is 4 multiplied by 1016/cm2The implantation depth was 70 nm.
(4) Another 8-inch silicon polished wafer is used as a substrate, and SiO with the thickness of 10nm is formed on the surface of the substrate through thermal oxidation at 1000 DEG C2An insulating layer. Bonding the first composite with a substrate to obtain a second composite (comprising a substrate/a substrate transition layer/a GaSb antimonide transition layer/an InGaSb ion adsorption layer/a GaSb antimonide semiconductor layer/SiO)2Insulating layer/Si substrate). Wherein, SiO2The insulating layer is connected with the GaSb antimonide semiconductor layerAnd (4) contacting.
(5) Annealing at 500 ℃ in nitrogen atmosphere for 1 hour to realize intelligent stripping in the InGaSb ion adsorption layer to obtain a third composite body (comprising a Si substrate/a substrate transition layer/a GaSb antimonide transition layer/a part of the InGaSb ion adsorption layer) and a semiconductor-on-insulator structure (comprising a Si substrate/a SiO substrate)2Insulating layer/GaSb antimonide semiconductor layer/residual InGaSb ion-adsorbing layer). And polishing and cleaning the obtained semiconductor-on-insulator structure to remove the residual ion adsorption layer and improve the surface flatness of the GaSb antimonide semiconductor layer.
EXAMPLE III
The steps (1) and (2) are the same as in the second embodiment.
(3) And carrying out vulcanization treatment on the first complex in a sulfuration ammonia water solution at room temperature to form sulfide with the thickness of about 2nm as a first passivation layer. This results in a first composite with a first passivation layer.
(4) Hydrogen ion implantation is carried out on the first complex body, and the implantation dosage is 4 multiplied by 1016/cm2The implantation depth was 70 nm.
(5) Another 8-inch silicon polished wafer is used as a substrate, and SiO with the thickness of 10nm is formed on the surface of the substrate through thermal oxidation at 1000 DEG C2An insulating layer. Bonding the first complex with a substrate to obtain a second complex (comprising a substrate/a substrate transition layer/a GaSb antimonide transition layer/an InGaSb ion adsorption layer/a GaSb antimonide semiconductor layer/a first passivation layer/SiO)2Insulating layer/Si substrate). Wherein, SiO2The insulating layer is in contact with the first passivation layer.
(6) Microwave annealing at 300 deg.C for 1 hr to realize intelligent stripping in the InGaSb ion adsorption layer to obtain a third composite body (comprising Si substrate/substrate transition layer/GaSb antimonide transition layer/partial InGaSb ion adsorption layer) and semiconductor-on-insulator structure (comprising Si substrate/SiO substrate)2Insulating layer/first passivation layer/GaSb antimonide semiconductor layer/residual InGaSb ion adsorption layer). And polishing and cleaning the obtained semiconductor-on-insulator structure to improve the surface flatness of the obtained semiconductor-on-insulator structure.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, in the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (23)
1. A method of fabricating a semiconductor-on-insulator structure, the method comprising:
(1) sequentially forming an antimonide transition layer and an antimonide semiconductor layer on the upper surface of a substrate, and forming an ion adsorption layer on the upper surface of the antimonide transition layer in advance before forming the antimonide semiconductor layer so as to obtain a first complex;
(2) subjecting the first complex to an ion implantation treatment, the implanted ions containing hydrogen ions, the implanted ions being present in the ion-adsorbing layer;
(3) carrying out bonding treatment on the first composite and a substrate so as to obtain a second composite, wherein the upper surface of the substrate is provided with an insulating layer, and the insulating layer is in contact with the antimonide semiconductor layer in the bonding treatment; and
(4) subjecting the second composite to a stripping treatment in the ion-adsorbing layer so as to obtain a third composite and the semiconductor-on-insulator structure, respectively,
wherein the ion adsorption layer does not have a superlattice structure therein, and the ion adsorption layer has a different lattice constant from the antimonide transition layer and the antimonide semiconductor layer.
2. The method of claim 1, wherein the antimonide transition layer and the antimonide semiconductor layer are each independently formed of a group III-V antimonide semiconductor material.
3. The method of claim 2, wherein the III-V antimonide semiconductor material is MSb, and wherein M is at least one of Ga, In, and Al.
4. The method of claim 2, wherein the group III-V antimonide semiconductor material is GaSb, InSb, AlSb, InxGa1-xSb、AlyGa1-ySb、InzAl1-zSb and InmAlnGa1-m-nAt least one of the components Sb is a metal,
wherein x, y, z, m and n are each independently greater than 0 and less than 1.
5. The method of claim 1, wherein the antimonide semiconductor layer and the antimonide transition layer are each independently formed by epitaxial growth.
6. The method according to claim 1, wherein in the step (1), a substrate transition layer is formed on an upper surface of the substrate in advance before the formation of the antimonide transition layer.
7. The method of claim 6, wherein the thickness of the substrate transition layer is not less than 1 micron.
8. The method of claim 1, wherein the ion-adsorbing layer comprises the group III-V antimonide semiconductor material of any one of claims 2-4, and wherein the group III-V antimonide semiconductor material in the ion-adsorbing layer has a different lattice constant than the group III-V antimonide semiconductor material in the antimonide transition layer and the antimonide semiconductor layer.
9. The method of claim 8, wherein the ion-adsorbing layer has a thickness of 2-50 nm.
10. The method of claim 1, wherein the substrate and the base are each independently formed of silicon.
11. The method of claim 1, further comprising: in the step (1), a first passivation layer is formed on the upper surface of the antimonide semiconductor layer.
12. The method of claim 11, further comprising: in step (1), a second passivation layer is formed on the upper surface of the semiconductor-on-insulator structure.
13. The method of claim 1, wherein the ion implantation process has an implant dose of: 0.5X 1016/cm2～1×1017/cm2。
14. The method as claimed in claim 1, wherein the temperature of the first complex is 200-600 ℃ during the ion implantation process.
15. The method of claim 1, wherein the thickness of the antimonide semiconductor layer in the semiconductor-on-insulator structure is less than 100 nm.
16. The method according to claim 1, wherein after step (1) and before step (2), the upper surface of the first composite body is subjected to a polishing treatment and/or an annealing treatment in advance.
17. The method of claim 16, wherein the annealing is performed in a hydrogen-containing atmosphere at 600-1000 ℃.
18. The method as claimed in claim 1, wherein the stripping process comprises an anneal at a temperature of 200-600 ℃.
19. The method of claim 1, further comprising: after the step (4), performing polishing treatment and/or annealing treatment on the surface of the semiconductor-on-insulator structure.
20. The method of claim 1, further comprising:
and (3) recycling the third complex, and returning the third complex to the step (2) for ion implantation treatment.
21. The method according to claim 20, wherein the following is performed on the third complex in advance before returning the third complex to step (2):
polishing and/or annealing the upper surface of the third composite body; and
and forming the antimonide semiconductor layer on the upper surface of the third composite.
22. A semiconductor-on-insulator structure formed by the method of any one of claims 1 to 21.
23. The semiconductor-on-insulator structure of claim 22, wherein the diameter of the antimonide semiconductor layer in the semiconductor-on-insulator structure is no less than 6 inches.
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