CN106611740B - Substrate and method for manufacturing the same - Google Patents
Substrate and method for manufacturing the same Download PDFInfo
- Publication number
- CN106611740B CN106611740B CN201510708606.5A CN201510708606A CN106611740B CN 106611740 B CN106611740 B CN 106611740B CN 201510708606 A CN201510708606 A CN 201510708606A CN 106611740 B CN106611740 B CN 106611740B
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- epitaxial layer
- bonding
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 233
- 238000000034 method Methods 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 230000008569 process Effects 0.000 claims abstract description 54
- 238000002161 passivation Methods 0.000 claims abstract description 50
- 239000000126 substance Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- 229910052732 germanium Inorganic materials 0.000 claims description 22
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 22
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical group O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 21
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 18
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 16
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 7
- IWTIUUVUEKAHRM-UHFFFAOYSA-N germanium tin Chemical compound [Ge].[Sn] IWTIUUVUEKAHRM-UHFFFAOYSA-N 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 33
- 239000010408 film Substances 0.000 description 33
- 239000000377 silicon dioxide Substances 0.000 description 16
- 235000012239 silicon dioxide Nutrition 0.000 description 16
- 230000000694 effects Effects 0.000 description 8
- 238000000407 epitaxy Methods 0.000 description 8
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 description 6
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910052594 sapphire Inorganic materials 0.000 description 6
- 239000010980 sapphire Substances 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- -1 oxygen ion Chemical class 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- XDXSUJKMVSURTH-UHFFFAOYSA-N [O--].[O--].[O--].[O--].[O--].[Sc+3].[Ta+5].[Pb++] Chemical compound [O--].[O--].[O--].[O--].[O--].[Sc+3].[Ta+5].[Pb++] XDXSUJKMVSURTH-UHFFFAOYSA-N 0.000 description 2
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- KJXBRHIPHIVJCS-UHFFFAOYSA-N oxo(oxoalumanyloxy)lanthanum Chemical compound O=[Al]O[La]=O KJXBRHIPHIVJCS-UHFFFAOYSA-N 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 2
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- NTWSIWWJPQHFTO-AATRIKPKSA-N (2E)-3-methylhex-2-enoic acid Chemical compound CCC\C(C)=C\C(O)=O NTWSIWWJPQHFTO-AATRIKPKSA-N 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000012459 cleaning agent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 238000001657 homoepitaxy Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a substrate and a manufacturing method thereof, comprising the following steps: providing an auxiliary substrate and a supporting substrate, wherein the auxiliary substrate at least comprises an epitaxial layer and a passivation layer above the epitaxial layer, and the supporting substrate at least comprises a buried dielectric layer; bonding the auxiliary substrate to the support substrate; removing the auxiliary substrate; chemical mechanical planarization CMP is performed until the epitaxial layer reaches a specified thickness. Because the passivation layer can effectively reduce the damage of the epitaxial layer in the bonding process, a large number of defects are avoided in the epitaxial layer, and the performance and reliability of the device manufactured by using the epitaxial layer are improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a substrate and a manufacturing method thereof.
Background
With the continuous development of the integrated circuit industry, how to reduce the substrate leakage current becomes the key point of research. Among them, by using a silicon-on-insulator (SOI) substrate so that the formed semiconductor device is located on the insulator, avoiding leakage current between the semiconductor device and the substrate is a well-known approach.
Furthermore, as semiconductor devices are being scaled down, there is a need to improve device performance by enhancing channel carrier mobility, for example, by replacing silicon with a semiconductor material having high carrier mobility such as silicon germanium, or the like. There has been proposed a structure for manufacturing a semiconductor device on a Germanium On Insulator (GOI) substrate, which is significantly superior to a structure for manufacturing a semiconductor device on an SOI substrate in terms of operation speed and the like.
In the prior art, an oxygen ion buried layer is formed in a semiconductor substrate through ion implantation, and then an oxide buried layer is formed in a semiconductor through an annealing mode; or forming an oxide buried layer in the semiconductor by implanting oxygen ions in combination with a lift-off process or the like; however, these methods are prone to damage and introduce defects into the material of the top layer during the manufacturing process, and on the other hand, they are expensive and inefficient due to the complex process, and are not suitable for large-scale germanium-on-insulator production. In addition, there is also a method of forming an oxide buried layer in a semiconductor substrate by a bonding process, generally including: forming a semiconductor epitaxial layer on one silicon substrate, then forming an oxide insulating layer on the other silicon substrate, then bonding the upper surfaces of the two substrates, and then forming an oxide buried layer in the semiconductor substrate and the epitaxial layer thereon by polishing or chemical etching. However, in the process of forming the buried oxide layer by the method, the epitaxial layer at the bonding contact surface is subjected to a long high-temperature and high-pressure process, so that a large number of defects are generated, and the defects affect the performance and reliability of the germanium layer.
Disclosure of Invention
The invention provides a substrate and a manufacturing method thereof, which aim to solve the problem that a high-quality oxide buried layer and an upper semiconductor layer thereof are difficult to form on a semiconductor substrate at low cost in the prior art.
The invention provides a substrate manufacturing method, which comprises the following steps:
providing an auxiliary substrate and a supporting substrate, wherein the auxiliary substrate at least comprises an epitaxial layer and a passivation layer above the epitaxial layer, and the supporting substrate at least comprises a buried dielectric layer;
bonding the auxiliary substrate to the support substrate;
removing the auxiliary substrate;
chemical mechanical planarization CMP is performed until the epitaxial layer reaches a specified thickness.
Preferably, the epitaxial layer comprises a buffer layer and a useful layer.
Preferably, the epitaxial layer comprises: germanium layer, silicon germanium layer, germanium tin layer, III-V compound semiconductor layer, silicon layer and their lamination.
Preferably, the passivation layer is a high-k dielectric layer, and includes any one or more of the following: aluminum oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium titanium oxide, strontium titanium oxide, yttrium oxide, scandium lead tantalum oxide, and laminates thereof.
Preferably, the high-k dielectric layer is an aluminum oxide film with the thickness of 5-10 nm.
Preferably, the auxiliary substrate is a silicon substrate, and the removing the auxiliary substrate includes:
carrying out mechanical grinding on the back surface of the auxiliary substrate until the thickness of the auxiliary substrate is less than 50 μm;
and etching by using diluted TMAH solution to remove the residual auxiliary substrate.
Preferably, the bonding process of the auxiliary substrate to the support substrate includes:
maximum temperature range of the chamber: 200 ℃ and 550 ℃;
bonding maximum pressure range: 1-60 KN;
bonding time range: 0.5-4 hours;
bonding chamber vacuum range: 1X 10-5mbar to 1 atm.
Preferably, the bonding process is:
maximum temperature of the chamber: 500 ℃;
bonding maximum pressure range: 10-30 KN;
bonding time: 2 hours;
degree of vacuum of bonding chamber: 5X 10-4mbar to 1 x 10-5mbar。
A substrate, comprising:
a support substrate;
a buried dielectric layer over the support substrate;
a passivation layer over the buried dielectric layer;
an epitaxial layer of a specified thickness over the passivation layer.
Preferably, the passivation layer is an aluminum oxide film with the thickness of 5-10 nm.
A semiconductor device, comprising: the device structure comprises a substrate and a device structure positioned at the epitaxial layer.
The invention provides a substrate and a manufacturing method thereof, wherein the provided auxiliary substrate at least comprises an epitaxial layer and a passivation layer on the epitaxial layer, and the passivation layer can effectively protect the epitaxial layer; then bonding the auxiliary substrate to the supporting substrate, wherein the buried dielectric layer on the supporting substrate can block leakage current between the epitaxial layer and the supporting substrate; the auxiliary substrate and the excess epitaxial layer are then removed. Because the passivation layer can effectively reduce the damage of the epitaxial layer in the bonding process, a large number of defects are avoided in the epitaxial layer, and the performance and reliability of the device manufactured by using the epitaxial layer are improved.
Furthermore, the passivation layer is made of a high-k dielectric material, the current blocking effect of the high-k dielectric material is obviously superior to that of an oxide layer adopted in a traditional SOI substrate such as silicon dioxide, and the leakage current phenomenon of the substrate can be effectively avoided.
Furthermore, the passivation layer is an aluminum oxide film with the thickness of 5-10nm, the aluminum oxide is a high-heat-conduction material compared with silicon dioxide, the performance and reliability of the device are directly influenced by the heat dissipation performance in a semiconductor integrated circuit, and the silicon dioxide film is adopted as an oxide buried layer in the traditional SOI substrate, so that the heat conduction performance is poor, and the heat dissipation of the device is not facilitated; the invention adopts the aluminum oxide film with the thickness of 5-10nm, which not only can reduce the damage of the epitaxial layer in the bonding process, but also can enhance the current blocking effect, so as to reduce the thickness of the oxide buried layer formed in the semiconductor substrate by the existing bonding process, facilitate the heat dissipation of the device and improve the performance and the reliability of the device.
Furthermore, the epitaxial layer may be a semiconductor material with higher carrier mobility than a silicon material, such as an epitaxial layer formed of germanium, silicon germanium, and the like, so as to enhance channel carrier mobility of a device manufactured by using the substrate, thereby improving device performance.
Furthermore, the invention provides bonding process parameters to prepare an oxide buried layer with high quality on a semiconductor substrate and an epitaxial layer on the oxide buried layer.
Drawings
In order to more clearly illustrate the embodiments of the present application or technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings can be obtained by those skilled in the art according to the drawings.
FIGS. 1A to 1D are schematic cross-sectional views of a semiconductor-on-insulator SeOI substrate fabrication process based on a bonding process in the prior art;
FIG. 2 is a flow chart of a method of fabricating a substrate according to an embodiment of the present invention;
FIGS. 3A to 3G are schematic cross-sectional views illustrating a substrate manufacturing process according to a first embodiment of the present invention;
FIGS. 4A to 4G are schematic cross-sectional views illustrating a second embodiment of a substrate manufacturing process according to the present invention;
FIGS. 5A to 5F are schematic cross-sectional views illustrating a third embodiment of a substrate manufacturing process according to the present invention;
fig. 6 is a schematic cross-sectional structure diagram of a semiconductor device manufactured by using the substrate provided by the embodiment of the invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
Since a buried oxide layer is formed in a substrate, the buried oxide layer can effectively prevent a leakage current between a device and the substrate, and improve latch-up and other problems. The fabrication of existing SeOI substrates generally employs three methods: 1. the method of forming an oxygen ion buried layer in a semiconductor substrate by ion implantation and then forming an oxide buried layer in a semiconductor by annealing is the most commonly used method at present, but because the oxide buried layer is formed by ion implantation, parameters such as depth and thickness of the buried layer are not easy to control; 2. the method of forming an oxide buried layer in a semiconductor by implanting oxygen ions in combination with a lift-off process or the like also has the above-described problems, and the ion implantation process is costly; forming a buried oxide layer in a semiconductor substrate by a bonding process, the method placing a pre-formed oxide layer in the substrate by the bonding process, typically comprising the steps of: first, an epitaxial layer of a specified kind of material is formed on one substrate as shown in fig. 1A, and an oxide film serving as an oxide buried layer is formed on the other substrate as shown in fig. 1B; then, bonding the upper surfaces of the two substrates as shown in fig. 1C; finally, the substrate with the epitaxial layer is removed by polishing or chemical etching to expose the epitaxial layer, as shown in fig. 1D. In particular, when the epitaxial layer is a germanium epitaxial layer, moisture is easily absorbed in air due to the epitaxially grown germanium layer. In addition, during the bonding process, the epitaxial layer at the bonding contact surface can be subjected to a long high-temperature and high-pressure process, so that a large number of defects are generated, and the defects can influence the performance and reliability of the germanium layer.
According to the substrate and the manufacturing method thereof provided by the invention, after the epitaxial layer is formed on the auxiliary substrate, the passivation layer is formed on the epitaxial layer so as to reduce the influence of the bonding process on the epitaxial layer. When the epitaxial layer is a high-k dielectric layer, the surface of germanium can be passivated, the leakage current blocking effect is enhanced, and the performance and reliability of the device are improved.
In order to better understand the technical solution and effect of the present invention, the following detailed description will be made with reference to a flowchart and a specific embodiment, the flowchart is shown in fig. 2, and the process of manufacturing a substrate is shown with reference to fig. 3A to 5F.
In the embodiment of the present invention, the selective etching ratio of the material of the auxiliary substrate 100 to the material of the epitaxial layer should be greater than or equal to 5:1, so as to ensure that the influence on the epitaxial layer 101 is reduced in the subsequent process of removing the auxiliary substrate 100. The auxiliary substrate 100 may be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, GaP, SiC, or the like, and may also be a stacked structure, such as Si/SiGe or the like. Since the epitaxial layer 101 needs to be formed on the auxiliary substrate 100, the closer the lattice constant of the epitaxial layer material is to the lattice constant of the auxiliary substrate 100, the better the quality of the epitaxial layer 101 is, which is helpful for improving the reliability of the device. Preferably, the substrate is a semiconductor substrate with a relatively low price and a lattice constant close to that of the target epitaxial layer material, such as a silicon substrate, as shown in fig. 3A.
The support substrate 200 should have high thermal stability and chemical stability, and in addition, should have high mechanical strength so as to facilitate the subsequent bonding and other process steps; preferably, the support substrate 200 should also have a high thermal conductivity to facilitate heat dissipation during operation of the device. Specifically, the auxiliary substrate 100 may be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, and may also be a stacked structure, such as Si/SiGe or the like; the auxiliary substrate 100 may be an oxide crystal substrate such as a sapphire substrate, which is not described herein.
The epitaxial layer 101 includes, but is not limited to: germanium layer, silicon germanium layer, germanium tin layer, III-V compound semiconductor layer, silicon layer and their lamination. The epitaxial process of the epitaxial layer 101 may be heteroepitaxy, for example, epitaxial growth of germanium, silicon germanium, iii-v compound semiconductor, etc. on a silicon substrate; it may of course be homoepitaxy, e.g. silicon on a silicon substrate, gallium arsenic on a gallium arsenic substrate, etc. In addition, the epitaxy can also be subjected to different epitaxy processes at different time intervals, for example, the epitaxy can comprise two parts, namely a buffer layer 1011 epitaxy part and a useful layer 1012 epitaxy part, and the buffer layer 1011 part can effectively reduce the number of epitaxy defects at a contact surface and improve the quality of the epitaxial layer 101; for another example, the epitaxial layer 101 may be a stack of multiple epitaxial layers 101: silicon/silicon germanium/germanium stacks, gallium arsenic/aluminum arsenic/gallium arsenic stacks, and the like. Preferably, the carrier mobility of the epitaxial layer material is greater than that of silicon, for example, the epitaxial layer 101 made of germanium, silicon germanium, gallium arsenic, or other materials enhances the channel carrier mobility of the device manufactured by using the substrate, so as to improve the device performance.
The passivation layer 102 may be undoped silicon oxide (SiO) deposited using CVD, PVD, or the like2) Doped silicon oxide (e.g., borosilicate glass, borophosphosilicate glass, etc.) and silicon nitride (Si)3N4) The dielectric material may be an oxide film formed by a thermal oxidation method, and further, in order to improve the insulating effect of the buried oxide layer, the passivation layer 102 may also be a high-k dielectric layer, and may include any one or more of the following: aluminum oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium titanium oxide, strontium titanium oxide, yttrium oxide, scandium lead tantalum oxide, and laminates thereof.
The buried dielectric layer 201 may be a silicon dioxide film commonly used in a conventional SOI substrate, or may also be a silicon oxynitride film, a silicon nitride film, or other commonly used dielectric films.
Example one
In this embodiment, the auxiliary substrate 100 and the supporting substrate 200 are bulk silicon substrates, the epitaxial layer 101 is a germanium layer, the passivation layer 102 is a hafnium oxide film, and the buried dielectric layer 201 is a silicon dioxide film, as shown in fig. 3G, the method includes:
step S01, providing an auxiliary substrate 100 and a supporting substrate 200, where the auxiliary substrate 100 at least includes an epitaxial layer 101 and a passivation layer 102 on the epitaxial layer 101, and the supporting substrate 200 at least includes a buried dielectric layer 201, as shown in fig. 3A to 3C.
In this embodiment, the auxiliary substrate 100 and the supporting substrate 200 are bulk silicon substrates, and the epitaxial layer 101 is a germanium layer with high carrier mobility to fabricate a high-speed device; the passivation layer 102 is a hafnium oxide high-k dielectric film; the buried dielectric layer 201 is a silicon dioxide film.
In one embodiment, two bulk silicon substrates of the same specification are provided, one of which serves as the auxiliary substrate 100 and the other serves as the support substrate 200. A germanium layer of 1 to 3 μm thickness is formed on the auxiliary substrate 100 by a reduced pressure epitaxy method (RP Epi) as shown in fig. 3A, and then a hafnium oxide thin film of 5 to 10nm thickness is formed on the germanium layer by an atomic layer deposition ALD method as shown in fig. 3B. A silicon dioxide layer with a thickness of 0.2 to 1 μm is formed on the germanium layer on the support substrate 200 by an isothermal oxidation CVD method, as shown in fig. 3C.
It should be noted that the hafnium oxide film can effectively reduce the influence of the bonding process on the germanium layer, and meanwhile, the hafnium oxide film is a high-k dielectric film, and can achieve a better current blocking effect with a thinner film, so that the thickness of the silicon dioxide layer can be smaller, but the silicon dioxide layer is not only used as a current blocking layer, and meanwhile, the silicon dioxide layer cannot be too thin as a key layer for improving the bonding effect.
Step S02, bonding the auxiliary substrate 100 to the supporting substrate 200, as shown in fig. 3D.
In this embodiment, the buried dielectric layer 201 of the auxiliary substrate 100 is surface-bonded to the supporting substrate 200 by a bonding apparatus, and the bonding process includes:
maximum temperature range of the chamber: 200 ℃ and 550 ℃;
bonding maximum pressure range: 1-60 KN;
bonding time range: 0.5-4 hours;
bonding chamber vacuum range: 1X 10-5mbar to 1 atm.
In one embodiment, the bonding process is:
maximum temperature of the chamber: 500 ℃;
bonding maximum pressure range: 10-30 KN;
bonding time: 2 hours;
degree of vacuum of bonding chamber: 5X 10-4mbar to 1 x 10-5mbar。
It should be noted that, in order to enhance the bonding effect, the pressurizing and/or heating process of the bonding process may be performed in a stepwise manner, for example, setting the step size of the bonding pressure increase to 10 minutes, increasing the pressure by 2KN per step size until the set pressure value is reached, and then maintaining the pressure until the bonding process is finished; it is of course also possible to carry out a linear pressurization, for example, set to a set pressure value within 3 minutes, and then to maintain the pressure until the bonding process is finished; further, when the bonding process is completed, the pressure may be reduced by a stepwise or linear reduction until the external pressure is no longer applied, depending on the effect of use.
Furthermore, the above-mentioned range of, for example, bonding processes is a feasible process window which can be found out through a lot of experiments, for example, when the chamber temperature is lower than 200 ℃, the auxiliary substrate 100 and the supporting substrate 200 cannot be bonded well, and if it is too high, for example, higher than 800 ℃, the germanium layer may be melted and/or evaporated; similarly, when the bonding pressure value is less than 1KN, the two substrates cannot be bonded together, and when the bonding pressure is greater than 60KN, the substrates may be chipped, and excessive internal stress may remain in the substrates, resulting in a decrease in reliability of the epitaxial layer 101, and therefore, the above-described bonding process range is a feasible process range.
Further, in order to improve the bonding effect, the auxiliary substrate 100 and the supporting substrate 200 may be pre-treated before bonding, for example, standard cleaning and/or chemical reagent treatment such as isopropyl alcohol is performed to form a clean substrate surface, and then the auxiliary substrate 100 and the supporting substrate 200 may be pre-baked at a low temperature before bonding to remove moisture on the surface and improve the bonding quality. In addition, the bonded substrate may be subjected to a low temperature annealing process to relieve stress formed in the substrate during bonding.
Step S03, the auxiliary substrate 100 is removed, as shown in fig. 3E to 3F.
In this embodiment, the removing the auxiliary substrate 100 includes: performing mechanical grinding on the back surface of the auxiliary substrate 100 until the thickness of the auxiliary substrate 100 becomes less than 50 μm, as shown in fig. 3E; the remaining auxiliary substrate 100 is removed by etching with a diluted TMAH solution, as shown in fig. 3F.
In a specific embodiment, the auxiliary substrate 100 is ground from the back side to less than 50 μm by mechanical grinding, and then the auxiliary substrate 100 is etched by a diluted TMAH solution. And the TMAH solution diluted by a certain concentration is selected to corrode the rest silicon substrate, so that the method has the advantages of controllable corrosion rate and good uniformity. Of course, before etching, the back surface of the support substrate 200 needs to be protected, for example, a photoresist is coated on the back surface of the support substrate 200 or a thin film that does not react with the TMAH solution is deposited, so as to reduce the influence of the TMAH solution on the support substrate 200.
It should be noted that, in the process of removing the auxiliary substrate 100 provided in this embodiment, the portion of the auxiliary substrate 100 in contact with the epitaxial layer 101 is removed by using a TMAH solution having a high selective etching ratio for the silicon substrate, so that when the back surface of the auxiliary substrate 100 is polished, efficiency can be prioritized, that is, the polishing can be performed at a higher speed to improve production efficiency.
In step S04, chemical mechanical planarization CMP is performed until the epitaxial layer 101 reaches a specified thickness, as shown in fig. 3G.
In this embodiment, the exposed epitaxial layer 101 is subjected to a planarization process by CMP until the thickness of the epitaxial layer 101 reaches a prescribed thickness. The epitaxial layer 101 having a precise thickness and having a flat surface can be formed by the CMP process.
It should be noted that, because the lattice constant of the epitaxial layer material is usually inconsistent with the lattice constant of the substrate, the quality of the initial epitaxial layer 101 is not high, and the epitaxial layer part with low epitaxial quality can be removed by the CMP process step provided by the present invention, so that the device manufactured by using the substrate provided by the present invention is formed in the high-quality epitaxial layer 101, so as to improve the performance and reliability of the device.
In the embodiment provided by the invention, the stacked layer at least comprising the epitaxial layer 101 and the passivation layer 102 and the buried dielectric layer 201 are respectively formed on the two bulk silicon substrates, and the passivation layer 102 can effectively reduce the influence of long-term high temperature and high pressure on the epitaxial layer 101 in the bonding process, so that a high-quality oxide buried layer and an upper semiconductor layer thereof are formed on the substrate, and the performance and reliability of a device manufactured by using the epitaxial layer 101 are improved.
Example two
A method for manufacturing a substrate, as described in the first embodiment, except that in the present embodiment, the auxiliary substrate 100 is a sige substrate; the epitaxial layer 101 comprises a buffer layer 1011 and a useful layer 1012; the passivation layer 102 is an aluminum oxide film with the thickness of 5-10 nm; the buried dielectric layer 201 is formed by a thermal oxidation method, as shown in fig. 4A to 4G.
Step S11, providing an auxiliary substrate 100 and a supporting substrate 200, where the auxiliary substrate 100 at least includes an epitaxial layer 101 and a passivation layer 102 on the epitaxial layer 101, and the supporting substrate 200 at least includes a buried dielectric layer 201, as shown in fig. 4A to 4C.
In this embodiment, the auxiliary substrate 100 is a silicon germanium substrate, the supporting substrate 200 is a bulk silicon substrate, and the epitaxial layer 101 includes a buffer layer 1011 and a useful layer 1012; the passivation layer 102 is an aluminum oxide film with the thickness of 5-10 nm; the buried dielectric layer 201 is a silicon dioxide film formed by a thermal oxidation method.
In the present embodiment, the buffer layer 1011 may adopt an epitaxial growth process to epitaxially grow Ge with a gradually changed composition on the bulk silicon substrate 100xSi1-xLayer of which 0<x<1, x of the initial epitaxial layer 101 is closer to 0, and x is closer to 1 near the end of epitaxial growth, and the thickness of the epitaxial layer 101 may be 1-500nm, depending on the practical effect. The buffer layer 1011 can effectively improve the problem of low epitaxial quality caused by the fact that the lattice constant of the epitaxial layer material is different from the lattice constant of the substrate material, and the buffer layer 1011 can be removed through subsequent CMP and other processes.
It should be noted that the passivation layer 102 is an aluminum oxide thin film with a thickness of 5-10nm, when the thermal conductivity of the passivation layer 102 is higher than that of the buried dielectric layer 201, or more specifically, when the thermal conductivity of the passivation layer 102 is greater than 10W · cm at room temperature-1·K-1While the passivation layer 102 can be considered to have high thermal conductivity. With the continuous development of integrated circuit technology, the number of devices integrated per unit area is exponentially increased, and the subsequent problem is the heat dissipation problem of the devices, which directly affects the performance and reliability of the devices finally manufactured. In the embodiment, the aluminum oxide film with the thickness of 5-10nm is used as the passivation layer 102, so that the influence of the bonding process on the epitaxial layer 101 can be effectively reduced, and the aluminum oxide film has a thickness of more than 10W-cm-1·K-1The thermal conductivity of the semiconductor substrate is improved, and the aluminum oxide is a high-k medium, so that the current blocking effect can be enhanced, and meanwhile, the thickness of an oxide buried layer with low thermal conductivity formed in the semiconductor substrate through a bonding process is reduced, the heat dissipation of a device is facilitated, and the performance and the reliability of the device are improved.
In one embodiment, two substrates of the same size are provided, wherein a silicon germanium substrate is used as the auxiliary substrate 100 and a bulk silicon substrate is used as the support substrate 200. Epitaxially growing compositionally graded Ge on the auxiliary substrate 100 by Molecular Beam Epitaxy (MBE) or reduced pressure epitaxyxSi1-xThe layer serves as a buffer layer 1011 of which 0<x<1, x of the initial epitaxial layer 101 is closer to 0, x is closer to 1 near the end of epitaxial growth, the buffer layer 1011 has a thickness of 1-500nm, and then a germanium layer having a thickness of 0.2-1 μm is epitaxially grown, as shown in fig. 4A; then, an aluminum oxide thin film having a thickness of 5 to 10nm is formed on the germanium layer by an atomic layer deposition ALD method, as shown in fig. 4B. A silicon dioxide thin film having a thickness of 0.2 to 1 μm is formed on the support substrate 200 by a thermal oxidation method, as shown in fig. 4C.
It should be noted that a dense silicon dioxide film can be formed by a thermal oxidation method to improve the insulating effect. Before the epitaxial growth, the auxiliary substrate 100 may be pre-etched by using TMAH solution to improve the quality of the epitaxial layer 101.
Step S12, bonding the auxiliary substrate 100 to the supporting substrate 200, as shown in fig. 4D.
Specifically, the bonding process comprises the following steps:
maximum temperature of the chamber: 550 ℃;
bonding maximum pressure range: 8-20 KN;
bonding time: 1 hour;
degree of vacuum of bonding chamber: 1X 10-4mbar to 1 x 10-5mbar。
Steps S13 to S14 are similar to steps S03 to S04 of the first embodiment, as shown in fig. 4E to 4G, and are not described in detail herein.
In the substrate manufacturing method provided by the embodiment of the invention, the aluminum oxide film with the thickness of 5-10nm is formed on the epitaxial layer 101 to be used as the passivation layer 102, and the passivation layer 102 is larger than 10W-cm at room temperature-1·K-1The epitaxial layer 101 has high thermal conductivity, so that the influence of a bonding process on the epitaxial layer 101 can be reduced, the thickness of an oxide buried layer with low thermal conductivity formed in a semiconductor substrate by the existing bonding process can be reduced, the heat dissipation of a device is facilitated, and the performance and the reliability of the device are improved.
EXAMPLE III
A method for manufacturing a substrate, as described in the first embodiment, except that the epitaxial layer 101 is a germanium tin layer; the support substrate 200 is a sapphire substrate; the epitaxial layer 101 comprises a buffer layer 1011 and a useful layer 1012; the passivation layer 102 is an aluminum oxide film with the thickness of 5-10 nm; the auxiliary substrate 100 includes an epitaxial layer 101, a passivation layer 102 on the epitaxial layer 101, and an oxide material layer 103 on the passivation layer 102, as shown in fig. 5A to 5F.
Step S21, providing an auxiliary substrate 100 and a supporting substrate 200, where the auxiliary substrate 100 at least includes an epitaxial layer 101 and a passivation layer 102 on the epitaxial layer 101, and the supporting substrate 200 at least includes a buried dielectric layer 201, as shown in fig. 5A to 5B.
In this embodiment, different from the first embodiment, besides the epitaxial layer 101 and the passivation layer 102 formed on the epitaxial layer 101, an oxide layer 103 formed on the passivation layer 102 is also formed on the auxiliary substrate 100, as shown in fig. 5A; the material of the oxide layer 103 may be the same as or different from that of the buried dielectric layer 201, preferably, the material of the oxide layer 103 is the same as that of the buried dielectric layer 201, and the sum of the thicknesses of the oxide layer 103 and the buried dielectric layer 201 is equal to the preset thickness of the oxide buried layer. The oxide layer 103 on the passivation layer 102 can further reduce the influence of the bonding process on the epitaxial layer 101, so as to improve the performance and reliability of the device formed on the epitaxial layer 101. It should be noted that the sum of the thicknesses of the oxide layer 103 and the buried dielectric layer 201 may be equal to the predetermined thickness of the buried oxide layer, that is, the buried dielectric layer 201 may not be formed on the supporting substrate 200, and the thickness of the oxide layer of the auxiliary epitaxial layer 101 may be equal to the predetermined thickness of the buried oxide layer.
The epitaxial layer 101 may include a buffer layer 1011 and a useful layer 1012 on the buffer layer 1011. For example, in the present embodiment, the auxiliary substrate 100 is a bulk silicon substrate, the useful layer 1012 is a germanium-tin epitaxial layer, and the buffer layer 1011 is a silicon-germanium epitaxial layer to alleviate the problem that the lattice constant of the germanium-tin material is mismatched with the lattice constant of the silicon material to cause low epitaxial quality of the useful layer 1012.
The buried dielectric layer 201 may be an oxide film formed by a process such as PECVD, as shown in fig. 5B, or may be a stack of common dielectric films such as silicon dioxide and silicon oxynitride. The passivation layer 102 is an alumina thin film with a thickness of 5-10nm, and functions in detail with reference to the contents of the relevant portions of the example.
The support substrate 200 is a sapphire substrate, and since sapphire has a high thermal conductivity and very high hardness, it can be used for manufacturing chips with high mechanical strength. In addition, since the selective etching ratios of the sapphire material and the silicon material with respect to the TMHA solution are very different, when the auxiliary substrate 100 is subsequently removed, a step such as coating a photoresist on the back surface of the silicon substrate may not be performed on the silicon substrate to protect the supporting substrate 200 from being affected.
In a specific embodiment, a silicon germanium layer with the thickness of 200nm and a germanium tin layer with the thickness of 2 μm are epitaxially formed on a bulk silicon substrate in sequence by an ultrahigh vacuum chemical vapor deposition (UHVCVD) method and/or a Reactive Plasma Chemical Vapor Deposition (RPCVD) method to respectively serve as a buffer layer 1011 and a useful layer 1012; then forming an aluminum oxide film with the thickness of 5-10nm by an ALD method; then, a silicon dioxide film having a thickness of 0.2 μm was formed by a low pressure chemical vapor deposition LPCVD method. A silicon dioxide film with a thickness of 0.3 μm was formed on a sapphire substrate by a High Density Plasma Chemical Vapor Deposition (HDPCVD) method.
Step S22, bonding the auxiliary substrate 100 to the supporting substrate 200, as shown in fig. 5C.
Specifically, the bonding process comprises the following steps:
maximum temperature of the chamber: 500 ℃;
bonding maximum pressure range: 8-20 KN;
bonding time: 3 hours;
degree of vacuum of bonding chamber: 1X 10-4mbar to 1 x 10-5mbar。
In steps S23 to S24, the schematic cross-sectional structure in the substrate manufacturing process is shown in fig. 5D to 5F, and the details refer to the second embodiment, which will not be described herein.
In this embodiment, an aluminum oxide thin film with a thickness of 5-10nm is formed on the epitaxial layer 101 as the passivation layer 102, and then the oxide layer 103 with a specified thickness is formed on the passivation layer 102, so that the passivation layer 102 and the oxide layer 103 can be used to reduce the influence of the bonding process on the epitaxial layer 101, and improve the performance and reliability of the device formed on the epitaxial layer 101.
Accordingly, the present invention also provides a substrate manufactured according to the above method, as shown with reference to fig. 3G, comprising:
a support substrate 200;
a buried dielectric layer 201 over the support substrate 200;
a passivation layer 102 over the buried dielectric layer 201;
an epitaxial layer 101 of a specified thickness is over the passivation layer 102.
Wherein, the passivation layer 102 is an aluminum oxide film with the thickness of 5-10 nm.
The substrate provided by the invention can be used for manufacturing a semiconductor device structure, and comprises the following components: the substrate according to the above embodiment, and the device structure located at the epitaxial layer, the device structure may include: a gate dielectric layer 303 located on the epitaxial layer 101, a gate 304 located on the gate dielectric layer 303, source/drain regions 302 located at two sides of the gate 304, and an isolation 301 for isolating the source/drain regions 302, as shown in fig. 6. The gate 304 may be a polysilicon gate or a metal gate; when the gate electrode 304 is a metal gate, the gate dielectric layer 303 preferably uses a high-k dielectric material such as hafnium oxide, tantalum oxide, aluminum oxide, zirconium oxide, etc. Of course, the epitaxial layer 101 may also be used to form fins to fabricate finfets. However, the present invention is not limited thereto, and other semiconductor devices such as a transistor, a diode, an LSI, and the like may also be formed.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present invention, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (6)
1. A method of manufacturing a substrate, comprising:
providing an auxiliary substrate and a supporting substrate, wherein the auxiliary substrate at least comprises an epitaxial layer, a passivation layer on the epitaxial layer and an oxide substance layer on the passivation layer, the epitaxial layer comprises a buffer layer and a useful layer, the supporting substrate at least comprises a buried dielectric layer, the material of the oxide substance layer is the same as that of the buried dielectric layer, the sum of the thicknesses of the oxide substance layer and the buried dielectric layer is equal to the preset thickness of the oxide buried layer, the passivation layer is a high-k dielectric layer, and the high-k dielectric layer is an aluminum oxide film with the thickness of 5-10 nm;
bonding the auxiliary substrate to the support substrate, the bonding process of the auxiliary substrate to the support substrate comprising:
maximum temperature range of the chamber: 200 ℃ and 550 ℃;
bonding maximum pressure range: 1-60 KN;
bonding time range: 0.5-4 hours;
bonding chamber vacuum range: 1X 10-5mbar to 1 atm;
removing the auxiliary substrate;
chemical mechanical planarization CMP is performed until the epitaxial layer reaches a specified thickness.
2. The method of claim 1, wherein the epitaxial layer comprises: germanium layer, silicon germanium layer, germanium tin layer, III-V compound semiconductor layer, silicon layer and their lamination.
3. The method of claim 1, wherein the auxiliary substrate is a silicon substrate, and wherein removing the auxiliary substrate comprises:
mechanically grinding the back surface of the auxiliary substrate until the thickness of the auxiliary substrate is less than 50 μm;
and etching by using diluted TMAH solution to remove the residual auxiliary substrate.
4. The method of claim 1, wherein the bonding process is:
maximum temperature of the chamber: 500 ℃;
bonding maximum pressure range: 10-30 KN;
bonding time: 2 hours;
degree of vacuum of bonding chamber: 5X 10-4mbar to 1 x 10-5mbar。
5. A substrate manufactured by the substrate manufacturing method according to any one of claims 1 to 4, comprising:
a support substrate;
a buried dielectric layer over the support substrate;
an oxide layer over the buried dielectric layer;
a passivation layer over the oxide layer;
an epitaxial layer with a specified thickness is arranged on the passivation layer, and the epitaxial layer comprises a buffer layer and a useful layer;
the material of the oxide substance layer is the same as that of the buried dielectric layer, the sum of the thicknesses of the oxide substance layer and the buried dielectric layer is equal to the preset thickness of the oxide buried layer, the passivation layer is a high-k dielectric layer, and the high-k dielectric layer is an aluminum oxide film with the thickness of 5-10 nm.
6. A semiconductor device, comprising: the substrate of claim 5, and a device structure located at the epitaxial layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510708606.5A CN106611740B (en) | 2015-10-27 | 2015-10-27 | Substrate and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510708606.5A CN106611740B (en) | 2015-10-27 | 2015-10-27 | Substrate and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106611740A CN106611740A (en) | 2017-05-03 |
| CN106611740B true CN106611740B (en) | 2020-05-12 |
Family
ID=58614646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510708606.5A Active CN106611740B (en) | 2015-10-27 | 2015-10-27 | Substrate and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106611740B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491826B (en) | 2019-07-31 | 2020-09-29 | 北京工业大学 | Transfer method of compound semiconductor single crystal thin film layer and preparation method of single crystal GaAs-OI composite wafer |
| CN111834286B (en) * | 2020-07-24 | 2021-11-30 | 广东省大湾区集成电路与系统应用研究院 | Semiconductor insulating substrate, transistor and preparation method thereof |
| CN112447771B (en) * | 2020-10-16 | 2023-12-01 | 广东省大湾区集成电路与系统应用研究院 | GeSiOI substrate and preparation method thereof, and GeSiOI device and preparation method thereof |
| CN116666236B (en) * | 2023-08-02 | 2023-11-21 | 深圳市鲁光电子科技有限公司 | Surface passivation method of semiconductor material |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5494849A (en) * | 1995-03-23 | 1996-02-27 | Si Bond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator substrates |
| CN101615590B (en) * | 2009-07-31 | 2011-07-20 | 上海新傲科技股份有限公司 | Method for preparing silicon-on-insulator material using selective corrosion process |
| JP2013110161A (en) * | 2011-11-17 | 2013-06-06 | National Institute Of Advanced Industrial & Technology | Substrate for element formation and manufacturing method therefor |
| CN103794471A (en) * | 2014-01-14 | 2014-05-14 | 上海新储集成电路有限公司 | Method for preparing compound semiconductor substrate |
| US9355889B2 (en) * | 2014-03-28 | 2016-05-31 | Imec Vzw | Semiconductor-on-insulator device and method of fabricating the same |
-
2015
- 2015-10-27 CN CN201510708606.5A patent/CN106611740B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN106611740A (en) | 2017-05-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106611739B (en) | Substrate and method for manufacturing the same | |
| CN109844184B (en) | Engineered substrate structures for power and radio frequency applications | |
| KR102403038B1 (en) | Electronic Power Device Integrated with Machined Substrate | |
| JP7105239B2 (en) | Gallium nitride epitaxial structure for power devices | |
| US10755986B2 (en) | Aluminum nitride based Silicon-on-Insulator substrate structure | |
| US10930576B2 (en) | Gallium-nitride based devices implementing an engineered substrate structure | |
| US8946063B2 (en) | Semiconductor device having SSOI substrate with relaxed tensile stress | |
| US20140048765A1 (en) | Semiconductor device and method for manufacturing the same | |
| KR20080108498A (en) | Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor | |
| CN112447771B (en) | GeSiOI substrate and preparation method thereof, and GeSiOI device and preparation method thereof | |
| CN106611740B (en) | Substrate and method for manufacturing the same | |
| JP7118069B2 (en) | Method and system for vertical power devices | |
| WO2019118473A1 (en) | Methods for transistor epitaxial stack fabrication | |
| US20230395376A1 (en) | Semiconductor substrates and methods of producing the same | |
| CN103548126B (en) | The manufacture method of semiconductor substrate and semiconductor substrate | |
| CN106449663B (en) | Semiconductor-on-insulator structure and method of fabrication | |
| CN106558612B (en) | P-type fin field effect transistor and manufacturing method thereof | |
| US20240258321A1 (en) | Composite substrate and method for manufacturing the same, and semiconductor device structure | |
| CN106449368B (en) | Semiconductor structure and preparation method | |
| CN106558613B (en) | N-type fin field effect transistor and manufacturing method thereof | |
| CN117790559A (en) | GaN HEMT device structure and preparation method thereof | |
| CN117613079A (en) | GaN HEMT device structure and preparation method thereof | |
| KR20190108260A (en) | Semiconductor device using interdiffusion and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220119 Address after: 510000 building a, No. 136, Kaiyuan Avenue, development zone, Guangzhou, Guangdong Patentee after: Guangdong Dawan District integrated circuit and System Application Research Institute Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |