CN101615590B - Method for preparing silicon-on-insulator material using selective corrosion process - Google Patents
Method for preparing silicon-on-insulator material using selective corrosion process Download PDFInfo
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Abstract
A method for preparing a silicon-on-insulator material using selective corrosion process comprises the following steps: providing a doped monocrystalline silicon substrate; growing an undoped intrinsic monocrystalline silicon layer on the surface of the monocrystalline silicon substrate; growing a component layer on the surface of the monocrystalline silicon substrate; providing a support substrate; growing an insulating layer; bonding the monocrystalline silicon substrate with the support substrate; selecting the selective corrosion process to remove the doped monocrystalline silicon substrate; removing the intrinsic monocrystalline silicon layer. The invention is characterized by adopting the intrinsic monocrystalline silicon layer as the etch-stop layer and removing the intrinsic monocrystalline silicon layer in post process by methods of overheating oxidation and the like, thus the technical proposal provided by the invention can be used for preparing the silicon-on-insulator substrate with top silicon of arbitrary resistivity.
Description
[technical field]
The present invention relates to field of semiconductor devices, relate in particular to a kind of method that adopts selective etching prepared silicon-on-insulator material.
[background technology]
Compare with the body silicon device, silicon-on-insulator (SOI) device has advantages such as high speed, low driving voltage, high temperature resistant, low-power consumption and anti-irradiation, enjoys people's attention, is all obtaining development fast aspect material and the preparation of devices.The SOI material can be divided into thin film SOI (top layer silicon thickness is less than 1 micron) and thick film SOI (top layer silicon thickness is greater than 1 micron) two big classes by the thickness of its top layer silicon thin layer.
At present, the technology of preparing of SOI material mainly contain injection oxygen isolation technology (SIMOX), bonding and back side corrosion technology (BESOI) and the smart peeling technology (Smart-cut), epitaxial loayer transfer techniques (ELTRAN) of deriving out etc.Wherein, technology is simple because bonding and back side corrosion technology have, low cost and other advantages, therefore is subject to people's attention, though oxygen buried layer thickness is adjustable continuously, but by the way attenuate top layer silicon of grinding or corroding, the thickness evenness of top layer silicon is difficult to precisely controlled.Is on the basis of 1 ± 0.3 mu m bonded attenuate SOI material as P.B.Mumola etc. at top layer silicon thickness, adopt the special way of computer controlled controlling partially plasma attenuate, top layer silicon is thinned to 0.1 μ m, evenness only can be controlled at ± 0.01 μ m, and this has also just limited bonding and wafer thinning SOI material in the application that the top layer silicon thickness evenness is required aspect high.And the SOI material that adopts the SIMOX technology to prepare, though have excellent top layer silicon thickness evenness, but owing to be subjected to the restriction of implantation dosage and energy, the oxygen buried layer maximum ga(u)ge is difficult to surpass 400nm, and SIMOX technology is to utilize high annealing, promote oxygen to form continuous oxygen buried layer in silicon chip inner gathering nucleation, but the SiO that the pin hole that exists in the oxygen buried layer makes its insulation property form not as thermal oxidation
2, puncture voltage is only about 6MV/cm, these drawbacks limit the application of SIMOX material aspect thick buried regions (greater than 400nm).
The Smart-cut technology develops on the basis of bonding techniques, and the thickness of its top layer silicon is determined by hydrionic injection energy, its thickness is adjustable continuously, therefore this technology can satisfy oxygen buried layer thickness and the inhomogeneity requirement of top layer silicon simultaneously, but this technology is peeled off device layer owing to adopt hydrogen ion to inject, so production cost is higher.The epitaxial loayer transfer techniques need be on porous silicon the epitaxy single-crystal silicon layer, defective control difficulty, the prematurity still of this technology, the not report of using.
Technology is simple because bonding and back side corrosion technology have, low cost and other advantages, but the difficult control of uniformity.Its main starting point is the lightly doped device layer of extension on the heavy doping device substrate, grinds attenuate behind the bonding, and (main component is 1HF:3HNO to utilize HNA solution
3: 8CH
3COOH) weight is mixed the different corrosion rate of layer and remove heavily doped layer, realize the transfer of lightly-doped layer, prepare the thick film SOI substrate.Used the corrosion selectivity of HNA solution in the method to the different resistivity material, but, HNA solution will reach good corrosion to be selected than needing doping content to have tangible difference, and this has just limited the application of this technology aspect preparation low-resistivity top layer silicon (resistivity is less than 10 Ω cm) SOI substrate.And direct epitaxial light doped layer on the heavy doping substrate, because the transition region of a resistivity gradual change is arranged between the heavy and light doped layer that autodoping effect is, rather than present the abrupt change resistivity distribution, and local electrical resistance rate skewness in this transition region makes that the SOI substrate top layer silicon thickness evenness of preparing is relatively poor.
[summary of the invention]
Technical problem to be solved by this invention is, a kind of method for preparing silicon-on-insulator material is provided, and breaks through the restriction of existing etching process, can prepare the top layer silicon with any resistivity.
In order to address the above problem, the invention provides a kind of method that adopts selective etching prepared silicon-on-insulator material, comprise the steps: to provide the monocrystalline substrate of doping; Intrinsic monocrystalline silicon layer in the non-doping of monocrystalline substrate superficial growth; In intrinsic monocrystalline surface growth of device layers; Provide support substrate; At the superficial growth insulating barrier of support substrates and device layer, perhaps at the superficial growth insulating barrier of support substrates or device layer; With monocrystalline substrate and support substrates bonding, if at support substrates superficial growth insulating barrier, then the exposed surface with insulating barrier and device layer is a bonding face, if at the epontic insulating barrier of device layer, then the exposed surface with support substrates and insulating barrier is a bonding face, if all grow insulating barrier on the surface of device layer and support substrates, then should be respectively be bonding face with the exposed surface of two insulating barriers; Adopt selective corrosion technology to remove the monocrystalline substrate of doping; Adopt selective corrosion technology to remove the monocrystalline substrate of doping; Remove the intrinsic monocrystalline silicon layer.
As optional technical scheme, the thickness of described intrinsic monocrystalline silicon layer is greater than 50nm.
As optional technical scheme, the difference of the resistivity between monocrystalline substrate 100 and the intrinsic monocrystalline silicon layer 110 should be greater than 1000 times.The resistivity of the monocrystalline substrate of especially described doping is less than 0.02 Ω cm, and the resistivity of intrinsic monocrystalline silicon layer is greater than 20 Ω cm.
As optional technical scheme, the step of described removal monocrystalline substrate further comprises: be positioned on the spin etching platform on monocrystalline substrate one side direction with the sandwich construction behind the bonding; Make corrosive liquid flow through the monocrystalline substrate surface, and rotate the spin etching platform simultaneously, the monocrystalline substrate corrosion is removed.
As optional technical scheme, described corrosive liquid is a hydrofluoric acid, external direct current power supply in the corrosion process, and monocrystalline substrate is connected with positive source electricity, and electrolyte is connected with power cathode electricity.
As optional technical scheme, described corrosive liquid is the mixed liquor of hydrofluoric acid, nitric acid and acetic acid.
As optional technical scheme, adopt the method for grinding or oxidation to remove the intrinsic monocrystalline silicon layer.。
The invention has the advantages that, adopted the intrinsic monocrystalline silicon layer as corrosion stop layer certainly, and in subsequent technique, be removed by methods such as thermal oxidations.The intrinsic monocrystalline silicon layer can not corroded by the protection device layer in the technology of selective corrosion; so device layer can have resistivity arbitrarily; and it is follow-up by thermal oxidation or grinding; but not selective corrosion technology removes the intrinsic monocrystalline silicon layer, therefore can guarantee that device layer can not sustain damage in the process of removing the intrinsic monocrystalline silicon layer.In sum, technical scheme provided by the present invention can be used to prepare the silicon-on-insulator substrate with any resistivity top layer silicon.
[description of drawings]
It shown in the accompanying drawing 1 the implementation step schematic diagram of embodiment of the method for employing selective etching prepared silicon-on-insulator material of the present invention;
Accompanying drawing 2 is to the process chart of embodiment that shown in the accompanying drawing 9 is the method for employing selective etching prepared silicon-on-insulator material of the present invention.
[embodiment]
Below in conjunction with accompanying drawing the embodiment that the invention provides the method that adopts selective etching prepared silicon-on-insulator material is elaborated.
Be the implementation step schematic diagram of this embodiment shown in the accompanying drawing 1, comprise: step S10 provides the monocrystalline substrate of doping; Step S11 is at the intrinsic monocrystalline silicon layer of the non-doping of monocrystalline substrate superficial growth; Step S12 is in intrinsic monocrystalline surface growth of device layers; Step S13 provides support substrate; Step S14 is at support substrates superficial growth insulating barrier; Step S15 is a bonding face with the exposed surface of insulating barrier and device layer, carries out bonding; Step S16 adopts selective corrosion technology to remove the monocrystalline substrate of doping; Step S17 removes the intrinsic monocrystalline silicon layer.
Accompanying drawing 2 is depicted as the process chart of this embodiment to accompanying drawing 9.
Shown in the accompanying drawing 2, refer step S10 provides the monocrystalline substrate 100 of doping.
In order can 100 corrosion of this monocrystalline substrate to be removed by selective corrosion technology in the subsequent step, thus this embodiment adopt the monocrystalline silicon that mixes and extrinsic monocrystalline silicon as the material of substrate.
Shown in the accompanying drawing 3, refer step S11 is at the intrinsic monocrystalline silicon layer 110 of the non-doping of monocrystalline substrate 100 superficial growths.
Intrinsic monocrystalline silicon layer 110 will use as special etch stop layer in subsequent step in this step, and therefore 110 thickness of described intrinsic monocrystalline silicon layer are 50nm to 5 μ m.The thickness of intrinsic monocrystalline silicon layer 110 can guarantee its reliability as corrosion barrier layer greater than the advantage of 50nm, and is and can be removed by thermal oxidation technology less than the meaning of 5 μ m.
As optimized technical scheme, the difference of the resistivity between monocrystalline substrate 100 and the intrinsic monocrystalline silicon layer 110 should be greater than 1000 times.For example the resistivity of the monocrystalline substrate 100 of described doping is less than 0.02 Ω cm, and the resistivity of intrinsic monocrystalline silicon layer 110 is greater than 20 Ω cm.Ratio is selected in the corrosion that above condition helps improving in the selective corrosion process, can guarantee monocrystalline substrate 100 whole corrosion are removed, and levies monocrystalline silicon layer 110 and be stale-proof to lose capital as far as possible.
Shown in the accompanying drawing 4, refer step S12 is at intrinsic monocrystalline silicon layer 110 superficial growth device layers 120.
The meaning of so-called device layer is that this layer will be as the top silicon layer of silicon-on-insulator material in subsequent step, and this layer is generally used for growth of device, so be referred to as device layer.The material of the device layer 120 described in this step is the monocrystalline silicon with any doping content, and in other embodiment, this device layer 120 also can be other common semi-conducting materials arbitrarily.
Shown in the accompanying drawing 5, refer step S13 provides support substrate 200.
In this embodiment, the material of described support substrates 200 is a monocrystalline silicon.In other embodiment, the material of described support substrates 200 can also be any common semi-conducting material, also can be that sapphire etc. is usually used in the non-semiconductor material as substrate, even can be metal material, for example copper or aluminium etc.
Shown in the accompanying drawing 6, refer step S14 is at support substrates 200 superficial growth insulating barriers 210.
In this embodiment because the material of support substrates 200 is a monocrystalline silicon, the method for therefore selecting thermal oxidation for use at its superficial growth silicon dioxide as insulating barrier 210.Adopt the silica compact structure of thermal oxidation technology growth, therefore good insulating is a kind of selection process.In other embodiment, also can adopt materials such as other common technology growing silicon oxides such as chemical deposition or silicon nitride as insulating barrier 210.
In other execution mode, also can be chosen in the superficial growth insulating barrier of device layer 120, even the insulating barrier of also can all growing on the surface of device layer 120 and support substrates 200.
Shown in the accompanying drawing 7, refer step S15 is a bonding face with the exposed surface of insulating barrier 210 and device layer 120, carries out bonding.
Bonding again after bonding can at first adopt plasma that the surface is activated also can Direct Bonding.Can select to reinforce at low temperatures after the bonding.Perhaps adopt conventional hydrophilic bonding, ruggedization under lower temperature.So-called ruggedization under lower temperature, it reinforces temperature range is 400～800 ℃.
In other execution mode,, then should be that exposed surface with insulating barrier 210 and support substrates 200 is as bonding face if insulating barrier is the surface that is grown in device layer 120.If all grow insulating barrier on both surfaces of device layer 120 and support substrates 200, then should be respectively be bonding face with the exposed surface of two insulating barriers.
Shown in the accompanying drawing 8, refer step S16 adopts selective corrosion technology to remove the monocrystalline substrate 100 of doping.
In this embodiment, step S16 further comprises: be positioned on the spin etching platform on monocrystalline substrate one side direction with the sandwich construction behind the bonding; Make corrosive liquid flow through the monocrystalline substrate surface, and rotate the spin etching platform simultaneously, the monocrystalline substrate corrosion is removed.
Described corrosive liquid is the mixed liquor of hydrofluoric acid or hydrofluoric acid, nitric acid and acetic acid.
In adopting the technology of hydrofluoric acid as corrosive liquid, need an external direct current power supply, monocrystalline substrate is connected with positive source electricity, and voltage is 5～30V.Electrolyte is connected with power cathode electricity, and corrosive liquid adopts 5% hydrofluoric acid solution.Whole loop is connected when electrolyte is sprayed onto wafer surface.Positive electrode provides the hole, makes surperficial Si be in high valence state, and chemical reaction is as follows:
Si+4h
+→Si
4+
The Si of high valence state and OH
-In conjunction with, have:
Si
4++OH
-→SiO
2+H
2
Silicon dioxide can enter in the solution silicon atom with the hydrofluoric acid reaction, reaches the purpose that corrosion is removed.
In corrosion process, also insert an ammeter in the loop with the electric current between monitoring substrate and the electrolyte.Can be by the accurately whole corrosion reaction of control of variation of electric current.When eroding to intrinsic monocrystalline silicon layer 110, from high to low a sudden change can take place in electric current, and in time stop corrosion this moment, can guarantee that promptly monocrystalline substrate 100 corrosion that will mix remove and keep intrinsic monocrystalline silicon layer 110.Because the silicon atom in the intrinsic monocrystalline silicon layer 110 is inactive, therefore be not easy ionization and and OH
-React, therefore can realize the purpose of selective corrosion.Since intrinsic monocrystalline silicon layer 110 be not fully with corrosive liquid reaction, and just reaction speed is slower, so the thick more protection device layer 120 that helps more of the intrinsic monocrystalline silicon layer 110 in this embodiment is not corroded, preferable thickness is greater than 50nm.
The electrochemical corrosive process that more than provides can obtain higher corrosion and select ratio, and the purpose of spin etching is to make corrosion rate more even.
Corrosive liquid can also be selected the mixed liquor of hydrofluoric acid, nitric acid and acetic acid, and three's mixed proportion is 1: 3: 8.Adopt this corrosive liquid, then do not need external dc power supply, HNO3 can provide the hole by reaction, and chemical equation is as follows:
HNO
3+H
2O+HNO
2→2HNO
2+2OH
-+2h
+
Therefore do not need extra DC electrode, but still need between corrosive liquid and electrode, connect an ammeter with the monitoring etch state.
Shown in the accompanying drawing 9, refer step S17 removes intrinsic monocrystalline silicon layer 110.
This step can adopt the method for grinding or thermal oxidation to remove intrinsic monocrystalline silicon layer 110.And preferably adopt thermal oxidation technology that intrinsic monocrystalline silicon layer 110 is fallen by oxidation consumption, and adopt the hydrofluoric acid corrosion to remove.Reason is that thermal oxidation is easy to accurate control, and the surfacing after the oxidation.Especially in this embodiment, the effect of intrinsic monocrystalline silicon layer 110 only is to play the effect of corrosion barrier layer, so thickness also needn't be excessive.Usually the thickness of intrinsic monocrystalline silicon layer 110 less than 5 microns situation under, the time of oxidation was an acceptable time range less than six hours, therefore can adopt thermal oxidation technology to remove intrinsic monocrystalline silicon layer 110.
Above step obtains the silicon substrate on the insulator after implementing to finish, and comprises support substrates 200, insulating barrier 210 and device layer 120.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (7)
1. a method that adopts selective etching prepared silicon-on-insulator material is characterized in that, comprises the steps:
The monocrystalline substrate of doping is provided;
Intrinsic monocrystalline silicon layer in the non-doping of monocrystalline substrate superficial growth;
In intrinsic monocrystalline surface growth of device layers;
Provide support substrate;
At the superficial growth insulating barrier of support substrates and device layer, perhaps at the superficial growth insulating barrier of support substrates or device layer;
With monocrystalline substrate and support substrates bonding, if at support substrates superficial growth insulating barrier, then the exposed surface with insulating barrier and device layer is a bonding face, if at the epontic insulating barrier of device layer, then the exposed surface with support substrates and insulating barrier is a bonding face, if all grow insulating barrier on the surface of device layer and support substrates, then should be respectively be bonding face with the exposed surface of two insulating barriers;
Adopt selective corrosion technology to remove the monocrystalline substrate of doping;
Adopt the method for thermal oxidation to remove the intrinsic monocrystalline silicon layer.
2. the method for employing selective etching prepared silicon-on-insulator material according to claim 1 is characterized in that, the thickness range of described intrinsic monocrystalline silicon layer is 50nm to 5 μ m.
3. the method for employing selective etching prepared silicon-on-insulator material according to claim 1 and 2 is characterized in that the difference of the resistivity between monocrystalline substrate 100 and the intrinsic monocrystalline silicon layer 110 should be greater than 1000 times
4. the method for employing selective etching prepared silicon-on-insulator material according to claim 3 is characterized in that, the resistivity of the monocrystalline substrate of described doping is less than 0.02 Ω cm, and the resistivity of intrinsic monocrystalline silicon layer is greater than 20 Ω cm.
5. the method for employing selective etching prepared silicon-on-insulator material according to claim 1 is characterized in that the step of described removal monocrystalline substrate further comprises:
Be positioned on the spin etching platform on monocrystalline substrate one side direction with the sandwich construction behind the bonding;
Make corrosive liquid flow through the monocrystalline substrate surface, and rotate the spin etching platform simultaneously, the monocrystalline substrate corrosion is removed.
6. the method for employing selective etching prepared silicon-on-insulator material according to claim 5, it is characterized in that described corrosive liquid is a hydrofluoric acid, external direct current power supply in the corrosion process, monocrystalline substrate is connected with positive source electricity, and electrolyte is connected with power cathode electricity.
7. the method for employing selective etching prepared silicon-on-insulator material according to claim 5 is characterized in that described corrosive liquid is the mixed liquor of hydrofluoric acid, nitric acid and acetic acid.
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| CN102817082B (en) * | 2011-06-08 | 2016-06-01 | 无锡华润华晶微电子有限公司 | A kind of preparation method of silicon fiml |
| CN102903607A (en) * | 2011-06-30 | 2013-01-30 | 上海新傲科技股份有限公司 | Method for preparing substrate with buried insulation layers by selective etching |
| CN102637607B (en) * | 2011-12-29 | 2016-02-24 | 上海新傲科技股份有限公司 | Three-dimension packaging method |
| CN105067165B (en) * | 2015-07-19 | 2018-02-02 | 江苏德尔森传感器科技有限公司 | The production technology of monocrystalline silicon sensors chip |
| CN106611740B (en) * | 2015-10-27 | 2020-05-12 | 中国科学院微电子研究所 | Substrate and method for manufacturing the same |
| CN110085510B (en) * | 2018-01-26 | 2021-06-04 | 沈阳硅基科技有限公司 | Preparation method of multilayer monocrystalline silicon thin film |
| CN111146141A (en) * | 2019-12-13 | 2020-05-12 | 中国科学院微电子研究所 | Preparation method of on-chip single crystal material |
| CN113421848B (en) * | 2021-05-24 | 2022-09-13 | 中环领先半导体材料有限公司 | Preparation process of silicon substrate on power insulator |
| CN114242647B (en) * | 2021-12-08 | 2022-11-18 | 中环领先半导体材料有限公司 | Method for improving thickness uniformity of device silicon layer of silicon wafer on insulator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155755A (en) * | 1995-12-12 | 1997-07-30 | 佳能株式会社 | Fabrication process of SOI (silicon on insulator) substrate |
| US6607968B1 (en) * | 1999-06-14 | 2003-08-19 | France Telecom | Method for making a silicon substrate comprising a buried thin silicon oxide film |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155755A (en) * | 1995-12-12 | 1997-07-30 | 佳能株式会社 | Fabrication process of SOI (silicon on insulator) substrate |
| US6607968B1 (en) * | 1999-06-14 | 2003-08-19 | France Telecom | Method for making a silicon substrate comprising a buried thin silicon oxide film |
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