CN100585805C - The preparation method of the silicon substrate on the insulator - Google Patents
The preparation method of the silicon substrate on the insulator Download PDFInfo
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- CN100585805C CN100585805C CN200810201039A CN200810201039A CN100585805C CN 100585805 C CN100585805 C CN 100585805C CN 200810201039 A CN200810201039 A CN 200810201039A CN 200810201039 A CN200810201039 A CN 200810201039A CN 100585805 C CN100585805 C CN 100585805C
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Abstract
The preparation method of the silicon substrate on a kind of insulator comprises the steps: that (a) provides monocrystalline substrate; (b) at monocrystalline substrate superficial growth doped single crystal silicon layer; (c) provide support substrate; (d) support substrates and monocrystalline substrate are bonded together the substrate behind the formation bonding; (e) substrate behind the para-linkage carries out the annealing first time; (f) the corrosion monocrystalline substrate is to exposing the doped single crystal silicon layer; (g) substrate behind the para-linkage carries out the annealing second time; The surface of the doped single crystal silicon layer that (h) exposes behind the polishing etch.The invention has the advantages that, utilize spin etching technology to quicken the speed that dopant ion breaks away from the surface, the activity that keeps etchant solution is selected ratio thereby improve etchant solution to the corrosion of different levels of doping monocrystalline silicon, thereby improves the uniformity of SOI substrate top layer silicon thickness.And adopt twice annealed method, guaranteed the firm degree of the interface quality and the bonded interface of spin etching simultaneously.
Description
[technical field]
The present invention relates to the preparation method of integrated circuit material, relate in particular to the preparation method of the silicon substrate on the insulator.
[background technology]
Compare with the body silicon device, silicon-on-insulator (SOI) device has advantages such as high speed, low driving voltage, high temperature resistant, low-power consumption and anti-irradiation, enjoys people's attention, is all obtaining development fast aspect material and the preparation of devices.The SOI material can be divided into thin film SOI (top layer silicon is usually less than 1 μ m) and thick film SOI (top layer silicon is usually greater than 1 μ m) two big classes by the thickness of its top layer silicon thin layer.The application in thin film SOI market 95% concentrates on 8 inches and 12 inches, and wherein most users are the guide of most advanced and sophisticated microelectric technique, as IBM, AMD, Motorola, Intel, UMC, TSMC, OKI etc.Supplier is Japanese SHIN-ETSU HANTOTAI (SEH), French Soitec, Japanese SUMCO at present, and wherein preceding two families have supplied about product more than 90%.The main actuating force in thin film SOI market comes from a high speed, low-power consumption product, particularly microprocessor (CPU) are used.These products with high content of technology, added value is big, is the tap of whole integrated circuit.
Much the report to SOI all concentrates on above these breathtaking most advanced and sophisticated application, and in fact the early stage application of SOI concentrates on Aero-Space and military field, is extended to power and dexterous device and MEMS now and uses.Particularly rapidly in the development of aspects such as automotive electronics, demonstration, wireless telecommunications.Because the control of power supply and conversion, automotive electronics and consumer power device aspect make that to the requirement of adverse circumstances, high temperature, big electric current, high power consumption aspect the strict demand aspect reliability has to adopt the SOI device.Adopt thick film SOI material in these fields more, concentrate on 6 inches and 8 inches, present user comprises U.S. Maxim, ADI, TI (USA), Japanese NEC, Toshiba, Panasonic, Denso, TI (Japan), FUJI, Omron etc., European Philips, X-Fab etc.The characteristics in this field are that the SOI device technology is relatively ripe, and technology content is relatively low, and the profit of device also reduces relatively, to the price comparison sensitivity of SOI material.In these SOI materials user the inside, very big application is mainly derived from the drive circuit in the various application: as the amplifier circuit that is applied to be mainly mobile phone acceptance section of Maxim; Panasonic, TI, FUJI, Toshiba, NEC etc. are mainly used in the scan drive circuit in the display driver circuit; The application of DENSO is mainly at automotive electronics, wireless radio frequency circuit etc.; The application of Toshiba even in the power control circuit of air-conditioning; Omron is mainly aspect transducer; ADI is also mainly at high temperature circuit, transducer etc.; The application of Phillips then mainly is the LDMOS in the power device, is used for consumer electronics such as automobile audio, audio frequency, audio frequency amplifier etc.; The Magnchip of Korea S (Hynix) then is used for display driver circuit that digital camera uses and for the PDP display driver circuit of LG production etc. for Kopin produces.
At present, the technology of preparing of SOI material mainly contain injection oxygen isolation technology (SIMOX), bonding and back side corrosion technology (BESOI) and the smart peeling technology (Smart-cut), epitaxial loayer transfer techniques (ELTRAN) of deriving out etc.Wherein, technology is simple because bonding and back side corrosion technology have, low cost and other advantages, therefore is subject to people's attention, though oxygen buried layer thickness is adjustable continuously, but by the way attenuate top layer silicon of grinding or corroding, the thickness evenness of top layer silicon is difficult to precisely controlled.Is on the basis of 1 ± 0.3 mu m bonded attenuate SOI material as P.B.Mumola etc. at top layer silicon thickness, adopt the special way of computer controlled controlling partially plasma attenuate, top layer silicon is thinned to 0.1 μ m, evenness only can be controlled at ± 0.01 μ m, and this has also just limited bonding and wafer thinning SOI material in the application that the top layer silicon thickness evenness is required aspect high.And the SOI material that adopts the SIMOX technology to prepare, though have excellent top layer silicon thickness evenness, but owing to be subjected to the restriction of implantation dosage and energy, the oxygen buried layer maximum ga(u)ge is difficult to surpass 400nm, and SIMOX technology is to utilize high annealing, promote oxygen to form continuous oxygen buried layer in silicon chip inner gathering nucleation, but the SiO that the pin hole that exists in the oxygen buried layer makes its insulation property form not as thermal oxidation
2, puncture voltage is only about 6MV/cm, these drawbacks limit the application of SIMOX material aspect thick buried regions (greater than 400nm).The Smart-cut technology develops on the basis of bonding techniques, and the thickness of its top layer silicon is determined by hydrionic injection energy, its thickness is adjustable continuously, therefore this technology can satisfy oxygen buried layer thickness and the inhomogeneity requirement of top layer silicon simultaneously, but this technology is peeled off device layer owing to adopt hydrogen ion to inject, so production cost is higher.The epitaxial loayer transfer techniques need be on porous silicon the epitaxy single-crystal silicon layer, defective control difficulty, the prematurity still of this technology, the not report of using.
Above mention, technology is simple because bonding and back side corrosion technology have, low cost and other advantages, but the difficult control of uniformity.Its main starting point is the lightly doped device layer of extension on the heavy doping device substrate, grinds attenuate behind the bonding, utilizes HF, HNO
3And CH
3The hybrid corrosion solution of COOH is mixed the different corrosion rate of layer to weight and is removed heavily doped layer, realizes the transfer of lightly-doped layer, prepares the thick film SOI substrate.The problem that conventional method exists is in the corrosion process that this corrosion is wayward, causes the SOI substrate top layer silicon uniformity prepared relatively poor.
[summary of the invention]
Technical problem to be solved by this invention is, the preparation method of the silicon substrate on a kind of insulator is provided, and can be good at controlling the corrosion of solution to heavily doped layer, reaches higher selection ratio, and the top layer silicon uniformity of the silicon substrate on the insulator of preparing is better.
In order to address the above problem, the invention provides the preparation side of the silicon substrate on a kind of insulator, comprise the steps: that (a) provides monocrystalline substrate, the doping content on the surface of described monocrystalline substrate is D
1(b) at monocrystalline substrate superficial growth doped single crystal silicon layer, described doped single crystal silicon layer has identical dopant with monocrystalline substrate, and the doping content of doped single crystal silicon layer is D
2, D
1Be not equal to D
2(c) provide support substrate, described support substrates surface has insulating barrier; (d) be two relative bonding faces away from the surface of support substrates and doped single crystal silicon layer away from the surface of monocrystalline substrate with insulating barrier, support substrates and monocrystalline substrate are bonded together, form the substrate behind the bonding; (e) substrate behind the para-linkage carries out the annealing first time, and annealing temperature is not higher than 800 ℃; (f) method of employing spin etching makes etchant solution flow through the surface of monocrystalline substrate away from the doped single crystal silicon layer, and the substrate behind the rotation bonding, and the corrosion monocrystalline substrate is to exposing the doped single crystal silicon layer; (g) substrate behind the para-linkage carries out the annealing second time, and annealing temperature is not less than 1000 ℃; The surface of the doped single crystal silicon layer that (h) exposes behind the polishing etch.
As optional technical scheme, described dopant is a boron.
As optional technical scheme, the doping content D of described monocrystalline substrate
1Concentration D greater than the doped single crystal silicon layer
2, the etchant solution of described corrosion monocrystalline substrate is the mixed solution of hydrofluoric acid, nitric acid and acetic acid.
As optional technical scheme, the doping content D of described monocrystalline substrate
1Concentration D less than the doped single crystal silicon layer
2, the etchant solution of described corrosion monocrystalline substrate is the mixed solution of catechol, ethylenediamine and water.
As optional technical scheme, the angular velocity of rotation of described bonding back substrate is 100～5000 weeks of per minute.
The present invention also provides the preparation side of the silicon substrate on a kind of insulator, comprises the steps: that (a) provides monocrystalline substrate; (b) dopant ion is injected monocrystalline substrate, form heavily doped layer and the lightly-doped layer that is positioned at the heavily doped layer surface; (c) provide support substrate, described support substrates surface has insulating barrier; (d) be two relative bonding faces away from the surface of support substrates and lightly-doped layer away from the surface of heavily doped layer with insulating barrier, support substrates and monocrystalline substrate are bonded together, form the substrate behind the bonding; (e) substrate behind the para-linkage carries out the annealing first time, and annealing temperature is not higher than 800 ℃; (f) method of employing spin etching makes first etchant solution flow through the surface of monocrystalline substrate away from the doped single crystal silicon layer, and the substrate behind the rotation bonding, and the corrosion monocrystalline substrate is until exposing heavily doped layer; (g) adopt and the identical method of step (e), use second etchant solution corrosion heavily doped layer, until exposing lightly-doped layer; (h) substrate behind the para-linkage carries out the annealing second time, and annealing temperature is not less than 1000 ℃; (i) surface of the lightly-doped layer that exposes behind the polishing etch; The enforcement order of step (h) and step (i) is commutative.
As optional technical scheme, described dopant is a boron.
As optional technical scheme, described first etchant solution is the mixed solution of catechol, ethylenediamine and water, and second etchant solution is the mixed solution of hydrofluoric acid, nitric acid and acetic acid.
The invention has the advantages that, spin etching technology is introduced in the top layer silicon etching process of preparation of SOI material, the etching process that is adopted combines from stopping technology doped layer with spin etching technology, utilize spin etching technology to quicken the speed that dopant ion breaks away from the surface, the activity that keeps etchant solution, thereby improve etchant solution ratio is selected in the corrosion of different levels of doping monocrystalline silicon, thereby improved the uniformity of SOI substrate top layer silicon thickness.And adopt twice annealed method, before bonding, adopt and be lower than 800 ℃ annealing temperature, guaranteeing under the prerequisite of follow-up spin etching to the requirement of boundary strength, avoided the influence of dopant diffusion corrosion interface, adopt to be higher than 1000 ℃ annealing temperature behind spin etching, the para-linkage interface further reinforces again.
[description of drawings]
Figure 1 shows that the preparation method's of the silicon substrate on the insulator provided by the invention implementation step flow chart of first embodiment;
Accompanying drawing 2 is depicted as the preparation method's of the silicon substrate on the insulator provided by the invention process schematic representation of first embodiment to accompanying drawing 6;
Figure 7 shows that the preparation method's of the silicon substrate on the insulator provided by the invention implementation step flow chart of second embodiment;
Accompanying drawing 8 is depicted as the preparation method's of the silicon substrate on the insulator provided by the invention process schematic representation of second embodiment to accompanying drawing 9.
[embodiment]
Elaborate below in conjunction with preparation method's embodiment of accompanying drawing to the silicon substrate on the insulator provided by the invention.
At first provide the preparation method's of the silicon substrate on the insulator provided by the invention first embodiment.Figure 1 shows that the implementation step flow chart of this embodiment, comprise the steps: step S101, monocrystalline substrate is provided, the doping content on the surface of described monocrystalline substrate is D
1Step S102, at monocrystalline substrate superficial growth doped single crystal silicon layer, described doped single crystal silicon layer has identical dopant with monocrystalline substrate, and the doping content of doped single crystal silicon layer is D
2, D
1Be not equal to D
2Step S103 provides support substrate, and described support substrates surface has insulating barrier; Step S104 is two relative bonding faces away from the surface of support substrates and doped single crystal silicon layer away from the surface of monocrystalline substrate with insulating barrier, and support substrates and monocrystalline substrate are bonded together, and forms the substrate behind the bonding; Step S105, substrate behind the para-linkage carries out the annealing first time, annealing temperature is not higher than 800 ℃ of step S106, adopt the method for spin etching, make etchant solution flow through the surface of monocrystalline substrate away from the doped single crystal silicon layer, and the substrate behind the rotation bonding, the corrosion monocrystalline substrate is to exposing the doped single crystal silicon layer; Step S107, the substrate behind the para-linkage carry out the annealing second time, and annealing temperature is not less than 1000 ℃; Step S108, the surface of the doped single crystal silicon layer that exposes behind the polishing etch.
Accompanying drawing 2 is depicted as the process schematic representation of this embodiment to accompanying drawing 6.
Shown in the accompanying drawing 2, refer step S101 provides monocrystalline substrate 100, and the doping content on the surface of described monocrystalline substrate 100 is D
1Described monocrystalline substrate 100 can be the substrate with unified doping content D1, the one deck that also can be only surface has doping content D1, and this layer with next be monocrystalline silicon with other doping contents or even other doping types, also can be the monocrystalline silicon of intrinsic.
In this embodiment, described dopant is a boron.
Shown in the accompanying drawing 3, refer step S102, at monocrystalline substrate 100 superficial growth doped single crystal silicon layers 110, described doped single crystal silicon layer 110 has identical dopant with monocrystalline substrate 100, and the doping content of doped single crystal silicon layer is D
2, D
1Be not equal to D
2
Doped single crystal silicon layer 110 will be used to form the top silicon layer of silicon-on-insulator substrate in follow-up technology, adopt different doping contents can on the two interface, form the distribution gradient of doping content in doped single crystal silicon layer 110 and monocrystalline substrate 100 surfaces, realize peeling off of substrate so that following adopted is corroded from the method that stops.
Shown in the accompanying drawing 4, refer step S103 provides support substrate 120, and described support substrates 120 surfaces have insulating barrier 130.
Described support substrates 120 can be monocrystalline substrate or other Semiconductor substrate, also can be common backing material in common other semiconductor technologies such as Sapphire Substrate, even also can be the substrate of metal material.The material of insulating barrier 130 can be silica, silicon nitride or silicon oxynitride etc.
Shown in the accompanying drawing 5, refer step S104, is two relative bonding faces away from the surface of support substrates 120 and doped single crystal silicon layer 110 away from the surface of monocrystalline substrate 100 with insulating barrier 130, and support substrates 120 and monocrystalline substrate 100 are bonded together, and forms the substrate 150 behind the bonding.
Described bonding can activate methods such as bonding or conventional hydrophilic bonding by using plasma, reinforces in low temperature behind the bonding, reinforces 400 ℃～800 ℃ of temperature.
Refer step S105, the substrate behind the para-linkage carry out the annealing first time, and annealing temperature is not higher than 800 ℃.
The annealing atmosphere of this step is selected from a kind of in wet oxygen atmosphere, dry oxygen ambient and the nitrogen atmosphere, annealing time 2 hours～4 hours.The purpose of annealing temperature is that the interface of para-linkage reinforces in advance for the first time, to satisfy the requirement of follow-up spin etching to the firm degree in interface.The temperature of annealing is not higher than the diffusion phenomena of doped chemical in 800 ℃ of processes that can be suppressed at annealing, prevent that doped chemical from spreading in substrate, thereby cause the interface of doping content gradient to thicken, to such an extent as to the corrosion interface variation that adopts the spin etching method to obtain.
Refer step S106, the method for employing spin etching makes etchant solution flow through the surface of monocrystalline substrate 100 away from doped single crystal silicon layer 110, and the substrate 150 behind the rotation bonding, and corrosion monocrystalline substrate 100 is to exposing doped single crystal silicon layer 110.Accompanying drawing 6 is depicted as the process schematic representation after corrosion finishes.
Doping content D in described monocrystalline substrate 100
1Doping content D greater than doped single crystal silicon layer 110
2Situation under, the etchant solution of described corrosion monocrystalline substrate is the mixed solution of hydrofluoric acid, nitric acid and acetic acid, HF, HNO in the mixed liquor
3And CH
3The mol ratio of COOH is 1: 3: 8; Doping content D in described monocrystalline substrate 100
1Doping content D less than doped single crystal silicon layer 100
2Situation under, the etchant solution of described corrosion monocrystalline substrate is the mixed solution of catechol, ethylenediamine and water.
Spin etching technology is introduced in the top layer silicon etching process of preparation of SOI material herein, the etching process that is adopted combines from stopping technology doped layer with spin etching technology, utilize spin etching technology to quicken the speed that dopant ion breaks away from the surface, the activity that keeps etchant solution, thereby improve etchant solution ratio is selected in the corrosion of different levels of doping monocrystalline silicon, thereby improved the uniformity of SOI substrate top layer silicon thickness.
The angular velocity of rotation of described bonding back substrate is that 100～5000 weeks of per minute are preferred technical parameters.Less than the underspeed in 100 weeks of per minute so that reacted residual substance promptly breaks away from the surface, make promptly the flow through surface of substrate of corrosive liquid greater than the rotating speed in 5000 weeks, the time of staying on the surface is too short, thereby abundant inadequately with surface generation chemical reaction, therefore caused the waste of corrosive liquid.
Refer step S107, the substrate behind the para-linkage carry out the annealing second time, and annealing temperature is not less than 1000 ℃.
The annealing atmosphere of this step is selected from a kind of in wet oxygen atmosphere, dry oxygen ambient and the nitrogen atmosphere, and annealing time was greater than 3 hours.The purpose of annealing is that the interface behind the para-linkage reinforces further for the second time.Annealing temperature is not less than 1000 ℃ can be impelled and form covalent bond between the bonded interface, has guaranteed the firm degree at interface.This step is carried out after spin etching, therefore can anneal under higher temperature.
Refer step S108, the surface of the doped single crystal silicon layer that exposes behind the polishing etch.Surface after the corrosion still needs further polishing, improves the evenness of top layer silicon surface microscopic, can satisfy the requirement of industry to the SOI substrate.
The enforcement of step S107 and step S108 is independent of each other, and therefore the enforcement of above-mentioned two steps order is commutative.
Next provide the preparation method's of the silicon substrate on the insulator provided by the invention second embodiment.Figure 7 shows that the implementation step flow chart of this embodiment, comprise the steps: step S201, monocrystalline substrate is provided; Step S202 injects monocrystalline substrate with dopant ion, forms heavily doped layer and the lightly-doped layer that is positioned at the heavily doped layer surface; Step S203 provides support substrate, and described support substrates surface has insulating barrier; Step S204 is two relative bonding faces away from the surface of support substrates and lightly-doped layer away from the surface of heavily doped layer with insulating barrier, and support substrates and monocrystalline substrate are bonded together, and forms the substrate behind the bonding; Step S205, the substrate behind the para-linkage carry out the annealing first time, and annealing temperature is not higher than 800 ℃; Step S206,, the method for employing spin etching makes first etchant solution flow through the surface of monocrystalline substrate away from the doped single crystal silicon layer, and the substrate behind the rotation bonding, and the corrosion monocrystalline substrate is until exposing heavily doped layer; Step S207 adopts the method identical with step S206, uses second etchant solution corrosion heavily doped layer, until exposing lightly-doped layer; Step S208, the substrate behind the para-linkage carry out the annealing second time, and annealing temperature is not less than 1000 ℃, step S209, the surface of the lightly-doped layer that exposes behind the polishing etch.
Shown in the accompanying drawing 8, refer step S201 provides monocrystalline substrate 200.
Shown in the accompanying drawing 9, refer step S202 injects monocrystalline substrate 200 with dopant ion, forms heavily doped layer 210 and the lightly-doped layer 220 that is positioned at the heavily doped layer surface.
Lightly-doped layer 220 will be used to form the top silicon layer of SOI material in follow-up technology.The effect of injection technology is the Gradient distribution that forms doping content between the remainder of lightly-doped layer 220 and monocrystalline substrate 200, so that carry out etch stop.
In this embodiment, described dopant is a boron.
The detailed explanation of other steps of this embodiment can repeat no more with reference to content corresponding in the previous embodiment herein.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. the preparation method of the silicon substrate on the insulator is characterized in that, comprises the steps:
(a) provide monocrystalline substrate, the doping content on the surface of described monocrystalline substrate is D
1
(b) at monocrystalline substrate superficial growth doped single crystal silicon layer, described doped single crystal silicon layer has identical dopant with monocrystalline substrate, and the doping content of doped single crystal silicon layer is D
2, D
1Be not equal to D
2
(c) provide support substrate, described support substrates surface has insulating barrier;
(d) be two relative bonding faces away from the surface of support substrates and doped single crystal silicon layer away from the surface of monocrystalline substrate with insulating barrier, support substrates and monocrystalline substrate are bonded together, form the substrate behind the bonding;
(e) substrate behind the para-linkage carries out the annealing first time, and annealing temperature is not higher than 800 ℃;
(f) method of employing spin etching makes etchant solution flow through the surface of monocrystalline substrate away from the doped single crystal silicon layer, and the substrate behind the rotation bonding, and the corrosion monocrystalline substrate is to exposing the doped single crystal silicon layer;
(g) substrate behind the para-linkage carries out the annealing second time, and annealing temperature is not less than 1000 ℃;
The surface of the doped single crystal silicon layer that (h) exposes behind the polishing etch;
The enforcement order of step (g) and step (h) is commutative.
2. the preparation method of the silicon substrate on the insulator according to claim 1 is characterized in that, described dopant is a boron.
3. the preparation method of the silicon substrate on the insulator according to claim 2 is characterized in that, the doping content D of described monocrystalline substrate
1Concentration D greater than the doped single crystal silicon layer
2
4. the preparation method of the silicon substrate on the insulator according to claim 3 is characterized in that, the etchant solution of described corrosion monocrystalline substrate is the mixed solution of hydrofluoric acid, nitric acid and acetic acid.
5. the preparation method of the silicon substrate on the insulator according to claim 2 is characterized in that, the doping content D of described monocrystalline substrate
1Concentration D less than the doped single crystal silicon layer
2
6. the preparation method of the silicon substrate on the insulator according to claim 5 is characterized in that, the etchant solution of described corrosion monocrystalline substrate is the mixed solution of catechol, ethylenediamine and water.
7. the preparation method of the silicon substrate on the insulator according to claim 1 is characterized in that, the angular velocity of rotation of described bonding back substrate is 100～5000 weeks of per minute.
8. the preparation method of the silicon substrate on the insulator is characterized in that, comprises the steps:
(a) provide monocrystalline substrate;
(b) dopant ion is injected monocrystalline substrate, form heavily doped layer and the lightly-doped layer that is positioned at the heavily doped layer surface;
(c) provide support substrate, described support substrates surface has insulating barrier;
(d) be two relative bonding faces away from the surface of support substrates and lightly-doped layer away from the surface of heavily doped layer with insulating barrier, support substrates and monocrystalline substrate are bonded together, form the substrate behind the bonding;
(e) substrate behind the para-linkage carries out the annealing first time, and annealing temperature is not higher than 800 ℃;
(f) method of employing spin etching makes first etchant solution flow through the surface of monocrystalline substrate away from the doped single crystal silicon layer, and the substrate behind the rotation bonding, and the corrosion monocrystalline substrate is until exposing heavily doped layer;
(g) adopt and the identical method of step (e), use second etchant solution corrosion heavily doped layer, until exposing lightly-doped layer;
(h) substrate behind the para-linkage carries out the annealing second time, and annealing temperature is not less than 1000 ℃;
(i) surface of the lightly-doped layer that exposes behind the polishing etch;
The enforcement order of step (h) and step (i) is commutative.
9. the preparation method of the silicon substrate on the insulator according to claim 8 is characterized in that, described dopant is a boron.
10. the preparation method of the silicon substrate on the insulator according to claim 9 is characterized in that, described first etchant solution is the mixed solution of catechol, ethylenediamine and water, and second etchant solution is the mixed solution of hydrofluoric acid, nitric acid and acetic acid.
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| CN101707188B (en) * | 2009-11-27 | 2013-02-20 | 上海新傲科技股份有限公司 | Method for forming underlay with insulating buried layer by adopting etching process |
| FR2955697B1 (en) * | 2010-01-25 | 2012-09-28 | Soitec Silicon Insulator Technologies | METHOD FOR REALIZING A STRUCTURE |
| CN103579103A (en) * | 2013-11-22 | 2014-02-12 | 上海新傲科技股份有限公司 | Three-dimensional lamination packing method and production method of image sensor |
| CN104752308B (en) * | 2013-12-26 | 2017-12-05 | 中国科学院上海微系统与信息技术研究所 | A kind of method that material on insulator is prepared based on Hybrid Heating |
| WO2015109456A1 (en) * | 2014-01-22 | 2015-07-30 | 华为技术有限公司 | Soi substrate manufacturing method and soi substrate |
| CN109786392A (en) * | 2017-11-13 | 2019-05-21 | 丁欣 | Show equipment and its manufacturing method |
| CN108091565B (en) * | 2017-12-13 | 2020-08-25 | 上海华虹宏力半导体制造有限公司 | Rapid thermal annealing method |
| CN110854018A (en) * | 2019-11-28 | 2020-02-28 | 长春长光圆辰微电子技术有限公司 | High-selectivity silicon etching solution and use method thereof |
| CN113889431A (en) * | 2020-07-01 | 2022-01-04 | 中芯集成电路（宁波）有限公司上海分公司 | Method for manufacturing semiconductor-on-insulator structure |
| CN113421849B (en) * | 2021-06-09 | 2023-01-03 | 中环领先半导体材料有限公司 | Preparation process of silicon substrate with insulating buried layer |
| CN114242647B (en) * | 2021-12-08 | 2022-11-18 | 中环领先半导体材料有限公司 | Method for improving thickness uniformity of device silicon layer of silicon wafer on insulator |
| CN117955446A (en) * | 2022-10-21 | 2024-04-30 | 广州乐仪投资有限公司 | Preparation method of semiconductor structure, semiconductor structure and electronic equipment |
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