CN102768981B - With the preparation method of insulating buried layer substrate - Google Patents
With the preparation method of insulating buried layer substrate Download PDFInfo
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- CN102768981B CN102768981B CN201210233324.0A CN201210233324A CN102768981B CN 102768981 B CN102768981 B CN 102768981B CN 201210233324 A CN201210233324 A CN 201210233324A CN 102768981 B CN102768981 B CN 102768981B
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Abstract
The invention provides a kind of preparation method with insulating buried layer substrate, comprise the steps: to provide the support substrates and device substrate with same material; Adopt the surface of single-sided polishing technique polishing support substrates; Insulating barrier is formed at the surface of polished of support substrates and/or a surface of device substrate; Be that support substrates and device substrate are bonded together by intermediate layer with insulating barrier; Grind thinning device substrate; Adopt the polished surface of single-sided polishing technique polishing device substrate, the technological parameter adopted is identical with polishing support substrates surface.The invention has the advantages that, twice glossing adopts identical process conditions, therefore the device substrate surface after polishing should have the surface topography identical with support substrates surface, such device substrate surface coordinates with the pattern on support substrates surface, can ensure that the thickness of device layer is uniform.
Description
Technical field
The present invention relates to field of semiconductor materials, particularly relate to a kind of preparation method with insulating buried layer substrate.
Background technology
Compared with body silicon device, silicon-on-insulator (SOI) device has high speed, low driving voltage, high temperature resistant, the advantage such as low-power consumption and Flouride-resistani acid phesphatase, enjoys the concern of people, is obtained for and develops fast in the preparation of materials and devices.SOI material, by the thickness of its top layer silicon thin layer, can be divided into thin film SOI (top layer silicon is less than 1 μm usually) and the large class of thick film SOI (top layer silicon is greater than 1 μm usually) two.The application in thin film SOI market 95% concentrates on 8 inches and 12 inches, and wherein most user is the guide of most advanced and sophisticated microelectric technique, as IBM, AMD, Motorola, Intel, UMC, TSMC, OKI etc.Current supplier is Japanese SHIN-ETSU HANTOTAI (SEH), French Soitec, Japanese SUMCO, has wherein supplied the about product of more than 90% for first two.The main actuating force in thin film SOI market comes from a high speed, low-power consumption product, particularly microprocessor (CPU) application.These products with high content of technology, added value is large, is the tap of whole integrated circuit.
Much the report of SOI is all concentrated in these breathtaking tip application above, and the application that in fact SOI is early stage concentrates on Aero-Space and military field, is extended to now power and smart material and MEMS and applies.Particularly in automotive electronics, display, wireless telecommunications etc., development is rapid.Because the control of power supply and conversion, automotive electronics and consumer power device aspect are to the requirement of adverse circumstances, high temperature, big current, high power consumption aspect, the strict demand in reliability is made to have to adopt SOI device.At these field many employings thick film SOI materials, concentrate on 6 inches and 8 inches, current user comprises the U.S. Maxim, ADI, TI (USA), Japan NEC, Toshiba, Panasonic, Denso, TI (Japan), FUJI, Omron etc., European Philips, X-Fab etc.The feature in this field is that SOI device technology is relatively ripe, and technology content is relatively low, and the profit of device also reduces relatively, responsive to the price comparison of SOI material.Inside these SOI material users, very large application is mainly derived from the drive circuit in various application: be applied to as Maxim the amplifier circuit being mainly the mobile phone section of acceptance; Panasonic, TI, FUJI, Toshiba, NEC etc. are mainly used in the scan drive circuit in display driver circuit; The application of DENSO is mainly at automotive electronics, wireless radio frequency circuit etc.; The application of Toshiba is even in the power control circuit of air-conditioning; Omron is mainly in transducer; ADI is also main at high temperature circuit, sensor; The application of the Phillips LDMOS then mainly in power device, in consumer electronics as automobile audio, audio frequency, audio frequency amplifier etc.; The Magnchip (Hynix) of Korea S is then for Kopin produces for the display driver circuit of digital camera and the PDP display driver circuit etc. for LG production.
At present, the technology of preparing of SOI material mainly contains injection oxygen isolation technology (SIMOX), bonding and back side corrosion technology (BESOI) and the smart cut technique (Smart-cut) be derived, epitaxial loayer transfer techniques (ELTRAN) etc.Wherein, because bonding and back side corrosion technology have, technique is simple, low cost and other advantages, is therefore subject to people's attention, although oxygen buried layer thickness continuously adjustabe, but by the thinning top layer silicon of the way of grinding or corrode, the thickness evenness of top layer silicon is difficult to precisely controlled.If P.B.Mumola etc. is on the basis that top layer silicon thickness is 1 ± 0.3 mu m bonded thinning SOI material, adopt the special way that computer control local plasma is thinning, top layer silicon is thinned to 0.1 μm, evenness only can control at ± 0.01 μm, and this also just limits the application of bonding and wafer thinning SOI material in high to the requirement of top layer silicon thickness evenness.And the SOI material adopting SIMOX technology to prepare, although have excellent top layer silicon thickness evenness, but owing to being subject to implantation dosage and energy quantitative limitation, oxygen buried layer maximum ga(u)ge is difficult to more than 400nm, and SIMOX technique utilizes high annealing, promote that oxygen forms continuous oxygen buried layer in silicon chip accumulated inside nucleation, but the SiO that the pin hole existed in oxygen buried layer makes its insulation property be formed not as thermal oxidation
2, puncture voltage is about 6MV/cm only, and these shortcomings limit the application of SIMOX material in thick buried regions (being greater than 400nm).Smart-cut technology develops on the basis of bonding techniques, and the thickness of its top layer silicon determined by hydrionic Implantation Energy, its thickness continuously adjustabe, therefore this technology can meet the requirement of oxygen buried layer thickness and top layer silicon uniformity simultaneously, but this technology peels off device layer owing to adopting Hydrogen implantation, and therefore production cost is higher.Epitaxial loayer transfer techniques needs extension monocrystalline silicon layer on porous silicon, powder injection molding difficulty, and this technology is not yet ripe, the report of not application.
Summary of the invention
Technical problem to be solved by this invention is, provides a kind of preparation method with insulating buried layer substrate, can the thickness of control device layer better, thus improves thickness evenness and the yield of whole substrate.
In order to solve the problem, the invention provides a kind of preparation method with insulating buried layer substrate, comprise the steps: to provide the support substrates and device substrate with same material; Adopt the surface of single-sided polishing technique polishing support substrates; Insulating barrier is formed at the surface of polished of support substrates and/or a surface of device substrate; Be that support substrates and device substrate are bonded together by intermediate layer with insulating barrier; Grind thinning device substrate; Adopt the polished surface of single-sided polishing technique polishing device substrate, the technological parameter adopted is identical with polishing support substrates surface.
Optionally, before single-sided polishing support substrates, also comprise step support substrates being implemented to twin polishing; Between the step and the step of single-sided polishing device substrate of the thinning device substrate of grinding, also comprise step support substrates being implemented to twin polishing further; Described twice double-side polishing step also adopts identical technological parameter.
Optionally, between bonding steps and grinding reduction steps, the step that the device substrate after para-linkage carries out chamfered is comprised further.
Optionally, the material of described support substrates and device substrate is monocrystalline silicon.
Optionally, the material of described insulating barrier is selected from any one in silica, silicon nitride and silicon oxynitride.
The invention has the advantages that, twice glossing adopts identical process conditions, therefore the device substrate surface after polishing should have the surface topography identical with support substrates surface, such device substrate surface coordinates with the pattern on support substrates surface, can ensure that the thickness of device layer is uniform.Thickness due to device layer only has several micron even thinner usually, therefore adopts identical glossing to device substrate surface with support substrates surface, can significantly improve the thickness evenness of device layer.
Accompanying drawing explanation
It is the implementation step schematic diagram of the specific embodiment of the invention shown in accompanying drawing 1.
It is the process chart of this embodiment of invention shown in accompanying drawing 2A to accompanying drawing 2F.
Embodiment
Elaborate below in conjunction with the embodiment of accompanying drawing to the preparation method with insulating buried layer substrate provided by the invention.
Be the implementation step schematic diagram of this embodiment shown in accompanying drawing 1, comprise: step S10, the support substrates and device substrate with same material are provided; Step S11, adopts the surface of single-sided polishing technique polishing support substrates; Step S12, forms insulating barrier at the surface of polished of support substrates and/or a surface of device substrate; Step S13 is that support substrates and device substrate are bonded together by intermediate layer with insulating barrier; Step S14, grinds thinning device substrate; Step S15, adopt the polished surface of single-sided polishing technique polishing device substrate, the technological parameter adopted is identical with polishing support substrates surface.
It is the process chart of this embodiment shown in accompanying drawing 2A to accompanying drawing 2F.
Shown in accompanying drawing 2A, refer step S10, provides the support substrates 200 and device substrate 210 with same material.Both materials can be any one the common semi-conducting materials comprising monocrystalline substrate.
Shown in accompanying drawing 2B, refer step S11, adopts the surface of single-sided polishing technique polishing support substrates 200.The object of this step is the total thickness deviation reducing support substrates 200.After single-sided polishing is thrown eventually, support substrates 200 has three kinds of possible thickness distribution: the first is that intermediate thin edge is thick, is similar to the one distribution in the bottom of a pan; The second is thick middle thin edge, is similar to a kind of distribution of back-off pot; The third is flat distribution, and namely polishing rear support substrate 200 surface is flat, and this is a kind of very desirable distribution.Shown in this embodiment accompanying drawing 2B is the first state.As a rule, the thickness of mid portion should be no more than 0.5 μm than thin edge, is generally about 0.2 μm, and accompanying drawing 2B has for the sake of clarity done exaggeration and illustrated, and does not mean that actual substrate has so large thickness deviation after a polish.
Before step S11 implements, step support substrates 200 being implemented to twin polishing can also be selected, to revise the total thickness deviation of support substrates 200 further.
Shown in accompanying drawing 2C, refer step S12, forms insulating barrier 220 at the surface of polished of support substrates 200 and/or a surface of device substrate 210.This embodiment forms insulating barrier 220 at the surface of polished of support substrates 200, and the technique of formation can be chemical vapour deposition (CVD) or thermal oxidation etc., and material can be silica, silicon nitride or silicon oxynitride.Speed due to growth technique is uniform throughout, so the surface topography of insulating barrier 220 has still followed the surface topography of support substrates 200.
Shown in accompanying drawing 2D, refer step S13, is bonded together support substrates 200 and device substrate 210 for intermediate layer with insulating barrier 220.This bonding can be hydrophilic bonding can be also hydrophobic bonding, is optimized for hydrophilic bonding.Now, the hydrophilic bonding of plasma asistance can be selected also can be common hydrophilic bonding.Flatness deviation due to the polished surface of support substrates 200 is only the scope less than 1 micron, and bonded interface itself has certain elasticity, therefore for the device substrate 210 after bonding, we can think that its exposed surface is smooth, can not be subject to the impact of support substrates 200.
Can also select after bonding to implement chamfer angle technique to device substrate 210, the parameter of chamfering is determined by the user of this substrate.
Shown in accompanying drawing 2E, refer step S14, grinds thinning device substrate 210.Milling apparatus is preferably single-sided lapping machine, first roughly grind thinning fast, grinding wheel speed is greater than 2000rpm, fine grinding reduces to grind the damage caused subsequently, grinding wheel speed is greater than 2000rpm, grinding back substrate thickness slightly larger than the target thickness of top layer device layer, should think that the glossing of junior scholar reserves surplus.
Shown in accompanying drawing 2F, refer step S15, adopt the polished surface of single-sided polishing technique polishing device substrate 210, the technological parameter adopted is identical with polishing support substrates 200 surface in step S11, comprises type, concentration and the consumption etc. that adopt identical ramming head pressure, rotary speed, polishing fluid.This step forms final device layer 211 on the surface of insulating barrier 220.Because both adopt identical process conditions, therefore device substrate 210 surface after polishing should have the surface topography identical with support substrates 200 surface, namely should be that intermediate thin edge is thick, is similar to the one distribution in the bottom of a pan.Such device substrate 210 surface coordinates with the pattern on support substrates 200 surface, can ensure that the thickness of device layer 211 is uniform.Thickness due to device layer 211 only has several micron even thinner usually, therefore adopts identical glossing to device substrate 210 surface with support substrates 200 surface, can significantly improve the thickness evenness of device layer 211.
If have selected the step implementing twin polishing before step S11 implements, then preferred before step S15 implements, also select the substrate after para-linkage to implement the step of twin polishing, to revise the total thickness deviation of the substrate after bonding further.And twice double-side polishing step also adopts identical technological parameter, to form the coupling of surface topography, improve the thickness evenness of device layer 211.
Next one embodiment of the present of invention are provided.
Step one: a slice support substrates is provided, Si support substrates is processed, monocrystalline substrate, for 8 cun of substrates, substrate thickness 750 microns, substrate total thickness deviation is less than 4 microns, substrate target thickness is 650 microns, and first grind this monocrystalline substrate thinning, milling apparatus is preferably single-sided lapping machine, first roughly grind thinning fast, grinding wheel speed is greater than 2000rpm, and fine grinding reduces to grind the damage caused subsequently, and grinding wheel speed is greater than 2000rpm, grinding back substrate thickness is greater than target thickness more than 3 microns, is thinned to 665 microns here.
Step 2: carry out polishing to the support substrates after grinding can be twin polishing also can be single-sided polishing, and also can be two-sided+single-sided polishing, be two-sided+single-sided polishing here.First twin polishing, whole polishing process is divided into two steps, first rough polishing, subsequently finishing polish, and in two throwing process, total polishing removal amount is no less than 2 microns; Adopt single-sided polishing accurately to control silicon wafer thickness subsequently, whole polishing process is divided into rough polishing and finishing polish two step equally, and polishing removal amount is not more than 4 microns, and after revising, substrate total thickness deviation is less than 1 micron.After single-sided polishing is thrown eventually, support substrates presents intermediate thin, the distribution that edge is thick, and be similar to the one distribution in the bottom of a pan, intermediate epitaxial layers thickness than thin edge 0-0.5 μm, should be generally 0.2 μm.
Step 3: to support substrates or device substrate, or all insulating process is carried out to the two, can be oxidation technology, can be PECVD or LPCVD deposition insulating layer, and dielectric can be silicon dioxide also can be silicon nitride.Optimization Technology is the thermal oxidation technology of standard, and oxidizing condition can wet oxygen also can be dry oxygen, and oxidation technology depends on the oxidated layer thickness of needs, and temperature is 900-1400 DEG C, wet-oxygen oxidation, and oxidated layer thickness need determine according to the thickness of final SOI.
Step 4: the support substrates after oxidation and the device substrate bonding delayed outward, this bonding can be hydrophilic bonding can be also hydrophobic bonding, is optimized for hydrophilic bonding.Now, the hydrophilic bonding of plasma asistance can be selected also can be common hydrophilic bonding.If using plasma assists hydrophilic bonding, first Ar or N2 or O2 ion pair surface is adopted to process, carry out annealing subsequently to reinforce, annealing temperature is 50-700 DEG C, be optimized for 300 DEG C, annealing time be 10 min by 10 hours, be optimized for 2.5 hours, annealing atmosphere is oxygen, argon gas, nitrogen or its mist.If adopt traditional hydrophilic or hydrophobic bonding, reinforcing temperature is 800-1400 DEG C, and annealing time is 0.5-10 hour, and annealing atmosphere is oxygen, argon gas, nitrogen or its mist.
Step 5: to the substrate after reinforcing to carrying out chamfered, chamfering width is determined by customer specifications.The remaining silicon layer thickness of grinding back edge is 0-150 micron.Substrate after chamfering is corroded in TMAH solution, removes the remaining silicon layer in 100 microns of edges.The way optimized is the way adopting spin etching, sprays TMAH corrosive liquid, and in corrosion process, substrate is to rotating, and rotating speed is 100-10000rpm, is optimized for 1000rpm, and TMAH temperature optimization is 95 DEG C.
Step 6: grind thinning device substrate, milling apparatus is preferably single-sided lapping machine, first roughly grind thinning fast, grinding wheel speed is greater than 2000rpm, fine grinding reduces to grind the damage caused subsequently, grinding wheel speed is greater than 2000rpm, and grinding back substrate thickness is greater than prepared SOI top material layer silicon target thickness more than 3 microns, and being thinned to excess silicon layer thickness is here 18 microns.It is the same that the distribution of thinning rear remaining silicon layer thickness also should be similar to support substrates, presents the distribution that a kind of intermediate thin edge is thick.
Step 7: carry out polishing to the device substrate after grinding can be twin polishing also can be single-sided polishing, also can be two-sided+single-sided polishing, be optimized for two-sided+single-sided polishing here.First twin polishing, whole polishing process is divided into two steps, first rough polishing, subsequently finishing polish, and in two throwing process, total polishing removal amount is no less than 2 microns; Adopt single-sided polishing accurately to control silicon wafer thickness subsequently, whole polishing process is divided into rough polishing and finishing polish two step equally, and polishing removal amount is not more than 6 microns.Adopt in single side polishing machine polishing process with before identical setting parameter, require that its final thickness is distributed as recessed.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. with a preparation method for insulating buried layer substrate, it is characterized in that, comprise the steps: to provide the support substrates and device substrate with same material; Adopt the surface of single-sided polishing technique polishing support substrates; Insulating barrier is formed at the surface of polished of support substrates and/or a surface of device substrate; Be that support substrates and device substrate are bonded together by intermediate layer with insulating barrier; Grind thinning device substrate; Adopt the polished surface of single-sided polishing technique polishing device substrate, the technological parameter adopted is identical with polishing support substrates surface, has the surface topography identical with the support substrates surface after polishing to make the device substrate surface after polishing.
2. according to the method described in claim 1, it is characterized in that, before single-sided polishing support substrates, also comprise step support substrates being implemented to twin polishing; Between the step and the step of single-sided polishing device substrate of the thinning device substrate of grinding, also comprise the step that the substrate after para-linkage implements twin polishing further.
3. according to the method described in claim 2, it is characterized in that, described twice double-side polishing step also adopts identical technological parameter.
4. according to the method described in claim 1, it is characterized in that, between bonding steps and grinding reduction steps, comprise the step that the device substrate after para-linkage carries out chamfered further.
5. according to the method described in claim 1, it is characterized in that, the material of described support substrates and device substrate is monocrystalline silicon.
6., according to the method described in claim 1, it is characterized in that, the material of described insulating barrier be selected from silica, silicon nitride and silicon oxynitride any one.
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| CN102983074B (en) * | 2012-11-30 | 2015-10-14 | 上海新傲科技股份有限公司 | The method of thinning device layer and the preparation method of substrate |
| CN103560105A (en) * | 2013-11-22 | 2014-02-05 | 上海新傲科技股份有限公司 | Method for manufacturing semiconductor substrate with smooth edge |
| CN106847846A (en) * | 2016-12-23 | 2017-06-13 | 江苏正桥影像科技股份有限公司 | A kind of grinding method of ultra-thin image sensor wafer |
| CN110010458B (en) * | 2019-04-01 | 2021-08-27 | 徐州鑫晶半导体科技有限公司 | Method for controlling surface morphology of semiconductor wafer and semiconductor wafer |
| CN113601376A (en) * | 2021-08-10 | 2021-11-05 | 山西烁科晶体有限公司 | Method for measuring single-side polishing rate in silicon carbide double-side polishing |
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| US6090688A (en) * | 1996-11-15 | 2000-07-18 | Komatsu Electronic Metals Co., Ltd. | Method for fabricating an SOI substrate |
| CN101609800A (en) * | 2009-06-19 | 2009-12-23 | 上海新傲科技股份有限公司 | A kind of method for preparing the crystallographic orientation semiconductor substrate |
| CN101901753A (en) * | 2010-06-25 | 2010-12-01 | 上海新傲科技股份有限公司 | Method for preparing thick-film material with insulating embedded layer |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6090688A (en) * | 1996-11-15 | 2000-07-18 | Komatsu Electronic Metals Co., Ltd. | Method for fabricating an SOI substrate |
| CN101609800A (en) * | 2009-06-19 | 2009-12-23 | 上海新傲科技股份有限公司 | A kind of method for preparing the crystallographic orientation semiconductor substrate |
| CN101901753A (en) * | 2010-06-25 | 2010-12-01 | 上海新傲科技股份有限公司 | Method for preparing thick-film material with insulating embedded layer |
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