CN102437047B - Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method - Google Patents
Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method Download PDFInfo
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- CN102437047B CN102437047B CN201110250266.8A CN201110250266A CN102437047B CN 102437047 B CN102437047 B CN 102437047B CN 201110250266 A CN201110250266 A CN 201110250266A CN 102437047 B CN102437047 B CN 102437047B
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Abstract
The invention discloses a shallow trench isolation (STI)-chemical mechanical polishing (CMP) method for a silicon oxide/silicon nitride double inner wall protection layer and a method for manufacturing an STI structure by the STI-CMP method. Grinding liquid with higher grinding speed ratio of the silicon oxide to the silicon nitride is used for removing a trench silicon dioxide filling layer, the operation is stopped on a silicon nitride protection layer, then, grinding liquid with a higher grinding speed ratio of the silicon nitride to the silicon oxide is used for grinding the silicon nitride protection layer, after the silicon nitride protection layer is completely removed, the original grinding liquid with the higher grinding speed ratio of the silicon oxide to the silicon nitride is used for grinding a silicon dioxide protection layer, and finally, the operation is stopped on a silicon nitride blocking layer. Therefore, the wet etching step for additionally removing the silicon nitride protection layer and the silicon dioxide protection layer in the traditional STI manufacture method is avoided, the process complexity is reduced, and the flatness of the wafer surface is favorably improved.
Description
Technical field
The present invention relates to a kind of production process of electronic elements, relate in particular to a kind of cmp method for the two inner wall protection layer fleet plough groove isolation structure of silica/silicon nitride and adopt described method to make the method for described fleet plough groove isolation structure.
Background technology
In semiconductor fabrication process, shallow trench isolation is widely used as a kind of device separation from (Shallow Trench Isolation, or STI) technology.As shown in Figure 1; common STI technological process is: first deposit one deck silica (pad oxide) and silicon nitride (pad nitride) successively on silicon substrate (substrate) 1; wherein silicon oxide layer is as the protective layer of silicon substrate, and (Fig. 1 a) as the barrier layer of subsequent etching and CMP (Chemical Mechanical Polishing) process for silicon nitride.Successively by photoetching and etching, (Fig. 1 b) on silicon substrate, to form needed shallow trench afterwards.The degree of depth of general groove is between 300 ~ 700nm.Then at the inwall of groove with thermal oxidation method growth layer of silicon dioxide protective layer (liner oxide), damage substrate being caused to repair etching, and wedge angle sphering (corner rounding) to channel bottom (Fig. 1 c).Again using chemical gas-phase method deposit (chemical vapor deposition or CVD) silicon dioxide as filling trench isolation.Due to the characteristic of chemical gas-phase method, also can at the silicon dioxide layer of the suitable thickness of surface deposition of silicon nitride barrier, (Fig. 1 d) in groove deposit silicon dioxide, finally need to grind by chemico-mechanical polishing (Chemical-mechanical polishing or CMP) technology the silicon dioxide of removing in silicon nitride surface deposit, and stop on silicon nitride barrier, (Fig. 1 e) finally to form a smooth surface at wafer.Finally by wet etching, the silicon dioxide of silicon nitride and silicon nitride lower floor is removed again, exposed surface of silicon.So far, isolation shallow trench is completed into.
Although traditional STI technology can improve performance and the integrated level of device, in manufacture process, also produce many problems.One of them is isolated groove marginal trough (divot) phenomenon.This phenomenon is to remove in the process of silicon dioxide of silicon nitride and silicon nitride lower floor at wet etching, because the local stress of the silicon dioxide at shallow trench edge is different with material, and wet processing has isotropic characteristics and different silicon dioxide is had different etch rates and caused.Isolated groove marginal trough phenomenon can cause a lot of negative effects to device, and as gate voltage reduces, electric leakage increases etc.
A kind of current method of eliminating or improving isolated groove marginal trough phenomenon is that trench wall is adopted to two protective layers; first use thermal oxidation method at trench wall growth one deck silica protective layer; follow deposit one deck silicon nitride protective layer again, form the two protective layers (oxide/nitride double liner) of silica/silicon nitride.This method can be in the upper three-layer thin-film structure that forms the silica-filled layer of silica protective layer (liner oxide), silicon nitride protective layer (liner nitride) and groove of silicon nitride barrier (pad nitride).This structure is brought very large challenge to STI-CMP technique.This is because STI-CMP technique is the flatness that reaches higher and protects substrate below conventionally; all adopt the lapping liquid with the grinding rate ratio of higher silica to silicon nitride, grinding can stop on silicon nitride barrier (pad nitride) like this.
For this trilamellar membrane structure; common STI-CMP grinds while end and can be parked on silicon nitride (liner nitride) protective layer; thereby need extra wet process steps to remove successively silicon nitride protective layer; silica protective layer; and silicon nitride barrier and silica barrier layer; increase process complexity, be unfavorable for again the flatness of crystal column surface.
Summary of the invention
The present invention proposes a kind of CMP method, the lapping liquid that use has the grinding rate ratio of higher silica to silicon nitride grinds the silica-filled layer of removal groove and is parked on silicon nitride protective layer (liner nitride), then with thering is the lapping liquid polishing silicon nitride protective layer (liner nitride) of higher silicon nitride to silica grinding rate ratio, removing silicon nitride protective layer (liner nitride) completely afterwards, re-use the original lapping liquid abrasive silica protective layer (liner oxide) with the grinding rate ratio of higher silica to silicon nitride, finally rest on silicon nitride barrier (pad nitride).
The invention provides a kind of cmp method for the two inner wall protection layer shallow ditch groove structure of silica/silicon nitride, it is characterized in that, step comprises:
Step 1, use the lapping liquid with the grinding rate ratio of higher silica to silicon nitride to grind the silica-filled layer of groove, and grinding stops on silicon nitride protective layer; The grinding rate ratio of described higher silica to silicon nitride, refers to silica silicon nitride grinding rate ratio is greater than to 1.
Step 2, use has higher silicon nitride grinds silicon nitride protective layer layer the lapping liquid of silica grinding rate ratio, and grinding stops on silica protective layer; Described have higher silicon nitride to refer to silicon nitride to silica grinding rate ratio silica grinding rate ratio is greater than to 1
Step 3, reuses the abrasive silica of lapping liquid described in step 1 protective layer, and finally stops on silicon nitride barrier;
Step 4, removes silicon nitride and the silicon dioxide layer of protection on shallow trench outer-lining bottom surface.
CMP method of the present invention is applicable to the CMP (Chemical Mechanical Polishing) process (STI-CMP) of the shallow trench of the two inner wall protection layers (oxide/nitride double liner) of silica/silicon nitride, can overcome traditional STI-CMP technique and in the time grinding the two inner wall protection layer shallow trench of silica/silicon nitride, grind the problem less than silicon nitride barrier.
The present invention also provides a kind of sti structure manufacture method, and step comprises:
Step 1, deposit silicon dioxide barrier layer and silicon nitride barrier successively on silicon substrate;
Step 2 by photoetching and etching, defines shallow channel isolation area on described silicon substrate;
Step 3, at described shallow trench successively deposit silicon dioxide layer of protection and silicon nitride protective layer, forms two inner wall protection layers;
Step 4, substrate surface silicon oxide deposition packed layer around shallow trench and shallow trench;
Step 5, barrier layer and protective layer are removed in chemico-mechanical polishing, and concrete steps comprise:
Step 5.1, use silica the silica-filled layer of groove to be ground than the lapping liquid that is greater than 1 silicon nitride grinding rate, and grinding stops on silicon nitride protective layer;
Step 5.2, use silicon nitride silicon nitride protective layer layer to be ground than the lapping liquid that is greater than 1 silica grinding rate, and grinding stops on silica protective layer;
Step 5.3, reuses the abrasive silica of lapping liquid described in step 5.1 protective layer, and finally stops on silicon nitride barrier;
Step 5.4, removes silicon nitride and the silicon dioxide layer of protection on shallow trench outer-lining bottom surface.
In the above-mentioned method of the present invention, described silica is one or both the mixing in silicon dioxide or ceria to silicon nitride grinding rate than the lapping liquid abrasive material that is greater than 1; But this lapping liquid can be also other silica to silicon nitride grinding rate than the lapping liquid that is greater than 1.
In the above-mentioned method of the present invention, described silicon nitride is hot phosphoric acid to silica grinding rate than the lapping liquid that is greater than 1, but can be also other silicon nitrides to silica grinding rate than the lapping liquid that is greater than 1.
In the above-mentioned method of the present invention, removing the silicon nitride on shallow trench outer-lining bottom surface and the method for silicon dioxide layer of protection is wet etching.
The above-mentioned CMP (Chemical Mechanical Polishing) process of the present invention can be carried out on same abrasive disk, realizes multistep polishing by switching lapping liquid; Also can on two of same CMP board ~ tri-abrasive disks, carry out successively multistep polishing.
CMP method provided by the invention and STI manufacture method, avoided removal silicon nitride protective layer extra in conventional art and the wet process steps of silica protective layer, reduced process complexity, and be conducive to improve the flatness of crystal column surface.
Brief description of the drawings
Fig. 1 is traditional sti structure manufacture method flow chart, wherein:
Fig. 1 a is silicon oxide deposition and silicon nitride barrier successively on silicon substrate;
Fig. 1 b for defining STI isolated area on silicon substrate;
Fig. 1 c is the silicon dioxide layer of protection successively of growing at STI inwall;
Fig. 1 d is that silica is filled in deposit isolation;
Fig. 1 e is the silicon dioxide of removing silicon nitride barrier surface;
Fig. 2 is the two inner wall protection layer STI-CMP process charts of silica/silicon nitride of the present invention, wherein:
Fig. 2 a is STI inwall silicon oxide deposition and silicon nitride protective layer;
Fig. 2 b is that silicon dioxide is filled in deposit isolation;
Fig. 2 c is that CMP removes filling silicon dioxide, stops on silicon nitride protective layer;
Fig. 2 d is that CMP removes silicon nitride protective layer, stops on silica protective layer;
Fig. 2 e is that CMP removes silica protective layer, stops in silicon nitride barrier.
Embodiment
The invention provides a kind of cmp method for the two inner wall protection layer shallow ditch groove structure of silica/silicon nitride, and a kind of use method that described method is made sti structure is provided.Below with reference to specific embodiment, the method for the invention described in detail and describe, so that better understand the present invention, but following embodiment does not limit the scope of the invention.
embodiment 1
See figures.1.and.2, sti structure manufacture method of the present invention and CMP method step comprise:
Step 1, deposit silicon dioxide barrier layer 2 and silicon nitride barrier 3 successively on silicon substrate 1; Concrete deposition process can be implemented with reference to prior art, as patent CN1138872C, document " technique of photo-CVD silicon nitride and application study thereof " (microelectronics and computer, 1995(3): 45).
Step 2 by photoetching and etching, defines shallow channel isolation area 10 on described silicon substrate, and concrete grammar can be implemented with reference to prior art, method as disclosed in patent CN101447424B.
Step 3, at described shallow trench successively deposit silicon dioxide layer of protection 4 and silicon nitride protective layer 6, forms two inner wall protection layers;
Step 4, substrate surface silicon oxide deposition packed layer 5 around shallow trench and shallow trench;
Step 5, barrier layer and protective layer are removed in chemico-mechanical polishing;
Step 5.1, on abrasive disk, use abrasive silica lapping liquid to grind the silica-filled layer of groove, and grinding stops on silicon nitride protective layer; Described abrasive silica grinding agent to silica grinding rate to being greater than silicon nitride grinding rate;
Step 5.2, switches lapping liquid, uses hot phosphoric acid lapping liquid to grind silicon nitride protective layer on same abrasive disk, and grinding stops on silica protective layer; Described hot phosphoric acid is greater than silica grinding rate silicon nitride grinding rate;
Step 5.3, reuses the abrasive silica of lapping liquid described in step 5.1 protective layer, and finally stops on silicon nitride barrier;
Step 5.4, wet etching is removed silicon nitride and the silicon dioxide layer of protection on shallow trench outer-lining bottom surface.
embodiment 2
See figures.1.and.2, sti structure manufacture method of the present invention and CMP method step comprise:
Step 1, deposit silicon dioxide barrier layer 2 and silicon nitride barrier 3 successively on silicon substrate 1; Concrete deposition process can be implemented with reference to prior art, as patent CN1138872C, document " technique of photo-CVD silicon nitride and application study thereof " (microelectronics and computer, 1995(3): 45).
Step 2 by photoetching and etching, defines shallow channel isolation area 10 on described silicon substrate, and concrete grammar can be implemented with reference to prior art, method as disclosed in patent CN101447424B.
Step 3, at described shallow trench successively deposit silicon dioxide layer of protection 4 and silicon nitride protective layer 6, forms two inner wall protection layers;
Step 4, substrate surface silicon oxide deposition packed layer 5 around shallow trench and shallow trench;
Step 5, barrier layer and protective layer are removed in chemico-mechanical polishing;
Step 5.1, on abrasive disk, use ceria lapping fluid to grind the silica-filled layer of groove, and grinding stops on silicon nitride protective layer; Described abrasive silica grinding agent to silica grinding rate to being greater than silicon nitride grinding rate;
Step 5.2, switches lapping liquid, uses hot phosphoric acid lapping liquid to grind silicon nitride protective layer on same abrasive disk, and grinding stops on silica protective layer; Described hot phosphoric acid is greater than silica grinding rate silicon nitride grinding rate;
Step 5.3, reuses the abrasive silica of lapping liquid described in step 5.1 protective layer, and finally stops on silicon nitride barrier;
Step 5.4, wet etching is removed silicon nitride and the silicon dioxide layer of protection on shallow trench outer-lining bottom surface.
embodiment 3
See figures.1.and.2, sti structure manufacture method of the present invention and CMP method step comprise:
Step 1, deposit silicon dioxide barrier layer 2 and silicon nitride barrier 3 successively on silicon substrate 1; Concrete deposition process can be implemented with reference to prior art, as patent CN1138872C, document " technique of photo-CVD silicon nitride and application study thereof " (microelectronics and computer, 1995(3): 45).
Step 2 by photoetching and etching, defines shallow channel isolation area 10 on described silicon substrate, and concrete grammar can be implemented with reference to prior art, method as disclosed in patent CN101447424B.
Step 3, at described shallow trench successively deposit silicon dioxide layer of protection 4 and silicon nitride protective layer 6, forms two inner wall protection layers;
Step 4, substrate surface silicon oxide deposition packed layer 5 around shallow trench and shallow trench;
Step 5, barrier layer and protective layer are removed in chemico-mechanical polishing;
Step 5.1, on abrasive disk, use ceria lapping fluid to grind the silica-filled layer of groove, and grinding stops on silicon nitride protective layer; Described abrasive silica grinding agent to silica grinding rate to being greater than silicon nitride grinding rate;
Step 5.2, moves to another abrasive disk, uses hot phosphoric acid lapping liquid to grind silicon nitride protective layer, and grinding stops on silica protective layer; Described hot phosphoric acid is greater than silica grinding rate silicon nitride grinding rate;
Step 5.3, moves in the 3rd abrasive disk or step 2.1 on abrasive disk, reuses the abrasive silica of lapping liquid described in step 5.1 protective layer, and finally stops on silicon nitride barrier;
Step 5.4, wet etching is removed silicon nitride and the silicon dioxide layer of protection on shallow trench outer-lining bottom surface.
STI-CMP method for the two inner wall protection layers (oxide/nitride double liner) of silica/silicon nitride disclosed by the invention and adopt described method to make the method for sti structure; the lapping liquid by use with the grinding rate ratio of different silica to silicon nitride is removed silica-filled layer successively; silicon nitride protective layer (liner nitride) and silica protective layer (liner oxide), be finally parked in silicon nitride barrier (pad nitride).Thereby the wet process steps of having avoided extra removal liner nitride and liner oxide, has reduced process complexity, and has been conducive to improve the flatness of crystal column surface.
Above specific embodiments of the invention be have been described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and alternative also all among category of the present invention.Therefore, equalization conversion and the amendment done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.
Claims (4)
1. a manufacturing method of shallow trench structure, is characterized in that, step comprises:
Step 1, deposit silicon dioxide barrier layer and silicon nitride barrier successively on silicon substrate;
Step 2 by photoetching and etching, defines shallow channel isolation area on described silicon substrate;
Step 3, substrate surface deposit silicon dioxide layer of protection and silicon nitride protective layer successively around described shallow trench and shallow trench, forms two inner wall protection layers;
Step 4, the silica-filled layer of substrate surface deposit around shallow trench and shallow trench;
Step 5, protective layer is removed in chemico-mechanical polishing, then removes barrier layer, and concrete steps comprise:
Step 5.1, use silicon dioxide the silica-filled layer of groove to be ground than the lapping liquid that is greater than 1 silicon nitride grinding rate, and grinding stops on silicon nitride protective layer;
Step 5.2, use silicon nitride silicon nitride protective layer to be ground than the lapping liquid that is greater than 1 silicon dioxide grinding rate, and grinding stops on silicon dioxide layer of protection;
Step 5.3, reuses the abrasive silica of lapping liquid described in step 5.1 protective layer, and finally stops on silicon nitride barrier;
Step 5.4, silicon nitride and the silicon dioxide barrier layer on removal shallow trench outer-lining bottom surface.
2. manufacturing method of shallow trench structure according to claim 1, is characterized in that, the abrasive material of lapping liquid described in step 5.1 is one or both the mixing in silicon dioxide, ceria.
3. manufacturing method of shallow trench structure according to claim 1, is characterized in that, lapping liquid described in step 5.2 is hot phosphoric acid.
4. manufacturing method of shallow trench structure according to claim 1, is characterized in that, the method for removing described silicon nitride and silicon dioxide barrier layer in step 5.4 is wet etching.
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| CN102814727B (en) * | 2012-08-13 | 2015-05-06 | 无锡华润上华科技有限公司 | Method for chemically and mechanically grinding shallow trench isolation structure |
| CN104347413B (en) * | 2013-08-02 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of method making FinFET semiconductor device |
| CN104517884B (en) * | 2013-09-27 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | A kind of method for making semiconductor devices |
| CN105702573B (en) * | 2014-11-27 | 2019-03-26 | 联华电子股份有限公司 | The method for planarizing semiconductor device |
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| US5976951A (en) * | 1998-06-30 | 1999-11-02 | United Microelectronics Corp. | Method for preventing oxide recess formation in a shallow trench isolation |
| CN1540741A (en) * | 2003-04-24 | 2004-10-27 | 台湾积体电路制造股份有限公司 | Method for making shallow trench isolation even |
| US7294575B2 (en) * | 2004-01-05 | 2007-11-13 | United Microelectronics Corp. | Chemical mechanical polishing process for forming shallow trench isolation structure |
| CN101154618A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming device isolation region |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20050067487A (en) * | 2003-12-29 | 2005-07-04 | 주식회사 하이닉스반도체 | Shallow trench isolation method of semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5976951A (en) * | 1998-06-30 | 1999-11-02 | United Microelectronics Corp. | Method for preventing oxide recess formation in a shallow trench isolation |
| CN1540741A (en) * | 2003-04-24 | 2004-10-27 | 台湾积体电路制造股份有限公司 | Method for making shallow trench isolation even |
| US7294575B2 (en) * | 2004-01-05 | 2007-11-13 | United Microelectronics Corp. | Chemical mechanical polishing process for forming shallow trench isolation structure |
| CN101154618A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming device isolation region |
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