CN110391184B - Method for manufacturing zero-layer interlayer film - Google Patents
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- CN110391184B CN110391184B CN201910670179.4A CN201910670179A CN110391184B CN 110391184 B CN110391184 B CN 110391184B CN 201910670179 A CN201910670179 A CN 201910670179A CN 110391184 B CN110391184 B CN 110391184B
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- 239000010410 layer Substances 0.000 title claims abstract description 141
- 239000011229 interlayer Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 73
- 229920005591 polysilicon Polymers 0.000 claims abstract description 73
- 238000005498 polishing Methods 0.000 claims abstract description 60
- 238000005530 etching Methods 0.000 claims abstract description 53
- 239000000126 substance Substances 0.000 claims abstract description 42
- 150000004767 nitrides Chemical class 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000000227 grinding Methods 0.000 abstract description 13
- 230000007547 defect Effects 0.000 abstract description 11
- 238000010586 diagram Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
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- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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Abstract
The invention discloses a manufacturing method of a zeroth interlayer film, which comprises the following steps: step one, forming a first grid structure on the surface of a semiconductor substrate; the area between the first grid structures is a spacer area; forming a side wall and forming a contact hole etching stop layer consisting of a nitride film; growing a zero-layer interlayer film; step three, carrying out first selective chemical mechanical polishing to polish the zero interlayer film and stopping on the contact hole etching stop layer on the top surface of the side wall; step four, carrying out second non-selective chemical mechanical grinding to grind the oxide film and the nitride film simultaneously and stop on the contact hole etching stop layer on the top surface of the polysilicon gate; and fifthly, carrying out third selective etching to remove the residual contact hole etching stop layer on the top surface of the polysilicon gate. The invention can eliminate the butterfly defect of the zero-layer interlayer film and improve the product yield.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a zeroth interlayer film.
Background
In the current advanced logic chip process, a plurality of device units are integrated on the same semiconductor substrate wafer, the gate structures of the device units comprise polysilicon gates, the distances between the polysilicon gates are not completely the same but have various distance values, and the interval regions between the polysilicon gates are often filled with the zero-level interlayer film (ILD 0). And when the growth of the film between the zeroth layers is finished, the film between the zeroth layers also extends to the top area of the polysilicon gate outside the interval area, and then the film between the zeroth layers of the polysilicon gate top area outside the interval area is removed by adopting a Chemical Mechanical Polishing (CMP) process and the film between the zeroth layers of the interval area is polished to be level to the top surface of the polysilicon gate.
As shown in fig. 1A to 1E, the device structure diagram in each step of the conventional method for manufacturing the zeroth interlayer film is shown, and the conventional method for manufacturing the zeroth interlayer film includes the following steps:
step one, as shown in fig. 1A, providing a semiconductor substrate 101, and forming a plurality of first gate structures formed by overlapping gate dielectric layers and polysilicon gates 103 on the surface of the semiconductor substrate 101; the area between each of the first gate structures is a spacer 205.
And forming a side wall 104 on the side surface of the first gate structure, wherein the top surface of the side wall 104 is higher than the top surface of the polysilicon gate 103.
Forming a contact hole etching stop layer 105 composed of a nitride film, wherein the contact hole etching stop layer 105 covers the surface of the polysilicon gate 103 at the top of the first gate structure, the top surface and the inner and outer side surfaces of the side wall 104 and the surface of the semiconductor substrate 101 of the spacer 205. As shown in fig. 1A, the inner side surface of the inner and outer side surfaces of the sidewall 104 refers to a side surface of the sidewall 104 extending to the top of the polysilicon gate 103, which is close to the polysilicon gate 103, and the outer side surface of the inner and outer side surfaces of the sidewall 104 refers to a side surface of the sidewall 104, which is far from the polysilicon gate 103.
Generally, the sub-steps of forming the first gate structure include:
and 11, sequentially forming the gate dielectric layer (not shown) and the polysilicon gate 103 on the surface of the semiconductor substrate 101.
The semiconductor substrate 101 is a silicon substrate.
The gate dielectric layer is made of an oxide layer; or, the gate dielectric layer is made of a high dielectric constant material.
Step 12, forming a hard mask layer (not shown) on the surface of the polysilicon gate 103. The hard mask layer is made of an oxide layer or a nitride film.
And step 13, performing photoetching to form a plurality of first gate structures, wherein the hard mask layer is superposed on the top of the polysilicon gate 103 of each first gate structure.
The sub-steps of forming the first gate structure further include:
the material of the sidewall spacers 104 includes an oxide layer or a nitride film. After the side wall 104 is formed on the side surface of the first gate structure, the method further includes the step of removing the hard mask layer on the top of the polysilicon gate 103, so that the top surface of the side wall 104 is higher than the top surface of the polysilicon gate 103.
A field oxide layer 102 is formed on a semiconductor substrate 101, and the field oxide layer 102 is typically formed using a Shallow Trench Isolation (STI) process. The field oxide layer 102 isolates an active area, the active area includes an active area of a Core (Core) area and an active area of an input/output (IO) area, a Core device is formed in the active area of the Core area, and an input/output device is formed in the active area of the input/output area; shown in FIG. 1A are a core nFET201, a core pFET202, an input output nFET203, and an input output pFET 204. The width of the first gate structure in step one includes a plurality of, for example, the width of the first gate structure in the active area of the input-output region, i.e., input-output nFET203 and input-output pFET204, is greater than the width of the first gate structure in the active area of the core region, i.e., core nFET201 and core pFET 202. The size of the space between the first gate structures, i.e., the width of the spacer 205, includes a plurality of spaces, for example, the space between the first gate structures in the active region of the input/output region is larger than the space between the first gate structures in the active region of the core region.
And a step of forming a source region and a drain region on the surface of the semiconductor substrate 101 on two sides of the first gate structure is further included before the second step. When the source region or the drain region is formed, a step of forming a silicon germanium layer 106 in a formation region of the source region or the drain region is further included. In fig. 1A, only the ge-si layer 106 is shown to be formed in the drain region of the core pFET202, and the ge-si layer 106 can provide stress to the channel region of the device, which is beneficial for improving the performance of the device.
Step two, as shown in fig. 1B, growing a zero interlayer film 107, where the zero interlayer film 107 is an oxide film, the zero interlayer film 107 is formed on the surface of the contact hole etching stop layer 105, and the zero interlayer film 107 fills and extends the spacer 205 to the top of the first gate structure.
Generally, the zero-layer interlayer film 107 is grown using a High Aspect Ratio Process (HARP) process.
Step three, as shown in fig. 1C, performing a first selective chemical mechanical polishing, where a polishing rate of the first selective chemical mechanical polishing to the oxide film is greater than a polishing rate to the nitride film, such as 20: 1, the first selective chemical mechanical polishing polishes the zero-layer interlayer film 107, and since the surface position of the contact hole etching stop layer 105 on the top surface of the side wall 104 is the highest, the first selective chemical mechanical polishing polishes the zero-layer interlayer film 107 and then stops on the contact hole etching stop layer 105 on the top surface of the side wall 104.
The ratio of the polishing rate to the oxide film and the polishing rate to the nitride film in the first selective chemical mechanical polishing is greater than or equal to 20.
And step four, as shown in fig. 1D, performing a second chemical mechanical polishing with the surface of the polysilicon gate 103 as a stop layer, wherein a ratio of a polishing rate of the second chemical mechanical polishing to the oxide film to a polishing rate of the second chemical mechanical polishing to the nitride film is about 1: 2. Since the surface of the polysilicon gate 103 is used as a stop layer, the contact hole etching stop layer 105 remaining on the top surface of the polysilicon gate 103 needs to be removed in order to polish off the corresponding nitride film, and the oxide film is inevitably polished too much, so that the polished too much oxide film is liable to form a large butterfly defect on the zero interlayer film 107, and particularly the butterfly defect formed at the position of the spacer 205 with a large width is larger.
The method also comprises the following steps:
and removing the polysilicon gate 103. The process of removing the polysilicon gate 103 is generally referred to as a polysilicon dummy gate removal (DPR) process, and is usually completed by a dry etching and wet etching process.
And filling metal in the removal region of the polysilicon gate 103 to form a metal gate, and overlapping the gate dielectric layer and the metal gate to form a second gate structure.
In the process of forming the metal gate, metal residue is easily formed at the butterfly defect. If more polishing is performed to ensure no metal remains, the bottom sige layer 106 is easily polished, which also causes electrical anomalies in the device.
Disclosure of Invention
The invention aims to provide a manufacturing method of a zeroth interlayer film, which can improve butterfly defects.
In order to solve the above technical problems, the method for manufacturing the zeroth interlayer film provided by the invention comprises the following steps:
providing a semiconductor substrate, and forming a plurality of first grid structures formed by overlapping grid dielectric layers and polysilicon grids on the surface of the semiconductor substrate; the area between the first gate structures is a spacer area.
And forming a side wall on the side surface of the first grid structure, wherein the top surface of the side wall is higher than that of the polysilicon grid.
And forming a contact hole etching stop layer consisting of a nitride film, wherein the contact hole etching stop layer covers the surface of the polysilicon gate at the top of the first gate structure, the top surface and the inner and outer side surfaces of the side wall and the surface of the semiconductor substrate of the spacing area.
Growing a zero-layer interlayer film, wherein the zero-layer interlayer film is an oxide film, the zero-layer interlayer film is formed on the surface of the contact hole etching stop layer, and the zero-layer interlayer film fills the interval region and extends to the top of the first grid structure.
And step three, carrying out first-time selective chemical mechanical polishing, wherein the polishing rate of the first-time selective chemical mechanical polishing to the oxide film is greater than that to the nitride film, and the first-time selective chemical mechanical polishing is used for polishing the zero interlayer film and stops on the contact hole etching stop layer on the top surface of the side wall.
And fourthly, carrying out second-time non-selective chemical mechanical grinding, wherein the second-time non-selective chemical mechanical grinding simultaneously grinds the oxide film and the nitride film and stops on the contact hole etching stopping layer on the top surface of the polysilicon gate.
And fifthly, carrying out third selective etching to remove the residual contact hole etching stop layer on the top surface of the polysilicon gate.
In a further improvement, the first step of forming the first gate structure includes:
and 11, sequentially forming the gate dielectric layer and the polysilicon gate on the surface of the semiconductor substrate.
And 12, forming a hard mask layer on the surface of the polysilicon gate.
And step 13, carrying out photoetching to form a plurality of first gate structures, wherein the hard mask layer is superposed on the top of the polysilicon gate of each first gate structure.
In a further improvement, the first step of forming the first gate structure further comprises:
after the side wall is formed on the side face of the first gate structure, the method further comprises the step of removing the hard mask layer on the top of the polysilicon gate, so that the top surface of the side wall is higher than that of the polysilicon gate.
In a further improvement, the material of the hard mask layer comprises an oxide layer or a nitride film.
In a further improvement, the material of the sidewall comprises an oxide layer or a nitride film.
In a further improvement, the ratio of the polishing rate to the oxide film and the polishing rate to the nitride film in the first selective chemical mechanical polishing is greater than or equal to 20.
In a further improvement, the ratio of the polishing rate to the oxide film and the polishing rate to the nitride film in the second non-selective chemical mechanical polishing is 1: 2-1: 1.
in a further improvement, the ratio of the etching rate to the nitride film and the etching rate to the oxide film in the third selective etching is greater than or equal to 100.
The further improvement is that in the second step, the HARP process is adopted to grow the zero layer interlayer film.
In a further improvement, in the first step, the size of the space between the first gate structures includes a plurality, and the width of the first gate structure includes a plurality.
In a further improvement, the semiconductor substrate is a silicon substrate.
The further improvement is that the gate dielectric layer is made of an oxide layer; or, the gate dielectric layer is made of a high dielectric constant material.
In a further improvement, before the second step, a step of forming a source region and a drain region on the surface of the semiconductor substrate at two sides of the first gate structure is further included.
In a further improvement, the method further comprises the step of forming a silicon germanium layer in a formation region of the source region or the drain region when the source region or the drain region is formed.
The further improvement is that after the step five is completed, the method also comprises the following steps:
and removing the polysilicon gate.
And filling metal in the removal region of the polysilicon gate to form a metal gate, and overlapping the gate dielectric layer and the metal gate to form a second gate structure.
The invention has specially set the grinding process after the zero interlayer film growth, firstly, the first selective chemical mechanical grinding on the contact hole etching stop layer stopped on the top surface of the side wall is carried out; then, stopping the second non-selective chemical mechanical grinding on the contact hole etching stop layer on the top surface of the polysilicon gate, wherein the second non-selective chemical mechanical grinding can grind the oxide film and the nitride film simultaneously, so that the height difference of each position on the surface of the semiconductor substrate can be well eliminated; compared with the prior art that the polysilicon gate is directly used as the stop layer, the second non-selective chemical mechanical polishing is stopped on the contact hole etching stop layer, so that the polishing of the zero-layer interlayer film can be reduced, and the butterfly defect caused by excessive sinking of the zero-layer interlayer film can be overcome; and then, carrying out third selective etching to remove the residual contact hole etching stop layer on the top surface of the polysilicon gate, so that the invention can improve the butterfly defect, and can prevent metal residue caused by the butterfly defect of the zero-layer interlayer film, thereby improving the product yield.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A to 1E are device structure diagrams in respective steps of a conventional zero layer interlayer film manufacturing method;
FIG. 2 is a flow chart of a method of manufacturing a zero layer interlayer film according to an embodiment of the present invention;
fig. 3A to 3E are device configuration diagrams in respective steps of a zero-layer interlayer film manufacturing method according to an embodiment of the present invention.
Detailed Description
Fig. 2 is a flowchart showing a method for manufacturing the zero-layer interlayer film 7 according to the embodiment of the present invention; as shown in fig. 3A to 3E, the device structure diagrams in the steps of the method for manufacturing the zero-layer interlayer film 7 according to the embodiment of the present invention are shown, and the method for manufacturing the zero-layer interlayer film 7 according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, providing a semiconductor substrate 1, and forming a plurality of first gate structures formed by overlapping gate dielectric layers and polysilicon gates 3 on the surface of the semiconductor substrate 1; the area between each of the first gate structures is a spacer 305.
And forming a side wall 4 on the side surface of the first gate structure, wherein the top surface of the side wall 4 is higher than that of the polysilicon gate 3.
And forming a contact hole etching stop layer 5 consisting of a nitride film, wherein the contact hole etching stop layer 5 covers the surface of the polysilicon gate 3 at the top of the first gate structure, the top surface and the inner and outer side surfaces of the side wall 4 and the surface of the semiconductor substrate 1 of the spacing region 305. As shown in fig. 3A, the inner side surface of the inner and outer side surfaces of the side wall 4 refers to the side surface of the side wall 4 extending to the top of the polysilicon gate 3, which is close to the polysilicon gate 3, and the outer side surface of the inner and outer side surfaces of the side wall 4 refers to the side surface of the side wall 4, which is far from the polysilicon gate 3.
In an embodiment of the present invention, the sub-step of forming the first gate structure includes:
and 11, sequentially forming the gate dielectric layer (not shown) and the polysilicon gate 3 on the surface of the semiconductor substrate 1.
The semiconductor substrate 1 is a silicon substrate.
The gate dielectric layer is made of an oxide layer; or, the gate dielectric layer is made of a high dielectric constant material.
Step 12, forming a hard mask layer (not shown) on the surface of the polysilicon gate 3. The hard mask layer is made of an oxide layer or a nitride film.
And step 13, carrying out photoetching to form a plurality of first gate structures, wherein the hard mask layer is superposed on the top of the polysilicon gate 3 of each first gate structure.
The sub-steps of forming the first gate structure further include:
the material of the side wall 4 comprises an oxide layer or a nitride film. After the side wall 4 is formed on the side surface of the first gate structure, the method further includes the step of removing the hard mask layer on the top of the polysilicon gate 3, so that the top surface of the side wall 4 is higher than the top surface of the polysilicon gate 3.
A field oxide layer 2 is formed on a semiconductor substrate 1, and the field oxide layer 2 is typically formed using a Shallow Trench Isolation (STI) process. The field oxide layer 2 isolates an active area, the active area comprises an active area of a Core (Core) area and an active area of an input/output (IO) area, a Core device is formed in the active area of the Core area, and an input/output device is formed in the active area of the IO area; shown in FIG. 3A are a core nFET301, a core pFET302, an input output nFET303, and an input output pFET 304. The width of the first gate structure in step one includes a plurality of, for example, the width of the first gate structure in the active area of the input-output region, i.e., input-output nFET303 and input-output pFET304, is greater than the width of the first gate structure in the active area of the core region, i.e., core nFET301 and core pFET 302. In the embodiment of the present invention, the size of the space between the first gate structures, i.e. the width of the spacer 305, includes a plurality of first gate structures, for example, the space between the first gate structures in the active region of the input/output region is greater than the space between the first gate structures in the active region of the core region.
And a step of forming a source region and a drain region on the surface of the semiconductor substrate 1 at two sides of the first gate structure is further included before the step two. When the source region or the drain region is formed, a step of forming a silicon germanium layer 6 in a formation region of the source region or the drain region is further included. In fig. 3A, only the sige layer 6 is formed in the drain region of the core pFET302, and the sige layer 6 can provide stress to the channel region of the device, which is beneficial for improving the performance of the device.
Step two, as shown in fig. 3B, growing a zero interlayer film 7, wherein the zero interlayer film 7 is an oxide film, the zero interlayer film 7 is formed on the surface of the contact hole etching stop layer 5, and the zero interlayer film 7 fills the spacer 305 and extends to the top of the first gate structure.
In the embodiment of the invention, the zero interlayer film 7 is grown by using a HARP process.
Step three, as shown in fig. 3C, performing a first selective chemical mechanical polishing, where a polishing rate of the first selective chemical mechanical polishing to the oxide film is greater than a polishing rate to the nitride film, the first selective chemical mechanical polishing polishes the zero-layer interlayer film 7 and stops on the contact hole etching stop layer 5 on the top surface of the side wall 4, and since the surface position of the contact hole etching stop layer 105 on the top surface of the side wall 104 is the highest, the first selective chemical mechanical polishing stops on the contact hole etching stop layer 105 on the top surface of the side wall 104 after polishing the zero-layer interlayer film 107.
The ratio of the polishing rate to the oxide film and the polishing rate to the nitride film in the first selective chemical mechanical polishing is greater than or equal to 20.
And fourthly, as shown in fig. 3D, performing a second non-selective chemical mechanical polishing, wherein the second non-selective chemical mechanical polishing simultaneously polishes the oxide film and the nitride film and stops on the contact hole etching stop layer 5 on the top surface of the polysilicon gate 3. As shown in fig. 3C, before the second non-selective cmp, the surface of different regions of the semiconductor substrate 1 has a height difference, which is a height difference of a front layer caused by a front layer process, such as: the height difference of the junction structure of the side wall 4 protruding above the polysilicon gate 3 is caused by different grinding loads of the first selective chemical mechanical grinding on the zero-layer interlayer film 7 in different regions. After the second non-selective CMP process corresponding to FIG. 3D, the height difference of the front layer can be polished.
The ratio of the polishing rate of the oxide film to the polishing rate of the nitride film in the second non-selective chemical mechanical polishing is 1: 2-1: 1.
and fifthly, as shown in fig. 3E, carrying out third selective etching to remove the residual contact hole etching stop layer 5 on the top surface of the polysilicon gate 3.
And the ratio of the etching rate of the nitride film to the etching rate of the oxide film in the third selective etching is more than or equal to 100.
After the step five is finished, the method also comprises the following steps:
and removing the polysilicon gate 3, namely performing a DPR process, and usually removing the polysilicon gate 3 by dry etching and wet etching.
And filling metal in the removal region of the polysilicon gate 3 to form a metal gate, and overlapping the gate dielectric layer and the metal gate to form a second gate structure.
In the embodiment of the invention, the grinding process after the growth of the zero-layer interlayer film 7 is specially set, and first selective chemical mechanical grinding on the contact hole etching stop layer 5 stopped on the top surface of the side wall 4 is firstly carried out; then, stopping the second non-selective chemical mechanical grinding on the contact hole etching stopping layer 5 on the top surface of the polysilicon gate 3, wherein the second non-selective chemical mechanical grinding can grind the oxide film and the nitride film simultaneously, so that the height difference of each position on the surface of the semiconductor substrate 1 can be well eliminated; meanwhile, compared with the prior art that the polysilicon gate 3 is directly used as a stop layer, the second non-selective chemical mechanical polishing is stopped on the contact hole etching stop layer 5, so that the polishing of the zero interlayer film 7 can be reduced, and the butterfly defect caused by excessive sinking of the zero interlayer film 7 can be improved; and then, carrying out third selective etching to remove the residual contact hole etching stop layer 5 on the top surface of the polysilicon gate 3, so that the embodiment of the invention can improve the butterfly defect, and can prevent metal residue caused by the butterfly defect of the zero interlayer film 7, thereby improving the yield of products.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A method of making a zeroth layer interlayer film, comprising the steps of:
providing a semiconductor substrate, and forming a plurality of first grid structures formed by overlapping grid dielectric layers and polysilicon grids on the surface of the semiconductor substrate; the area between the first grid structures is a spacer area;
forming a side wall on the side face of the first grid structure, wherein the top surface of the side wall is higher than that of the polysilicon grid;
forming a contact hole etching stop layer consisting of a nitride film, wherein the contact hole etching stop layer covers the surface of the polysilicon gate at the top of the first gate structure, the top surface and the inner and outer side surfaces of the side wall and the surface of the semiconductor substrate of the spacing area;
growing a zero-layer interlayer film, wherein the zero-layer interlayer film is an oxide film, is formed on the surface of the contact hole etching stop layer, and fills the spacer region and extends to the top of the first gate structure;
carrying out first selective chemical mechanical polishing, wherein the polishing rate of the first selective chemical mechanical polishing to an oxide film is greater than that to a nitride film, and the first selective chemical mechanical polishing is used for polishing the zero interlayer film and stopping on the contact hole etching stop layer on the top surface of the side wall;
performing second non-selective chemical mechanical polishing, wherein the second non-selective chemical mechanical polishing simultaneously polishes the oxide film and the nitride film and stops on the contact hole etching stop layer on the top surface of the polysilicon gate;
and fifthly, carrying out third selective etching to remove the residual contact hole etching stop layer on the top surface of the polysilicon gate.
2. The method of claim 1, wherein the first sub-step of forming the first gate structure comprises:
step 11, sequentially forming the gate dielectric layer and the polysilicon gate on the surface of the semiconductor substrate;
step 12, forming a hard mask layer on the surface of the polysilicon gate;
and step 13, carrying out photoetching to form a plurality of first gate structures, wherein the hard mask layer is superposed on the top of the polysilicon gate of each first gate structure.
3. The method of claim 2, wherein the first sub-step of forming the first gate structure further comprises:
after the side wall is formed on the side face of the first gate structure, the method further comprises the step of removing the hard mask layer on the top of the polysilicon gate, so that the top surface of the side wall is higher than that of the polysilicon gate.
4. A method of manufacturing a zeroth interlayer film according to claim 2, wherein: the hard mask layer is made of an oxide layer or a nitride film.
5. A method of manufacturing a zeroth interlayer film according to claim 3, wherein: the material of the side wall comprises an oxide layer or a nitride film.
6. A method of manufacturing a zeroth interlayer film according to claim 1, wherein: the ratio of the polishing rate to the oxide film and the polishing rate to the nitride film in the first selective chemical mechanical polishing is greater than or equal to 20.
7. A method of manufacturing a zeroth interlayer film according to claim 1, wherein: the ratio of the polishing rate of the oxide film to the polishing rate of the nitride film in the second non-selective chemical mechanical polishing is 1: 2-1: 1.
8. a method of manufacturing a zeroth interlayer film according to claim 1, wherein: and the ratio of the etching rate of the nitride film to the etching rate of the oxide film in the third selective etching is more than or equal to 100.
9. A method of manufacturing a zeroth interlayer film according to claim 1, wherein: and growing the zero layer interlayer film by adopting an HARP process in the second step.
10. A method of manufacturing a zeroth interlayer film according to claim 1, wherein: in the first step, the space between the first gate structures is multiple, and the width of the first gate structure is multiple.
11. A method of manufacturing a zeroth interlayer film according to claim 1, wherein: the semiconductor substrate is a silicon substrate.
12. A method of manufacturing a zeroth interlayer film according to claim 11, wherein: the gate dielectric layer is made of an oxide layer; or, the gate dielectric layer is made of a high dielectric constant material.
13. A method of manufacturing a zeroth interlayer film according to claim 12, wherein: and before the second step, a step of forming a source region and a drain region on the surface of the semiconductor substrate at two sides of the first gate structure is also included.
14. A method of manufacturing a zeroth interlayer film according to claim 13, wherein: when the source region or the drain region is formed, a step of forming a germanium-silicon layer in a formation region of the source region or the drain region is further included.
15. A method of manufacturing a zeroth interlayer film according to claim 14, wherein: after the step five is finished, the method also comprises the following steps:
removing the polysilicon gate;
and filling metal in the removal region of the polysilicon gate to form a metal gate, and overlapping the gate dielectric layer and the metal gate to form a second gate structure.
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