CN110379705A - The manufacturing method of level 0 interlayer film - Google Patents
The manufacturing method of level 0 interlayer film Download PDFInfo
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- CN110379705A CN110379705A CN201910670197.2A CN201910670197A CN110379705A CN 110379705 A CN110379705 A CN 110379705A CN 201910670197 A CN201910670197 A CN 201910670197A CN 110379705 A CN110379705 A CN 110379705A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
The invention discloses a kind of manufacturing methods of level 0 interlayer film, comprising steps of Step 1: forming multiple first grid structures being formed by stacking by gate dielectric layer and polysilicon gate；Step 2: carry out the growth of level 0 interlayer film, including step by step: step 21, the first time for carrying out using FCVD technique, which deposit, to be formed the first oxide layer and is filled up completely each spacer region；Step 22, carry out using HDPCVD technique be deposited on for the second time the first oxidation layer surface formed the second oxide layer and be superimposed form level 0 interlayer film；Step 3: level 0 interlayer film is carried out carrying out chemical mechanical grinding and is ground to equal with the surface of first grid structure.The present invention has the characteristics that mobility is able to achieve using the first oxide layer that FCVD technique is formed and fills spacer region without cavity, increase the hardness of level 0 interlayer film, in combination with the second oxide layer formed using HDPCVD technique so as to eliminate the butterfly defect of the level 0 interlayer film after grinding.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture methods, more particularly to a kind of manufacture of level 0 interlayer film
Method.
Background technique
In existing advanced logic chip technique, with being integrated with multiple device cells, device list on semi-conductive substrate wafer
It include polysilicon gate in the gate structure of member, the spacing of each polysilicon gate will not be identical, but has a variety of distance values, more
It generally requires to fill using level 0 interlayer film (ILD0) in spacer region between crystal silicon grid.Existing level 0 interlayer film is logical
Frequently with high-aspect-ratio technique (High Aspect Ratio Process, HARP) fill, this is because HARP be able to achieve it is higher
Depth-to-width ratio filling.It is the device architecture in each step of manufacturing method of existing level 0 interlayer film as shown in Figure 1A to Fig. 1 D
Figure, the manufacturing method of existing level 0 interlayer film include the following steps:
Step 1: as shown in Figure 1A, providing semi-conductive substrate 101, being formed on 101 surface of semiconductor substrate multiple
The first grid structure being formed by stacking by gate dielectric layer 103 and polysilicon gate 104；Region between each first grid structure
For spacer region 205.
In general, form the first grid structure includes: step by step
Step 11 sequentially forms the gate dielectric layer 103 and the polysilicon gate on 101 surface of semiconductor substrate
104。
The semiconductor substrate 101 is silicon substrate.The material of the gate dielectric layer 103 is oxide layer；Alternatively, the grid are situated between
The material of matter layer 103 uses high dielectric constant material.
Step 12 forms hard mask layers on the surface of the polysilicon gate 104.The material of the hard mask layers includes
Oxide layer or nitration case.
Step 13 carries out chemical wet etching and forms multiple first grid structures, the first grid structure it is described more
The top of crystal silicon grid 104 is also superimposed with the hard mask layers.
Step 14 forms side wall 105 in the side of each first grid structure.The material of the side wall 105 includes oxygen
Change layer or nitration case.
Field oxide 102 is formed in semiconductor substrate 101, field oxide 102 generallys use shallow trench isolation (STI)
Technique is formed.Field oxide 102 isolates active area, and active area includes active area and the input and output in the region core (Core)
(IO) active area in region is formed with core devices in the active area of nucleus, is formed in the active area in input and output region
There is input and output device；Core nFET201, core pFET202, input and output nFET203, input and output are shown in Figure 1A
pFET204.The width of the first grid structure in step 1 includes multiple, such as in the active area in input and output region
The width of the first grid structure of device, that is, input and output nFET203 and input and output pFET204 is greater than nucleus
The width of the first grid structure of device, that is, core nFET201 and core pFET202 in active area.Each first grid
Spacing size, that is, spacer region 205 width between the structure of pole includes multiple, for example, in the active area in input and output region
Each first grid structure spacing be greater than nucleus active area in each first grid structure spacing.
It further include forming source on 101 surface of the semiconductor substrate of first grid structure two sides before step 2
The step of area and drain region.It further include in the forming region in the source region or the drain region when forming the source region or drain region
The step of forming germanium silicon layer 107.In Figure 1A, only shows and be formed with the germanium silicon layer in the drain region of the core pFET202
107, the germanium silicon layer 107 can provide stress for the channel region of device, be conducive to the performance for promoting device.
Later, further includes: form the contact hole etching stop-layer 106 being made of nitration case, the contact hole etching stops
Layer 106 is covered on the hard mask layer surface at top, the side of the side wall 105 and the institute of the first grid structure
State 101 surface of the semiconductor substrate of spacer region 205.In other embodiments, also can are as follows: forming the contact hole etching
The hard mask layer is removed before stop-layer 106, the contact hole etching stop-layer 106 described in this way can directly contact described first
The top surface of the polysilicon gate 104 of gate structure.
Step 2: carrying out the growth of level 0 interlayer film 108, including as follows step by step:
Step 21, as shown in Figure 1B, carrying out the first time using HARP technique deposits to form the first oxide layer 108a, described
First oxide layer 108a also extends into the top of each first grid structure.In general, the first oxide layer 108a can be in institute
The top for stating spacer region 205 is first closed that cavity can be formed in the spacer region 205.
Step 22, as shown in Figure 1 C, carries out second of etching processing to the first oxide layer 108a, at second of etching
The first oxide layer 108a after reason is individually indicated with label 108b.It would generally be by first oxygen after second of etching processing
Change the region with a closed top layer 108a to open.
Step 23, as shown in figure iD repeats second of etching processing technique of the first time deposition and step 22 of step 21
Eventually form the level 0 interlayer film 108 for filling the spacer region 205.
The level 0 interlayer film 108 is ground Step 3: carrying out chemical mechanical milling tech, it is described after grinding
Level 0 interlayer film 108 is only located in the spacer region 205 and surface is equal with the surface of the first grid structure.
With the continuous scaled down of the size of device, above-mentioned is existing using spacer region described in HARP process filling
205 method is easy to produce cavity blemish, so that the yield of product be made to be affected.It is existing as shown in Fig. 2A to Fig. 2 F
Occur device junction composition when cavity blemish in corresponding each step in the manufacturing method of zero layer interlayer film, be described below:
As shown in Figure 2 A, dotted line frame 205a, which corresponds to, forms the interval before the contact hole etching stop-layer 106
Area.At this moment, the width of the spacer region 205a is larger, and depth-to-width ratio is smaller, is advantageously implemented HARP technique to the spacer region
205a's fills without cavity.
But as shown in Figure 2 B, it is formed before the contact hole etching stop-layer 106, the width meeting of the spacer region 205
Become smaller, deep width can become larger, and fill without cavity using HARP technique to be unfavorable for realizing.
As shown in Figure 2 C, easy to form empty 206 after forming the level 0 interlayer film 108.
As shown in Figure 2 D, after the chemical mechanical milling tech for carrying out step 3, described empty 206 top area meeting
It opens.Later, the polysilicon gate 104 is removed.
As shown in Figure 2 F, metal gate 109 is formed in the region for removing the polysilicon gate 104.In general, forming the gold
It further include the barrier layer 110 of the metal of formation metal gate 109 as shown in Figure 2 E before belonging to grid 109.
As shown in Fig. 2 F it is found that while forming metal gate 109, also formed in empty 206 region
There is metal residual 109a.The performance that metal residual 109a will affect device is such as easy to bring short circuit problem, to will affect product
Yield.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of manufacturing methods of level 0 interlayer film, can be by gate structure
Between spacer region without cavity fill.
In order to solve the above technical problems, the manufacturing method of level 0 interlayer film provided by the invention includes the following steps:
Step 1: providing semi-conductive substrate, formed in the semiconductor substrate surface multiple by gate dielectric layer and polycrystalline
The first grid structure that Si-gate is formed by stacking；Region between each first grid structure is spacer region.
Step 2: carrying out the growth of level 0 interlayer film, including as follows step by step:
Each spacer region is filled up completely by the first oxide layer of deposition formation for the first time for step 21, progress, first oxygen
Change the top that layer also extends into each first grid structure；The first time deposition is using fluid chemistry vapor deposition (FCVD)
Technique, the mobility of first oxide layer formed using FCVD technique, which is realized, fills the spacer region without cavity.
Step 22 is deposited on the first oxidation layer surface second oxide layer of formation for the second time, by first oxygen
Change layer and second oxide layer is superimposed to form the level 0 interlayer film；Second of deposition uses HDPCVD technique, high
Density plasma CVD (HDPCVD) technique makes the hardness of second oxide layer be greater than first oxide layer
Hardness.
The level 0 interlayer film is ground Step 3: carrying out chemical mechanical milling tech, described the after grinding
It is equal with the surface of the first grid structure that zero layer interlayer film is only located in the spacer region and surface, utilizes second oxygen
The butterfly of the level 0 interlayer film after changing the characteristics of hardness of layer is greater than the hardness of first oxide layer elimination grinding is scarce
It falls into.
A further improvement is that step 1 form the first grid structure include: step by step
Step 11 sequentially forms the gate dielectric layer and the polysilicon gate in the semiconductor substrate surface.
Step 12 forms hard mask layers on the surface of the polysilicon gate.
Step 13 carries out chemical wet etching and forms multiple first grid structures, the first grid structure it is described more
The top of crystal silicon grid is also superimposed with the hard mask layers.
A further improvement is that step 1 forms the first grid structure step by step further include:
Step 14 forms side wall in the side of each first grid structure.
A further improvement is that the material of the hard mask layers includes oxide layer or nitration case.
A further improvement is that the material of the side wall includes oxide layer or nitration case.
A further improvement is that further including following steps before carrying out step 2:
The contact hole etching stop-layer being made of nitration case is formed, the contact hole etching stop-layer is covered on described first
The semiconductor of the hard mask layer surface at the top of gate structure, the side of the side wall and the spacer region serves as a contrast
Bottom surface.
A further improvement is that the chemical mechanical milling tech in step 3 is to stop with the surface of the polysilicon gate
Only layer.
A further improvement is that the chemical mechanical milling tech in step 3 is with the contact hole etching stop-layer
Surface is stop-layer.
A further improvement is that the spacing size in step 1 between each first grid structure includes multiple.
A further improvement is that the width of the first grid structure in step 1 includes multiple.
A further improvement is that the semiconductor substrate is silicon substrate.
A further improvement is that the material of the gate dielectric layer is oxide layer；Alternatively, the material of the gate dielectric layer uses
High dielectric constant material.
A further improvement is that further including that the semiconductor in first grid structure two sides serves as a contrast before step 2
Bottom surface forms the step of source region and drain region.
A further improvement is that further including the shape in the source region or the drain region when forming the source region or drain region
At the step of forming germanium silicon layer in region.
A further improvement is that step 3 is completed to further include later following steps:
Remove the polysilicon gate.
Metal gate is formed in the removal area filling metal of the polysilicon gate, by the gate dielectric layer and the metal gate
Superposition forms second grid structure.
The present invention has the characteristics that mobility is able to achieve spacer region without sky using the first oxide layer that FCVD technique is formed
Hole filling, increases the hardness of level 0 interlayer film in combination with the second oxide layer formed using HDPCVD technique, so as to
Spacer region is filled and is disappeared without cavity so the present invention can realize simultaneously by the butterfly defect of the level 0 interlayer film after eliminating grinding
Except butterfly defect；The structure of level 0 interlayer film without cavity and butterfly defect can prevent metal residual, so as to improve product
Yield.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Figure 1A-Fig. 1 D is the device junction composition in each step of manufacturing method of existing level 0 interlayer film；
Fig. 2A-Fig. 2 F be existing level 0 interlayer film manufacturing method in occur when cavity blemish in corresponding each step
Device junction composition；
Fig. 3 is the flow chart of the manufacturing method of level 0 interlayer film of the embodiment of the present invention；
Fig. 4 A- Fig. 4 C is the device junction composition in each step of manufacturing method of level 0 interlayer film of the embodiment of the present invention.
Specific embodiment
As shown in figure 3, being the flow chart of the manufacturing method of level 0 of embodiment of the present invention interlayer film 8；Such as Fig. 4 A to Fig. 4 C
It is shown, it is the device junction composition in each step of manufacturing method of level 0 of embodiment of the present invention interlayer film 8, the embodiment of the present invention
The manufacturing method of zero layer interlayer film 8 includes the following steps:
Step 1: as shown in Figure 4 A, providing semi-conductive substrate 1, being formed on 1 surface of semiconductor substrate multiple by grid
The first grid structure that dielectric layer 3 and polysilicon gate 4 are formed by stacking；Region between each first grid structure is spacer region
305。
Form the first grid structure includes: step by step
Step 11 sequentially forms the gate dielectric layer 3 and the polysilicon gate 4 on 1 surface of semiconductor substrate.
The semiconductor substrate 1 is silicon substrate.The material of the gate dielectric layer 3 is oxide layer；Alternatively, the gate dielectric layer
3 material uses high dielectric constant material.
Step 12 forms hard mask layers on the surface of the polysilicon gate 4.The material of the hard mask layers includes oxygen
Change layer or nitration case.
Step 13 carries out chemical wet etching and forms multiple first grid structures, the first grid structure it is described more
The top of crystal silicon grid 4 is also superimposed with the hard mask layers.
Step 14 forms side wall 5 in the side of each first grid structure.The material of the side wall 5 includes oxide layer
Or nitration case.
It is formed with field oxide 2 on semiconductor substrate 1, field oxide 2 generallys use shallow trench isolation (STI) technique shape
At.Field oxide 2 isolates active area, and active area includes active area and the region input and output (IO) in the region core (Core)
Active area, be formed with core devices in the active area of nucleus, it is defeated that input be formed in the active area in input and output region
Device out；Core nFET301, core pFET302, input and output nFET303, input and output pFET304 are shown in Fig. 4 A.
The width of the first grid structure in step 1 includes multiple, such as the device in the active area in input and output region, that is, defeated
The width for entering to export the first grid structure of nFET303 and input and output pFET304 is greater than in the active area of nucleus
Device, that is, core nFET301 and core pFET302 the first grid structure width.In the embodiment of the present invention, each institute
State the width of the i.e. described spacer region 305 of the spacing size between first grid structure include it is multiple, for example, input and output region
The spacing of each first grid structure in active area is greater than each first grid structure in the active area of nucleus
Spacing.
It further include forming source region on 1 surface of the semiconductor substrate of first grid structure two sides before step 2
And the step of drain region.It further include the shape in the forming region in the source region or the drain region when forming the source region or drain region
The step of at germanium silicon layer 7.In Fig. 4 A, only shows and be formed with the germanium silicon layer 7 in the drain region of the core pFET302, it is described
Germanium silicon layer 7 can provide stress for the channel region of device, be conducive to the performance for promoting device.
Later, further includes: form the contact hole etching stop-layer 6 being made of nitration case, the contact hole etching stop-layer 6
It is covered on the hard mask layer surface at the top of the first grid structure, the side and the interval of the side wall 5
1 surface of the semiconductor substrate in area 305.In other embodiments, also can are as follows: forming the contact hole etching stop-layer 6
The hard mask layer is removed before, and the contact hole etching stop-layer 6 described in this way can directly contact the first grid structure
The top surface of the polysilicon gate 4.
Step 2: carrying out the growth of level 0 interlayer film 8, including as follows step by step:
Step 21 carries out deposition for the first time and forms the first oxide layer 8a for each spacer region 305 being filled up completely, described the
One oxide layer 8a also extends into the top of each first grid structure；The first time deposition uses FCVD technique, utilizes
The mobility for the first oxide layer 8a that FCVD technique is formed, which is realized, fills the spacer region 305 without cavity.
Step 22 is deposited on the surface the first oxide layer 8a for the second time and forms the second oxide layer 8b, by described the
One oxide layer 8a and the second oxide layer 8b are superimposed to form the level 0 interlayer film 8；Second of deposition uses
HDPCVD technique, the hardness that HDPCVD technique makes the hardness of the second oxide layer 8b be greater than the first oxide layer 8a.
The level 0 interlayer film 8 is ground Step 3: carrying out chemical mechanical milling tech, described the after grinding
Zero layer interlayer film 8 is only located in the spacer region 305 and surface is equal with the surface of the first grid structure, utilizes described
The hardness of dioxide layer 8b is greater than the level 0 interlayer film 8 after the elimination grinding of the characteristics of hardness of the first oxide layer 8a
Butterfly defect.
The chemical mechanical milling tech in step 3 is using the surface of the polysilicon gate 4 as stop-layer.Alternatively, step
The chemical mechanical milling tech in three is using the surface of the contact hole etching stop-layer 6 as stop-layer.
Step 3 further includes following steps after completing:
Remove the polysilicon gate 4.
Metal gate is formed in the removal area filling metal of the polysilicon gate 4, by the gate dielectric layer 3 and the metal
Grid are superimposed to form second grid structure.
FCVD process flowability is preferable, and the embodiment of the present invention has flowing using the first oxide layer 8a that FCVD technique is formed
Property the characteristics of be able to achieve by spacer region 305 without cavity fill.But the hardness of the first oxide layer 8a of FCVD technique formation is softer,
Butterfly defect is easy to produce after chemical mechanical grinding, therefore the embodiment of the present invention is in combination with using the formation of HDPCVD technique
Second oxide layer 8b increases the hardness of level 0 interlayer film 8, lacks so as to eliminate the butterfly of the level 0 interlayer film 8 after grinding
It falls into, so the embodiment of the present invention can be realized spacer region 305 simultaneously without cavity filling and elimination butterfly defect；Without cavity and butterfly
The structure of the level 0 interlayer film 8 of defect can prevent metal residual, so as to improve product yield.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of manufacturing method of level 0 interlayer film, which comprises the steps of:
Step 1: providing semi-conductive substrate, formed in the semiconductor substrate surface multiple by gate dielectric layer and polysilicon gate
The first grid structure being formed by stacking；Region between each first grid structure is spacer region；
Step 2: carrying out the growth of level 0 interlayer film, including as follows step by step:
Each spacer region is filled up completely by the first oxide layer of deposition formation for the first time for step 21, progress, first oxide layer
Also extend into the top of each first grid structure；The first time deposition uses FCVD technique, is formed using FCVD technique
First oxide layer mobility realize by the spacer region without cavity fill；
Step 22 is deposited on the first oxidation layer surface second oxide layer of formation for the second time, by first oxide layer
It is superimposed to form the level 0 interlayer film with second oxide layer；Second of deposition uses HDPCVD technique, HDPCVD
Technique makes the hardness of second oxide layer greater than the hardness of first oxide layer；
The level 0 interlayer film is ground Step 3: carrying out chemical mechanical milling tech, the level 0 after grinding
It is equal with the surface of the first grid structure that interlayer film is only located in the spacer region and surface, utilizes second oxide layer
Hardness be greater than first oxide layer hardness the characteristics of eliminate grinding after the level 0 interlayer film butterfly defect.
2. the manufacturing method of level 0 interlayer film as described in claim 1, which is characterized in that step 1 forms the first grid
Pole structure includes: step by step
Step 11 sequentially forms the gate dielectric layer and the polysilicon gate in the semiconductor substrate surface；
Step 12 forms hard mask layers on the surface of the polysilicon gate；
Step 13, progress chemical wet etching form multiple first grid structures, the polysilicon of the first grid structure
The top of grid is also superimposed with the hard mask layers.
3. the manufacturing method of level 0 interlayer film as claimed in claim 2, which is characterized in that step 1 forms the first grid
Pole structure is step by step further include:
Step 14 forms side wall in the side of each first grid structure.
4. the manufacturing method of level 0 interlayer film as claimed in claim 2, it is characterised in that: the material of the hard mask layers
Including oxide layer or nitration case.
5. the manufacturing method of level 0 interlayer film as claimed in claim 3, it is characterised in that: the material of the side wall includes oxygen
Change layer or nitration case.
6. the manufacturing method of level 0 interlayer film as claimed in claim 3, it is characterised in that: also wrapped before carrying out step 2
Include following steps:
The contact hole etching stop-layer being made of nitration case is formed, the contact hole etching stop-layer is covered on the first grid
The semiconductor substrate table of the hard mask layer surface at the top of structure, the side of the side wall and the spacer region
Face.
7. the manufacturing method of level 0 interlayer film as described in claim 1, it is characterised in that: the chemical machine in step 3
Tool grinding technics is using the surface of the polysilicon gate as stop-layer.
8. the manufacturing method of level 0 interlayer film as claimed in claim 6, it is characterised in that: the chemical machine in step 3
Tool grinding technics is using the surface of the contact hole etching stop-layer as stop-layer.
9. the manufacturing method of level 0 interlayer film as described in claim 1, it is characterised in that: each first grid in step 1
Spacing size between the structure of pole includes multiple.
10. the manufacturing method of level 0 interlayer film as claimed in claim 9, it is characterised in that: described first in step 1
The width of gate structure includes multiple.
11. the manufacturing method of level 0 interlayer film as described in claim 1, it is characterised in that: the semiconductor substrate is silicon
Substrate.
12. the manufacturing method of level 0 interlayer film as claimed in claim 11, it is characterised in that: the material of the gate dielectric layer
For oxide layer；Alternatively, the material of the gate dielectric layer uses high dielectric constant material.
13. the manufacturing method of level 0 interlayer film as claimed in claim 12, it is characterised in that: further include before step 2
The step of semiconductor substrate surface in first grid structure two sides forms source region and drain region.
14. the manufacturing method of level 0 interlayer film as claimed in claim 13, it is characterised in that: forming the source region or leakage
Qu Shi further includes the steps that forming germanium silicon layer in the forming region in the source region or the drain region.
15. the manufacturing method of level 0 interlayer film as claimed in claim 14, it is characterised in that: step 3 is also wrapped after completing
Include following steps:
Remove the polysilicon gate；
Metal gate is formed in the removal area filling metal of the polysilicon gate, is superimposed by the gate dielectric layer and the metal gate
Form second grid structure.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110854019A (en) * | 2019-11-26 | 2020-02-28 | 上海华力集成电路制造有限公司 | Semiconductor manufacturing method |
| CN114038752A (en) * | 2021-10-09 | 2022-02-11 | 上海华力集成电路制造有限公司 | High-voltage MOSFET device and manufacturing method thereof |
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| CN114038752A (en) * | 2021-10-09 | 2022-02-11 | 上海华力集成电路制造有限公司 | High-voltage MOSFET device and manufacturing method thereof |
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