CN110277313A - The manufacturing method of side wall - Google Patents
The manufacturing method of side wall Download PDFInfo
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- CN110277313A CN110277313A CN201910476405.5A CN201910476405A CN110277313A CN 110277313 A CN110277313 A CN 110277313A CN 201910476405 A CN201910476405 A CN 201910476405A CN 110277313 A CN110277313 A CN 110277313A
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- side wall
- silicon nitride
- polysilicon gate
- manufacturing
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 75
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 72
- 229920005591 polysilicon Polymers 0.000 claims abstract description 72
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 71
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 238000005137 deposition process Methods 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 230000000717 retained effect Effects 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910003978 SiClx Inorganic materials 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 4
- 239000000203 mixture Substances 0.000 abstract description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 125000004429 atom Chemical group 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of manufacturing methods of side wall, comprising steps of Step 1: formation gate dielectric layer and polysilicon gate, are formed with the hard mask layers of silicon nitride composition in the top surface of polysilicon gate；Step 2: forming the second silicon nitride layer using atom layer deposition process；Step 3: carrying out the moditied processing of silicon nitride using ion implantation technology, the second silicon nitride layer of the side of polysilicon gate, which remains, is not modified processing；Step 4: being modified the silicon nitride of processing using DHF removal, the silicon nitride for not being modified processing is retained in the side formation first layer side wall of polysilicon gate.The present invention can to polysilicon gate side outside the silicon nitride using ALD deposition removed well, avoid at the top of polysilicon gate formed silicon nitride spacer fence.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture methods, more particularly to a kind of manufacturing method of side wall.
Background technique
In semiconductor fabrication, after forming the gate structure being formed by stacking by gate dielectric layer and polysilicon gate, often
It needs to form side wall in the side of polysilicon gate, the material of side wall would generally include silicon nitride.And in the definition of polysilicon gate
Cheng Zhong generally requires to use hard mask layers, and hard mask layers are usually also required to using silicon nitride.
In some techniques, as on thin buried oxide in the manufacturing process of silicon (SOTB), polysilicon gate formed after the
The corresponding silicon nitride of one layer of side wall generally requires to be formed using atomic layer deposition (ALD) technique.And the hard at the top of polysilicon gate
Mask layer generally requires to remove as removed using hot phosphoric acid, but the silicon nitride that ALD technique is formed cannot be removed by hot phosphoric acid, this
First layer side wall pair of sample during using the silicon nitride of hot phosphoric acid removal hard mask layers, positioned at hard mask layers side
The silicon nitride answered often retains；In this way, first layer side wall can be projected into the top of polysilicon gate after removing hard mask layers
On portion surface, so that fence (fence) structure is formed, to influence the performance of device and thereby influence the yield of product.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of manufacturing method of side wall, can be to polysilicon gate side outside
It is removed well using the silicon nitride of ALD deposition, avoids forming silicon nitride spacer fence at the top of polysilicon gate.
In order to solve the above technical problems, the manufacturing method of side wall provided by the invention includes the following steps:
Step 1: gate dielectric layer and polysilicon gate are formed in semiconductor substrate surface, in the top table of the polysilicon gate
Face is formed with the hard mask layers being made of the first silicon nitride layer.
Step 2: forming the second silicon nitride layer using atom layer deposition process, second silicon nitride layer is covered on described
The semiconductor substrate surface outside the side of polysilicon gate and the polysilicon gate and it is coated on the hard mask layers
Top surface and side.
Step 3: carrying out the moditied processing of silicon nitride using ion implantation technology, the silicon nitride for being modified processing includes institute
It states described at the top of second silicon nitride layer and the polysilicon gate of the semiconductor substrate surface outside polysilicon gate
Hard mask layers and second silicon nitride layer for being coated on the hard mask layers top surface and side；The polysilicon
Second silicon nitride layer of the side of grid, which remains, is not modified processing；The silicon nitride for being modified processing can be by dilute hydrogen fluorine
Sour (DHF) removal, the silicon nitride for not being modified processing cannot be removed by DHF.
Step 4: using DHF remove described in be modified the silicon nitride of processing, the silicon nitride for not being modified processing retains
First layer side wall is formed in the side of the polysilicon gate, the top surface of the first layer side wall, which is lower than, is equal to the polysilicon
The top surface of grid, thus eliminate due to the first layer side wall is projected into the top surface of the polysilicon gate and enclosing for being formed
Column structure.
A further improvement is that further including following steps:
Step 5: being formed in the side for being formed with the polysilicon gate of the first layer side wall by third silicon nitride layer group
At second layer side wall.
A further improvement is that the second layer side wall carries out autoregistration using third silicon nitride layer is first grown again later
Dry etching forms the second layer side wall.
A further improvement is that the ion of the ion implanting of moditied processing described in step 3 is hydrogen ion.
A further improvement is that in step 2, the hard mask layers at the top of the polysilicon gate and described
The superposition thickness of nitride silicon layer is less than or equal to
A further improvement is that semiconductor substrate described in step 1 uses SOI substrate, the SOI substrate includes bottom
Body silicon, buries oxide layer and top silicon layer.
A further improvement is that the corresponding transistor of the polysilicon gate is SOTB transistor；The gate dielectric layer is formed
On the top silicon layer surface.
A further improvement is that the gate dielectric layer is gate oxide.
A further improvement is that being formed with an oxygen layer on the semiconductor substrate, isolated by the field oxygen layer active
Area.
A further improvement is that the field oxygen layer is to be formed using shallow ditch groove separation process.
A further improvement is that being further comprised the steps of: after step 5
Step 6: using epitaxial growth technology outside the polysilicon gate for being formed with the second layer side wall described half
Conductor substrate surface forms semiconductor epitaxial layers.
A further improvement is that further including to described half before the epitaxial growth technology for carrying out the semiconductor epitaxial layers
The step of conductor substrate surface is cleaned.
A further improvement is that the semiconductor epitaxial layers are silicon epitaxy layer.
A further improvement is that being further comprised the steps of: after step 6
Step 7: forming source region and drain region in the semiconductor epitaxial layers of the polysilicon gate two sides.
A further improvement is that the ion implanting of moditied processing described in step 3 is vertical injection.
The present invention increases after the second silicon nitride layer that polysilicon gate side is formed by atom layer deposition process formation
One step carries out the moditied processing of silicon nitride using ion implantation technology, utilizes the silicon nitride energy quilt for being ion implanted modified
DHF is removed and is not ion implanted the characteristics of silicon nitride of modified will not be removed by DHF, in conjunction with subsequent DHF removal technique
Autoregistration all removes the silicon nitride except polysilicon gate side, and the second silicon nitride layer for being retained in polysilicon gate side is made
For first layer side wall；Modification is all ion implanted due to being located at hard mask layers within the scope of the whole thickness at the top of polysilicon gate
It crosses, second silicon nitride layer of the hard mask layers at the top of polysilicon gate together with the top surface and side for being coated on hard mask layers
It will be removed by DHF, so be resistant to avoid being projected into the formation of the fence surrounded by side wall at the top of polysilicon gate, so, this
Invention can to polysilicon gate side outside the silicon nitride using ALD deposition removed well, avoid at the top of polysilicon gate
Form silicon nitride spacer fence.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the flow chart of the manufacturing method of side wall of the embodiment of the present invention；
Fig. 2A-Fig. 2 E is the device junction composition in each step of manufacturing method of side wall of the embodiment of the present invention.
Specific embodiment
As shown in Figure 1, being the flow chart of the manufacturing method of side wall of the embodiment of the present invention；It is this as shown in Fig. 2A to Fig. 2 E
Device junction composition in each step of the manufacturing method of inventive embodiments side wall, the manufacturing method of side wall of the embodiment of the present invention include such as
Lower step:
Step 1: as shown in Figure 2 A, gate dielectric layer 5 and polysilicon gate 6 are formed in semiconductor substrate surface, in the polycrystalline
The top surface of Si-gate 6 is formed with the hard mask layers 7 being made of the first silicon nitride layer.
Semiconductor substrate described in step 1 uses SOI substrate, and the SOI substrate includes lower bulk silicon 1, buries oxide layer 2
With top silicon layer 3.
The corresponding transistor of the polysilicon gate 6 is SOTB transistor；The gate dielectric layer 5 is formed in the top silicon layer
On 3 surfaces.
The gate dielectric layer 5 is gate oxide.
It is formed with an oxygen layer 4 on the semiconductor substrate, active area is isolated by the field oxygen layer 4.The field oxygen layer 4
To be formed using shallow ditch groove separation process.
Step 2: as shown in Figure 2 A, forming the second silicon nitride layer 8, second silicon nitride using atom layer deposition process
Layer 8 is covered on the side of the polysilicon gate 6 and the semiconductor substrate surface outside the polysilicon gate 6 and is coated on
The top surface of the hard mask layers 7 and side.
It is small positioned at the hard mask layers 7 at 6 top of polysilicon gate and the superposition thickness of second silicon nitride layer 8
In being equal to
Step 3: as shown in Figure 2 B, the moditied processing of silicon nitride being carried out using ion implantation technology, is modified the nitrogen of processing
SiClx includes second silicon nitride layer 8 and the polysilicon of the semiconductor substrate surface outside the polysilicon gate 6
The hard mask layers 7 at 6 top of grid and second nitridation for being coated on 7 top surface of hard mask layers and side
Silicon layer 8；Second silicon nitride layer 8 of the side of the polysilicon gate 6, which remains, is not modified processing；It is described to be modified processing
Silicon nitride can be removed by diluted hydrofluoric acid (DHF), the silicon nitride for not being modified processing cannot be removed by DHF.
In Fig. 2 B, the ion implanting of the moditied processing is as shown in the corresponding arrow line of label 101.The moditied processing
Ion implanting is vertical injection.In present invention method, the ion of the ion implanting of the moditied processing be light ion such as
Hydrogen ion.
Second silicon nitride layer for being modified processing is individually indicated with label 8a, is modified the hardmask of processing
Layer is individually indicated with label 7a.
Step 4: as shown in Figure 2 C, using DHF remove described in be modified the silicon nitride of processing, it is described not to be modified processing
Silicon nitride be retained in the polysilicon gate 6 side formed first layer side wall 8b, the top surface of the first layer side wall 8b
Lower than the top surface for being equal to the polysilicon gate 6, to eliminate since the first layer side wall 8b is projected into the polysilicon
The top surface of grid 6 and the Fence structure formed.
Step 5: as shown in Figure 2 D, be formed with the polysilicon gate 6 of the first layer side wall 8b side formed by
The second layer side wall 9 of third silicon nitride layer composition.
It is preferably selected as, the second layer side wall 9 carries out autoregistration dry method using third silicon nitride layer is first grown again later
Etching forms the second layer side wall 9.
It further comprises the steps of:
Step 6: as shown in Figure 2 E, using epitaxial growth technology in the polysilicon for being formed with the second layer side wall 9
The semiconductor substrate surface outside grid 6 forms semiconductor epitaxial layers 10.
It further include to the semiconductor substrate surface before the epitaxial growth technology for carrying out the semiconductor epitaxial layers 10
The step of being cleaned.The semiconductor epitaxial layers 10 are silicon epitaxy layer.
Step 7: forming source region and drain region in the semiconductor epitaxial layers 10 of 6 two sides of polysilicon gate.
The embodiment of the present invention is formed by the second silicon nitride layer 8 of atom layer deposition process formation in 6 side of polysilicon gate
Later, the moditied processing that a step carries out silicon nitride using ion implantation technology is increased, the nitrogen for being ion implanted modified is utilized
The characteristics of silicon nitride that SiClx can not be ion implanted modified by DHF removal will not be removed by DHF, in conjunction with subsequent DHF
Removal technique autoregistration all removes the silicon nitride except 6 side of polysilicon gate, and will be retained in the second of 6 side of polysilicon gate
Silicon nitride layer 8 is used as first layer side wall 8b；Hard mask layers 7 are all within the scope of whole thickness due to being located at the top of polysilicon gate 6
Be ion implanted modified, the hard mask layers 7 at 6 top of polysilicon gate together with the top surface for being coated on hard mask layers 7 and
Second silicon nitride layer 8 of side can all be removed by DHF, so being resistant to avoid being projected into being surrounded by side wall for 6 top of polysilicon gate
Fence formation, so, the embodiment of the present invention can to 6 side of polysilicon gate outside using ALD deposition silicon nitride carry out very
Good removal avoids forming silicon nitride spacer fence at the top of polysilicon gate 6.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of manufacturing method of side wall, which comprises the steps of:
Step 1: gate dielectric layer and polysilicon gate are formed in semiconductor substrate surface, in the top surface shape of the polysilicon gate
At by the hard mask layers being made of the first silicon nitride layer；
Step 2: forming the second silicon nitride layer using atom layer deposition process, second silicon nitride layer is covered on the polycrystalline
The semiconductor substrate surface outside the side of Si-gate and the polysilicon gate and the top for being coated on the hard mask layers
Portion surface and side；
Step 3: carrying out the moditied processing of silicon nitride using ion implantation technology, it includes described more for being modified the silicon nitride of processing
Second silicon nitride layer and the hard at the top of the polysilicon gate of the semiconductor substrate surface outside crystal silicon grid
Mask layer and second silicon nitride layer for being coated on the hard mask layers top surface and side；The polysilicon gate
Second silicon nitride layer of side, which remains, is not modified processing；The silicon nitride for being modified processing can be removed by DHF, not
The silicon nitride for being modified processing cannot be removed by DHF；
Step 4: using DHF remove described in be modified the silicon nitride of processing, the silicon nitride for not being modified processing is retained in institute
The side for stating polysilicon gate forms first layer side wall, and the top surface of the first layer side wall is lower than equal to the polysilicon gate
Top surface, to eliminate due to the fence knot that the first layer side wall is projected into the top surface of the polysilicon gate and is formed
Structure.
2. the manufacturing method of side wall as described in claim 1, which is characterized in that further include following steps:
Step 5: be made of in the side formation for being formed with the polysilicon gate of the first layer side wall third silicon nitride layer
Second layer side wall.
3. such as the manufacturing method for the side wall that claim 2 is stated, it is characterised in that: the second layer side wall is using first growth third nitrogen
SiClx layer carries out autoregistration dry etching again later and forms the second layer side wall.
4. such as the manufacturing method for the side wall that claim 1 is stated, it is characterised in that: the ion implanting of moditied processing described in step 3
Ion be hydrogen ion.
5. such as the manufacturing method for the side wall that claim 1 is stated, it is characterised in that: in step 2, be located at the top of the polysilicon gate
The hard mask layers and the superposition thickness of second silicon nitride layer be less than or equal to
6. such as the manufacturing method for the side wall that claim 2 is stated, it is characterised in that: semiconductor substrate described in step 1 uses SOI
Substrate, the SOI substrate include lower bulk silicon, buries oxide layer and top silicon layer.
7. the manufacturing method for the side wall stated such as claim 6, it is characterised in that: the corresponding transistor of the polysilicon gate is SOTB
Transistor；The gate dielectric layer is formed on the top silicon layer surface.
8. such as the manufacturing method for the side wall that claim 7 is stated, it is characterised in that: the gate dielectric layer is gate oxide.
9. such as the manufacturing method for the side wall that claim 7 is stated, it is characterised in that: be formed with oxygen on the semiconductor substrate
Layer, isolates active area by the field oxygen layer.
10. such as the manufacturing method for the side wall that claim 9 is stated, it is characterised in that: the field oxygen layer is using shallow trench isolation work
Skill is formed.
11. such as the manufacturing method for the side wall that claim 7 is stated, it is characterised in that: further comprised the steps of: after step 5
Step 6: the semiconductor using epitaxial growth technology outside the polysilicon gate for being formed with the second layer side wall
Substrate surface forms semiconductor epitaxial layers.
12. such as the manufacturing method for the side wall that claim 11 is stated, it is characterised in that: in the extension for carrying out the semiconductor epitaxial layers
Further include the steps that cleaning the semiconductor substrate surface before growth technique.
13. such as the manufacturing method for the side wall that claim 11 is stated, it is characterised in that: the semiconductor epitaxial layers are silicon epitaxy layer.
14. such as the manufacturing method for the side wall that claim 11 is stated, it is characterised in that: further comprised the steps of: after step 6
Step 7: forming source region and drain region in the semiconductor epitaxial layers of the polysilicon gate two sides.
15. such as the manufacturing method for the side wall that claim 1 is stated, it is characterised in that: the ion of moditied processing described in step 3 is infused
Enter for vertical injection.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111599816A (en) * | 2020-05-28 | 2020-08-28 | 上海华力集成电路制造有限公司 | Method for improving line width difference of grid etching process in SADP process |
| CN111799225A (en) * | 2020-09-08 | 2020-10-20 | 中芯集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device |
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| CN104241119A (en) * | 2014-09-24 | 2014-12-24 | 上海华力微电子有限公司 | Preparation method of dual contact hole etching stop layer |
| CN105161463A (en) * | 2014-05-30 | 2015-12-16 | 华邦电子股份有限公司 | Method of reducing Vt shift of memory cell |
| CN109524299A (en) * | 2018-11-22 | 2019-03-26 | 上海华力微电子有限公司 | The manufacturing method of gate structure |
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2019
- 2019-06-03 CN CN201910476405.5A patent/CN110277313B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110156099A1 (en) * | 2009-12-30 | 2011-06-30 | Jan Hoentschel | Enhanced confinement of sensitive materials of a high-k metal gate electrode structure |
| CN105161463A (en) * | 2014-05-30 | 2015-12-16 | 华邦电子股份有限公司 | Method of reducing Vt shift of memory cell |
| CN104241119A (en) * | 2014-09-24 | 2014-12-24 | 上海华力微电子有限公司 | Preparation method of dual contact hole etching stop layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111599816A (en) * | 2020-05-28 | 2020-08-28 | 上海华力集成电路制造有限公司 | Method for improving line width difference of grid etching process in SADP process |
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| CN110277313B (en) | 2021-04-13 |
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