TWI755545B - Semiconductor structure including isolations and method for manufacturing the same - Google Patents

Abstract

A method for manufacturing a semiconductor structure including isolations includes receiving a substrate including a first region and a second region; forming a patterned hard mask, the patterned hard mask including a first opening exposing a portion of the first region and a second opening exposing a portion of the second region; removing portions of the substrate to form a first trench in the first region and to form a second trench in the second region; performing an ion implantation to a portion of the patterned hard mask in the first region and a portion of the substrate exposed from the first trench; enlarging the first opening to form a third opening over the first trench and enlarging the second opening to form a fourth opening over the second trench; and forming a first isolation by filling the first trench and a second isolation by filling the second trench.

Description

Semiconductor structure including isolation structure and method of making the same

Embodiments of the present invention relate to a semiconductor structure including an isolation structure and a method for fabricating the same.

In today's integrated circuit industry, hundreds of semiconductor devices are built on a single wafer. Each device on the wafer must be electrically isolated to ensure that they operate independently without interfering with each other. The technique of isolating semiconductor devices has become an important aspect of modern semiconductor technology for separating different devices or different functional areas. In the case of highly integrated semiconductor devices, improper electrical isolation in the device will cause current leakage, and current leakage can consume large amounts of power and compromise functionality. Latch-up (which can temporarily or permanently damage a circuit), noise margin degradation, voltage skew, and crosstalk are some examples of reduced functionality. Shallow trench isolation (STI) is one of the preferred electrical isolation techniques for highly integrated semiconductor wafers. Broadly speaking, STI technology involves forming shallow trenches in isolation regions or regions of a semiconductor wafer. The shallow trenches are then filled with a dielectric material, such as silicon dioxide, to provide electrical isolation between devices subsequently formed in active regions on either side of the filled trenches.

One embodiment of the present invention relates to a method for fabricating a semiconductor structure, comprising: receiving a substrate; forming a patterned hard mask over the substrate, the patterned hard mask including at least one first opening; at least one trench is formed in the substrate through the first opening of the patterned hard mask, and at least a portion of the substrate is exposed from the trench; the patterned hard mask and the substrate exposed from the trench performing an ion implantation on the portion to form a doped region in the substrate; enlarging the first opening by removing a portion of the patterned hard mask to form a second opening over the trench; and An isolation structure is formed by filling the trench. One embodiment of the present invention relates to a method for fabricating a semiconductor structure, comprising: receiving a substrate including a first region and a second region defined thereon; forming a patterned hard disk over the substrate a mask, the patterned hard mask includes a first opening exposing a part of the first area and a second opening exposing a part of the second area; removing a part of the substrate to pass through the first opening in the A first trench is formed in the first region and a second trench is formed in the second region through the second opening; a portion of the patterned hard mask in the first region and a portion of the patterned hard mask in the first region and from the first performing an ion implantation on a portion of the substrate exposed by the first trench in the region; enlarging the first opening to form a third opening over the first trench and enlarging the second opening to overlie the second trench A fourth opening is formed above the trench; and a first isolation structure filling the first trench and a second isolation structure filling the second trench are formed. An embodiment of the present invention relates to a semiconductor structure comprising: a substrate including a first region and a second region defined thereon, wherein the substrate includes a first material; a first isolation structure, It includes a first width in the first region; a second isolation structure includes a second width in the second region; and a region surrounds the first isolation structure in the substrate and includes the a first material and a second material, wherein the first width is greater than the second width, a bottom and sidewalls of the first isolation structure are in contact with the region, and a bottom and sidewalls of the second isolation structure are in contact with the substrate .

The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description a first member is formed over or on a second member may include embodiments in which the first member and the second member are formed in direct contact, and may also include embodiments in which additional members may be An embodiment is formed between the first member and the second member so that the first member and the second member may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and/or configurations discussed. Furthermore, for ease of description, spatially relative terms such as "below", "below", "under", "above", "on", "on" and the like may be used herein to describe the relationship of one element or component to another element(s) or component, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As used herein, terms such as "first,""second," and "third," describe various elements, components, regions, layers and/or sections. or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Terms such as "first,""second," and "third" when used herein do not imply a sequence or order unless the context clearly dictates otherwise. As used herein, the terms "approximately,""substantially,""substantially," and "approximately" are used to describe and take into account minor variations. When used in conjunction with an event or circumstance, these terms can refer to the instance in which the event or circumstance occurs exactly as well as the instance in which the event or circumstance approximately occurs. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, Less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1% or less than or equal to ±0.05%. For example, if the difference between two values is less than or equal to ±10% of the mean of one of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, such values may be considered "substantially" the same or equal. For example, "substantially" parallel may refer to an angular variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±3° equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1° or less than or equal to ±0.05°. For example, "substantially" vertical may refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±3° equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1° or less than or equal to ±0.05°. While CMOS scaling has enabled circuit and system designers to pack a large amount of functionality onto a silicon die, it simultaneously creates a number of significant problems with the chip's ability to interface with the outside world. This is especially true in the field of analog/digital mixed-signal chips. For example, the devices in the analog area contain larger sizes than the devices in the logical core area. Similarly, isolation structures that provide electrical isolation between devices in the analog region include larger sizes than the isolation structures in the logic core region. In addition, STIs typically include a step or a divot at the intersection between the semiconductor substrate and the STI fill material. The electric field is concentrated at the location where the polysilicon film (which forms the gate of the transistor device) extends over the step. The concentrated electric field lowers the threshold voltage Vt at the corners of the transistor devices. Therefore, the dip problem can cause unwanted noise in analog circuits. However, isolation structures of different sizes are formed at the same time. The problem of dealing with recesses in the analog region can be attributed to the isolation structures being susceptible to program damage during operation to adversely affect the STI in another region, such as the logic core region. In other words, it is difficult to modify or adjust operations for forming isolation structures in the analog region without affecting other isolation structures in another region, such as the logical core region. The present disclosure thus provides a method for fabricating a semiconductor structure including an isolation structure that alleviates the recess problem. In some embodiments, the present disclosure provides a method for fabricating a semiconductor structure including an isolation structure that alleviates the recess problem in one region while other isolation structures in another region are not affected by such operations. Therefore, the isolation structures of different sizes are improved and meet their respective design requirements. 1 is a flowchart illustrating a method 10 for fabricating a semiconductor structure including an isolation structure in accordance with aspects of the present disclosure. The method 10 for fabricating a semiconductor structure including an isolation structure includes operation 102, receiving a substrate. The method 10 further includes an operation 104 of forming a patterned hard mask over the substrate, the patterned hard mask including at least one first opening. The method 10 further includes an operation 106 of forming at least one trench in the substrate through the first opening of the patterned hard mask, and exposing at least a portion of the substrate from the trench. The method 10 further includes an operation 108 of performing an ion implantation on the patterned hard mask and the substrate exposed from the trench to form a doped region in the substrate. The method 10 further includes an operation 110 of enlarging the first opening by removing a portion of the patterned hard mask to form a second opening over the trench. The method 10 further includes an operation 112 of forming an isolation structure by filling the trench. Method 10 is further described in accordance with one or more embodiments. It should be noted that the operation of method 10 may be reconfigured or otherwise modified within the scope of the various aspects. It should be further noted that additional procedures may be provided before, during, and after method 10, and that some other procedures may only be briefly described herein. Accordingly, other implementations are possible within the scope of the aspects described herein. 2 is a flowchart illustrating a method 20 for fabricating a semiconductor structure including an isolation structure according to aspects of the present disclosure. The method 20 for fabricating a semiconductor structure including an isolation structure includes operation 202, receiving a substrate including a first region and a second region defined thereon. Method 20 further includes operation 204 of forming a patterned hard mask over the substrate, the patterned hard mask comprising a first opening exposing a portion of the first region and exposing a second opening of a portion of the second region Open your mouth. Method 20 further includes operation 206, removing a portion of the substrate to form a first trench in the first region through the first opening and a second trench in the second region through the second opening. Method 20 further includes operation 208 of performing an ion implant on a portion of the patterned hard mask in the first region and a portion of the substrate exposed from the first trench in the first region. The method 20 further includes an operation 210 of enlarging the first opening to form a third opening over the first trench and enlarging the second opening to form a fourth opening over the second trench. The method 20 further includes an operation 212 of forming a first isolation structure by filling the first trench and forming a second isolation structure by filling the second trench. Method 20 will be further described in accordance with one or more embodiments. It should be noted that the operation of method 20 may be reconfigured or otherwise modified within the scope of the various aspects. It should be further noted that additional procedures may be provided before, during, and after method 20, and some other procedures may only be briefly described herein. Accordingly, other implementations are possible within the scope of the aspects described herein. 3A-3J are schematic diagrams illustrating a semiconductor structure 30 including an isolation structure at various stages of fabrication constructed in accordance with aspects of the present disclosure in one or more embodiments. Referring to FIG. 3A , a substrate 300 is received or provided according to operation 102 . In some embodiments, the substrate 300 includes silicon (Si). In some embodiments, other common materials such as carbon (C), germanium (Ge), gallium (Ga), arsenic (As), nitrogen (N), indium (In) and/or phosphorus (P) and the like ) may also be included in the substrate 300 . A liner layer 304 may be formed on the substrate 300 . Next, a patterned hard mask 306 is formed over the substrate 300 according to operation 104 . The liner layer 304 may be a thin film including, for example, silicon oxide (SiO) formed using a thermal oxidation process. The liner layer 304 can act as an adhesion layer between the substrate 300 and the patterned hard mask 306 . The liner layer 304 may also act as an etch stop layer for etching the patterned hard mask 306 and as a buffer layer to buffer stress from the patterned hard mask 306 . In some embodiments, the patterned hard mask 306 includes silicon nitride (SiN). In some embodiments, the patterned hard mask 306 includes at least one first opening 308 as shown in FIG. 3A. Referring to FIG. 3B , at least one trench 310 is formed in the substrate 300 by patterning the first opening 308 of the hard mask 306 according to operation 106 . As shown in FIG. 3B , at least a portion of substrate 300 is exposed from trench 310 . The trench 310 defines a width W1. In some embodiments, the width W1 of the trench 310 may be between 1 micrometer (μm) and 10 μm, but the present disclosure is not limited thereto. Referring to FIG. 3C , an ion implant 320 is performed on the patterned hard mask 306 and the portion of the substrate 300 exposed from the trenches 310 according to operation 108 . In addition, ion implantation 320 is performed to form a doped region 330 in the substrate 300 . In some embodiments, as shown in Figure 3C, ion implantation 320 is performed at an oblique angle. In some embodiments, the ion implantation 320 includes implanting N, but the present disclosure is not so limited. In some embodiments, the ion implantation 320 includes implanting heavy ions having an atomic mass greater than one atomic mass of the substrate 300 or an atomic mass greater than 30 amu, but the present disclosure is not limited thereto. For example, the heavy ions may include Ge or Ar, but the present disclosure is not limited thereto. Heavy ions, such as Ge, for example, cause a substantial lattice disruption in the substrate 300 exposed from the trenches 310, thereby causing portions of the substrate 300 to amorphize. Accordingly, a doped region 330, which may be an amorphized region, is formed in the substrate 300 along the sidewalls and a bottom of the trench 310, as shown in FIG. 3C. In some embodiments, the doped region 330 or the amorphized region defines a depth, and the depth is between about 50 angstroms (Å) and about 200 Å, although the present disclosure is not limited thereto. Furthermore, ion implantation 320 damages patterned hardmask 306, and thus the physical and/or chemical properties of patterned hardmask 306 are altered or altered, and a patterned hardmask implanted by ion implantation 320 is obtained 307. In some embodiments, patterned hardmask 306 includes an original etch rate relative to an etchant, and patterned hardmask 307 includes an altered etch rate relative to one of the etchants. In some embodiments, due to damage caused by ion implantation 320, the altered etch rate is greater than the original etch rate. Referring to FIG. 3D , in some embodiments, an enlarged second opening 309 over trench 310 is formed through a pullback process 322 according to operation 110 . _In some embodiments, the retraction 322 is performed with an etchant, such as _H3PO4 , although the present disclosure is not so limited. Thus, the first opening 308 and the second opening 309 include a width difference "d", as shown in FIG. 3D. Referring to FIG. 3E , in some embodiments, an oxidation and thermal operation 324 may be performed after the pullback 322 . In some embodiments, the oxidation and thermal operation 324 repairs the damage at the surface of the doped region 330 exposed from the trench 310 caused by the retraction 322 . Furthermore, the lattice damage of doped regions 330 damaged by ion implantation 320 can be repaired by thermal operation 324, and thus a doped region 332 with a repaired lattice is obtained. In some embodiments, the doped region 320 (which was previously an amorphized region) may be fully recrystallized by thermal operation 324 . In some embodiments, an oxide liner (not shown) is formed over the surfaces of doped regions 332 exposed from trenches 310 . Please refer to Figure 3F. Next, operation 112 is performed to form an isolation structure 342 by filling the trenches 310 . In some embodiments, the trench filling process may include forming an insulating material 340 to fill trench 310 after thermal operation 324 . In some embodiments, a planarization operation may be performed such that a top surface of insulating material 340 is substantially flush with a top surface of patterned hard mask 307 . Referring to FIG. 3G , a portion of insulating material 340 is then removed to form isolation structure 342 such that a top surface of isolation structure 342 becomes lower than the top surface of patterned hard mask 307 . Still referring to FIG. 3G , the width W2 of the upper portion of the isolation structure 342 (ie, the portion occupying the second opening 309 ) is greater than the width W1 of the lower portion of the isolation structure 342 (ie, the portion that fills the trench 310 ). Referring to Figure 3H, the patterned hard mask 307 is then removed. Thus, liner layer 304 and isolation structures 342 are exposed as shown in Figure 3H. In some embodiments, well implantation and annealing may be performed to form n-wells or p-wells in substrate 300 . It should be readily understood that the conductivity type, implant concentration, and implant energy of well implants depend on different well requirements, so these details are omitted for brevity. In some embodiments, isolation structure 342 includes a lower portion in trench 310 and an upper portion above a surface line 300L of substrate 300 . The lower portion includes width W1, the upper portion includes width W2, and the width difference d between width W1 and width W2 is obtained, as shown in FIG. 3H. Referring to Figure 3I, the liner layer 304 is then removed. In some embodiments, sacrificial oxide formation and removal may be performed repeatedly to repair the exposed surface of substrate 300 . Accordingly, portions of isolation structures 342 may be consumed or removed. Due to the width difference d between the widths W1 and W2 , the insulating material 340 of the isolation structures 342 may be consumed without causing recesses around the top corners of the isolation structures 342 . Referring to FIG. 3J , a gate structure 350 may be formed over the substrate 300 . In some embodiments, a gate dielectric layer (not shown) may be formed over substrate 300 and then a gate conductive layer (not shown) formed thereon. A patterning operation is then performed to form a gate structure 350 including the gate dielectric layer and the gate conductive layer. The width difference d can easily be increased by performing ion implantation 320 according to the method described above. Therefore, the recessing problem at the interface between the substrate 300 and the top corners of the isolation structures 342 can be alleviated and thus the performance of the device can be improved. 4A-4J are schematic diagrams illustrating a semiconductor structure including isolation structures at various stages of fabrication constructed in accordance with aspects of the present disclosure, in one or more embodiments. It should be readily understood that the same elements in FIGS. 4A-4J and 3A-3J may comprise the same materials, and thus such details are omitted for brevity. Referring to FIG. 4A , a substrate 400 is received or provided according to operation 202 . In some embodiments, according to operation 202, the substrate 400 includes a first region 402a and a second region 402b. The first area 402a and the second area 402b can be different functional areas, such as a memory area (such as an embedded static random access memory (SRAM) area), an analog area, an input/output (also known as a peripheral device) ) area, a dummy area (for forming a dummy pattern), and one of the like. The device regions cited above are also schematically depicted in FIGS. 5 and 6 . In an exemplary embodiment, the first area 402a is an analog area, and the second area 402b is a logical core area, but the present disclosure is not limited thereto. Still referring to FIG. 4A , a liner layer 404 may be formed on the substrate 400 . Next, a patterned hard mask 406 is formed over the substrate 400 according to operation 204 . As mentioned above, the liner layer 404 may serve as an adhesion layer between the substrate 400 and the patterned hard mask 406 . The liner layer 404 may also act as an etch stop layer for etching the patterned hard mask 406 and as a buffer layer to buffer stress from the patterned hard mask 406 . In some embodiments, according to operation 204, the patterned hard mask 406 includes at least a first opening 408a exposing a portion of the first region 402a and a second opening 408b exposing a portion of the second region 402b. Referring to FIG. 4B , a portion of substrate 400 is removed according to operation 206 . In some embodiments, a first trench 410a is formed in the first region 402a through the first opening 408a of the patterned hard mask 406 and in the second region 402b through the second opening 408b of the patterned hard mask 406 A second trench 410b is formed. Therefore, a portion of the substrate 400 is exposed from the first trench 410a, and a portion of the substrate 400 is exposed from the second trench 410b. In some embodiments, a depth of the first trench 410a and a depth of the second trench 410b may be substantially the same, but the present disclosure is not limited thereto. In addition, the first trench 410a defines a width Wa1 and the second trench 410b defines a width Wb1. In some embodiments, the width Wa1 of the first trench 410a and the width Wb1 of the second trench 410b may be substantially the same. In some embodiments, the width Wa1 of the first trench 410a may be different from the width Wb1 of the second trench 410b. In some embodiments, when the first region 402a is an analog region and the second region 402b is a logic core region, the width Wa1 of the first trench 410a may be greater than the width Wb1 of the second trench 410b. In some embodiments, a ratio of width Wa1 to width Wb1 may be between about 10 and about 500, although the present disclosure is not limited thereto. For example, the width Wa1 of the first trench 410a is between 1 μm and 10 μm, and the width Wb1 of the second trench 410b is between 20 nanometers (nm) and 100 nm, but the present disclosure does not limited to this. In other words, in some embodiments, the width Wa1 of the first trench 410a may be much larger than the width Wb1 of the second trench 410b. However, the width Wb1 of the second trench 410b is exaggerated in FIGS. 4A-4J for the purpose of clearly showing the components. Referring to FIG. 4C , next, a protective layer 401 is formed on the substrate 400 . Specifically, the protective layer 401 is formed over the second region 402b and leaves the first region 402a exposed. In some embodiments, the protective layer 401 includes a photoresist, but the present disclosure is not limited thereto. After forming the protective layer 401 , an ion implantation 420 is performed according to operation 208 . Ion implantation 420 is performed on a portion of the patterned hard mask 406 in the first region 402a and a portion of the substrate 400 exposed from the first trench 410a in the first region 402a. In some embodiments, as shown in Figure 4C, ion implantation 420 is performed at an oblique angle. In some embodiments, the ion implantation 420 includes implanting N, but the present disclosure is not so limited. In some embodiments, the ion implantation 420 includes implanting heavy ions having an atomic mass greater than one atomic mass of the substrate 400 or an atomic mass greater than 30 amu, although the present disclosure is not limited thereto. For example, the heavy ions may include Ge or Ar, but the present disclosure is not limited thereto. Heavy ions, such as Ge, for example, create a substantial lattice disruption in substrate 400, thereby causing portions of substrate 400 to amorphize. Accordingly, a doped region 430, which may be an amorphized region, is formed in the substrate 400 along the sidewalls and a bottom of the first trench 410a, as shown in FIG. 4C. In some embodiments, the doped region 430 or the amorphized region defines a depth, and the depth is between about 50 Å and about 200 Å, although the present disclosure is not limited thereto. Furthermore, the ion implantation 420 damages the portion of the patterned hard mask 406 in the first region 402a that is exposed from the protective layer 401, thus changing the physical and/or chemical properties of the portion of the patterned hard mask 406 in the first region 402a Or alternatively, a patterned hard mask 407 implanted by ion implantation 420 is formed. In some embodiments, the physical and/or chemical properties of the implanted patterned hardmask 407 may be different from the physical and/or chemical properties of the patterned hardmask 406 protected by the protective layer 401 in the second region 402b chemical properties. In some embodiments, the patterned hard mask 407 in the first region 402a thus after ion implantation 420 includes a first etch rate relative to an etchant, the patterned hard mask 406 in the second region 402b A second etch rate relative to the etchant is included after ion implantation 420. More importantly, the first etch rate of the patterned hard mask 407 in the first region 402a is greater than the second etch rate of the patterned hard mask 406 in the second region 402b. Referring to FIG. 4D , the protective layer 401 is removed after the ion implantation 420 is performed. Next, an enlarged third opening 409a over the first trench 410a is formed through a pullback 422 and an enlarged fourth opening 409b over the second trench 410b is formed through a pullback 422 according to operation 210 . _In some embodiments, the retraction 422 is performed with an etchant, such as _H3PO4 , although the present disclosure is not so limited. As mentioned above, since the etch rate of the patterned hardmask 407 in the first region 402a is greater than the etch rate of the patterned hardmask 406 in the second region 402b, the self-patterned hardmask even using the same etchant The portion of the mask 407 removed is also greater than the portion removed from the patterned hard mask 406 . Therefore, the first opening 408a and the third opening 409a define a width difference "da1", the second opening 408b and the fourth opening 409b define a width difference "db1", and the width difference da1 is greater than the width difference db1, as shown in FIG. 4D exhibit. In some embodiments, the pullback 422 is referred to as a double pullback or double pullback 422 because the pullback 422 is performed to obtain at least two width differences simultaneously (width difference da1 and width difference db1 ). Referring to FIG. 4E , in some embodiments, an oxidation and thermal operation 424 may be performed after the double back-off 422 . In some embodiments, oxidation and thermal operation 424 repairs damage caused by double pullback 422 at the surface of substrate 400 exposed from second trench 410b and the surface of doped region 430 exposed from first trench 410a . Furthermore, the lattice damage of the doped region 430 damaged by the ion implantation 420 can be repaired by the thermal operation 424, and thus a doped region 432 with a repaired lattice is obtained. In some embodiments, doped region 430 (which was previously an amorphized region) may be fully recrystallized by thermal operation 424 . In some embodiments, an oxide liner (not shown) is formed over the surface of the doped region 432 exposed from the first trench 410a and the surface of the substrate 400 exposed from the second trench 410b. Please refer to Figure 4F. Next, operation 212 is performed to form a first isolation structure 442a by filling the first trench 410a and a second isolation structure 442b by filling the second trench 410b. In some embodiments, the trench filling process may include forming an insulating material 440 to fill the first trench 410a and the second trench 410b after the thermal operation 424 . In some embodiments, a planarization operation may be performed such that a top surface of insulating material 440 is substantially flush with a top surface of patterned hard mask 406 and a top surface of patterned hard mask 407 . Referring to FIG. 4G , then, a portion of the insulating material 440 is removed so that a top surface of the insulating material 440 is lower than the top surface of the patterned hard mask 406 and the top surface of the patterned hard mask 407 . As shown in FIG. 4G, the width Wa2 of the upper portion of the first isolation structure 442a (ie, the portion occupying the third opening 409a) is greater than the width Wa2 of the lower portion of the first isolation structure 442a (ie, the portion filling the first trench 410a) The width Wa1. And the width Wb2 of the upper portion of the second isolation structure 442b (ie the portion occupying the fourth opening 409b ) is greater than the width Wb1 of the lower portion of the second isolation structure 442b (ie the portion filling the second trench 410b ). However, because the width difference da1 is greater than the width difference db1 , a width difference da2 between the width Wa1 and the width Wa2 is greater than a width difference db2 between the width Wb1 and the width Wb2 , as shown in FIG. 4G . Referring to Figure 4H, the patterned mask 407 is then removed. Thus, the liner layer 404, the first isolation structure 442a, and the second isolation structure 442b are exposed as shown in FIG. 4H. In some embodiments, different well implantation and annealing may be performed. For example, when the second region 402b is a logical core region, an n-type core well implant or a p-type core well implant and an anneal may be performed to form an n-well or a p-well in the second region 402b. For example, when the second region 402b is an analog region, an n-type logic well implant or a p-type logic well implant and an anneal may be performed to form an n-well or p-well in the first region 402a. It should be readily understood that the conductivity type, implant concentration, and implant energy of well implants depend on different well requirements, so these details are omitted for brevity. In some embodiments, the first isolation structure 442a includes a lower portion in the first trench 410a and an upper portion above a surface line 400L of the substrate 400 . The lower portion includes a width Wa1, and the upper portion includes a width Wa2. Similarly, the second isolation structure 442b includes a lower portion in the second trench 410b and an upper portion above the surface line 400L of the substrate 400 . The lower part contains width Wb1 and the upper part contains width Wb2. As mentioned above, the width difference da2 between the width Wa1 and the width Wa2 is greater than the width difference db2 between the width Wb1 and the width Wb2, as shown in FIG. 4H . Referring to Figure 4I, the liner layer 404 is then removed. In some embodiments, the sacrificial oxide formation and removal may be repeatedly performed to repair the exposed surface of the substrate 400 . Accordingly, portions of the first isolation structures 442a and portions of the second isolation structures 442b may be removed. As mentioned above, the ratio of width Wa1 to width Wb1 is between about 50 and about 100, so the micro-loading effect can cause different etching results in the first region 402a and the second region 402b. For example, due to the micro-loading effect, the first isolation structure 442a (which includes the larger widths Wa1 and Wa2) consumes more than the second isolation structure 442b. However, since the width difference da2 between the widths Wa1 and Wa2 is greater than the difference db2 between the widths Wb1 and Wb2, the insulating material 440 may be consumed without causing the top corners of the first isolation structures 442a to be recessed. In some embodiments, a top portion of the first isolation structure 442a is different from a top portion of the second isolation structure 442b. For example, recesses may be formed around the top corners of the second isolation structures 442b. In other embodiments, the insulating material 440 may also be consumed without causing recesses around the top corners of the second isolation structures 442b. Referring to FIG. 4J, a first gate structure 450a may be formed in the first region 402a and a second gate structure 450b may be formed in the second region 402b. In some embodiments, a gate dielectric layer (not shown) may be formed over substrate 400 and then a gate conductive layer (not shown) formed thereon. A patterning operation is then performed to form a first gate structure 450a including the gate dielectric layer and the gate conductive layer in the first region 402a. At the same time, a second gate structure 450b including the gate dielectric layer and the gate conductive layer is formed in the second region 402b. In some embodiments, because the first gate structure 450a and the second gate structure 450b are formed in different regions for different devices, the width of the first gate structure 450a may be different from the width of the second gate structure 450b , but this disclosure is not limited to this. In some embodiments, a semiconductor structure 40 is formed as shown in FIG. 4J. The semiconductor structure 40 includes: a substrate 400 including a first region 402a and a second region 402b defined thereon; a first isolation structure 442a in the substrate 400 in the first region 402a; a second isolation structure 442b, It is in the second region 402b in the substrate 400; and a doped region 432, which surrounds the first isolation structure 442a in the substrate 400. In some embodiments, the semiconductor structure 40 further includes a first gate structure 450a positioned over the first region 402a and a second gate structure 450b positioned over the second region 402b. As mentioned above, the first area 402a and the second area 402b may be one of different functional areas, such as a logical core area, a memory area, an analog area, an input/output area, a dummy area, and the like. In an exemplary embodiment, the first area 402a is an analog area, and the second area 402b is a logical core area, but the present disclosure is not limited thereto. In some embodiments, the composition of region 432 and substrate 400 may be different. For example, substrate 400 includes a first material, such as Si, and region 432 includes the same first material as substrate 400 and a second material, such as Ge, N, or Ar. In some embodiments, the second material has an atomic mass greater than an atomic mass of the first material. In some embodiments, a bottom and sidewalls of the first isolation structure 442a are in contact with the region 432 and a bottom and sidewalls of the second isolation structure 442b are in contact with the substrate 440, as shown in FIG. 4J. In some embodiments, the doped regions 432 contain heavy ions. For example, the doped region 432 may include Ge, N or Ar, but the present disclosure is not limited thereto. In some embodiments, the width Wa1 of the first isolation structure 442a is greater than the width Wb1 of the second isolation structure 442b. Still referring to FIG. 4J, in some embodiments, a top portion of the first isolation structure 442a is different from a top portion of the second isolation structure 442b. For example, the second isolation structure 442b includes a recess around a top corner and the first isolation structure 442a includes an unrecessed top corner. Still referring to FIG. 4J, it should be noted that the first gate structure 450a extends over the top portion of the first isolation structure 442a and the second gate structure 450b extends over the top portion of the second isolation structure 442b. Because the first isolation structure 442a includes a non-recessed top corner, the concentrated or concentrated electric field is relieved at the corner of a transistor device used as an analog device. The stability of the threshold voltage (Vt) at the corners of these analog devices is thus improved. Therefore, unwanted noise caused by recesses is reduced, and the performance of the analog circuit is improved by noise reduction. More importantly, the sinking problem in the first region 402a is alleviated without affecting the second region 402b, which is susceptible to damage during operation. Unlike analog devices, the logic devices in the second region 402b are configured to act as switches between on and off in order to implement the logic functionality of an integrated chip (eg, form a process that is configured to perform the logic function) device). Therefore, noise problems do not affect logic devices as they affect analog devices. Thus, in the second region 402b, the sag is acceptable or tolerable. Referring to FIG. 5, shown is a schematic diagram of a semiconductor structure 40' including isolation structures in accordance with aspects of the present disclosure, in one or more embodiments. It should be readily understood that the same elements in FIGS. 5 and 4J are designated by the same reference numerals. And the same elements in the semiconductor structure 40 and the semiconductor structure 40' may comprise the same materials and/or be formed by the same operations, so these details are omitted for brevity, and only the differences are detailed. As mentioned above, during the formation and removal of the sacrificial oxide layer, the first isolation structure 442a and the second isolation structure 442b' may be subject to consumption. Also as mentioned above, due to the width difference da2 between the width Wa1 and the width Wa2 caused by the double draw-off 422, insulation can be consumed without causing a recess around the top corner of the first isolation structure 442a Material 440. Similarly, in some embodiments, due to the width difference db2 between the widths Wb1 and Wb2 caused by the double pullbacks 422, it is possible to not cause a recess around the top corners of the second isolation structures 442b' The insulating material 440 is consumed at the bottom. Therefore, the first isolation structure 442a may include a width Wa1 larger than the width Wb1 of the second isolation structure 442b'. However, the recess problem of both the first isolation structure 442a and the second isolation structure 442b' can be alleviated. In some embodiments, both the first isolation structure 442a and the second isolation structure 442b' include a non-recessed top corner, as shown in FIG. 5 . In addition, the semiconductor structure 40 ′ still includes the doped region 432 in the first region 402 a in the substrate 400 . As shown in FIG. 5, sidewalls and a bottom of the first isolation structure 442a are in contact with the doped region 432 and sidewalls and a bottom of the second isolation structure 442b' are in contact with the substrate 400, but the present disclosure is not limited thereto. Still referring to FIG. 5, as mentioned above, the first gate structure 450a extends over the top portion of the first isolation structure 442a and the second gate structure 450b extends over the top portion of the second isolation structure 442b'. Because both the first isolation structure 442a and the second isolation structure 442b' include a non-recessed top corner, the corners of the transistor devices in both the first region 402a and the second region 402b are relieved from concentration or concentrated electric field. The stability of the threshold voltage (Vt) at the corners of these transistor devices is thus improved. Thus, unwanted noise caused by the recess problem is reduced, and the performance of analog circuits is improved, such as but not limited to, by noise reduction. In addition, the performance of logic core circuits, such as but not limited to, may be improved by improved Vt stability. Referring to FIG. 6, shown in one or more embodiments is a schematic diagram of a semiconductor device 50 including semiconductor structures 40 including isolation structures 442a and 442b in accordance with aspects of the present disclosure. It should be readily understood that the same elements in FIGS. 6 and 4J are designated by the same reference numerals. And the same elements in the semiconductor structure 40 and the semiconductor device 50 may comprise the same materials and/or be formed by the same operations, so these details are omitted for brevity, and only the differences are detailed. Still referring to FIG. 6, after forming the first gate structure 450a and the second gate structure 450b, other elements such as source/drain extensions, spacers, source/drain, and salicide may be formed (salicide) for the construction of transistor devices. In some embodiments, other devices required for different products can be formed. Thereafter, an interlayer dielectric (ILD) layer 460 is formed over the substrate 400 and contacts 462 may be formed in the ILD layer 460 . In some embodiments, an intermetal dielectric layer 470 and a back end of line (BEOL) metal 472 can be formed over the substrate 400 , and then a passivation layer 480 is formed, as shown in FIG. 6 . Thus, the semiconductor device 50 including the semiconductor structure 40 is obtained. Accordingly, the present disclosure provides a method 10 for fabricating a semiconductor structure including an isolation structure that alleviates the recess problem. In some embodiments, the present disclosure provides a method 20 for fabricating a semiconductor structure including an isolation structure that alleviates the recess problem in one region while other isolation structures in another region are not affected by such operations. Therefore, isolation structures of different sizes are improved and meet the requirements. In some embodiments, a method for fabricating a semiconductor structure including an isolation structure is provided. The method includes: receiving a substrate; forming a patterned hard mask over the substrate, the patterned hard mask including a first opening; forming at least one in the substrate through the first opening of the patterned hard mask a trench, and at least a portion of the substrate is exposed from the trench; performing an ion implantation on the patterned hard mask and the portion of the substrate exposed from the trench to form a doped region in the substrate ; enlarging the first opening by removing a portion of the patterned hard mask to form a second opening over the trench; and forming an isolation structure by filling the trench. In some embodiments, a method for fabricating a semiconductor structure including an isolation structure is provided. The method includes: receiving a substrate including a first region and a second region defined thereon; forming a patterned hard mask over the substrate, the patterned hard mask including exposing a portion of the first region a first opening and a second opening exposing a portion of the second region; removing a portion of the substrate to form a first trench in the first region through the first opening and through the second opening in A second trench is formed in the second region; an ion is performed on a portion of the patterned hardmask in the first region and a portion of the substrate exposed from the first trench in the first region implanting; enlarging the first opening to form a third opening over the first trench and enlarging the second opening to form a fourth opening over the second trench; and by filling the first trench A first isolation structure is formed and a second isolation structure is formed by filling the second trench. In some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a substrate having a first region and a second region defined thereon; a first isolation structure in the first region; a second isolation structure in the second in a region; and a region surrounding the first isolation structure in the substrate. In some embodiments, the substrate includes a first material, and the region includes the first material and a second material. The first isolation structure includes a first width, and the second isolation structure includes a second width. In some embodiments, the first width is greater than the second width. In some embodiments, a bottom and sidewalls of the first isolation structure are in contact with the region, and a bottom and sidewalls of the second isolation structure are in contact with the substrate. The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other procedures and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that these equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

10‧‧‧Method 20‧‧‧Method 30‧‧‧Semiconductor Structure 40‧‧‧Semiconductor Structure 40'‧‧‧Semiconductor Structure 50‧‧‧Semiconductor Device 102‧‧‧Operation 104‧‧‧Operation 106‧‧‧Operation 108‧‧‧Operation 110‧‧‧Operation 112‧‧‧Operation 202‧‧‧Operation 204‧‧‧Operation 206‧‧‧Operation 208‧‧‧Operation 210‧‧‧Operation 212‧‧‧Operation 300‧‧‧Substrate 300L‧‧‧Surface Line 304‧‧‧Pad Layer 306‧‧‧Patterned Hard Mask 307‧‧‧Patterned Hard Mask 308‧‧‧First Opening 309‧‧‧Enlarged Second Opening/Second Opening 310‧‧‧Trench 320‧‧‧Ion Implantation 322‧‧‧Retraction Procedure 324‧‧‧Thermal Operation 330‧‧‧Doped Region 332‧‧‧Doping Region 340‧‧‧Insulating Material 342‧‧ ‧Isolation structure 350‧‧‧Gate structure 400‧‧‧Substrate 400L‧‧‧Surface line 401‧‧‧Protective layer 402a‧‧‧First region 402b‧‧‧Second region 404‧‧‧liner layer 406‧ ‧‧Patterned hard mask 407‧‧‧Patterned hard mask 408a‧‧First opening 408b‧‧‧Second opening 409a‧‧‧Enlarged third opening 409b‧‧‧Enlarged fourth opening 410a‧ ‧‧First trench 410b‧‧‧Second trench 420‧‧‧Ion implantation 422‧‧‧Retraction/Double Retraction/Double Retraction 424‧‧‧Thermal operation 430‧‧‧Doped region 432‧ ‧‧Doping region/region 440‧‧‧Insulating material 442a‧‧‧First isolation structure 442b‧‧‧Second isolation structure 442b'‧‧‧Second isolation structure 450a‧‧‧First gate structure 450b‧‧ ‧Second Gate Structure 460‧‧‧Interlayer Dielectric (ILD) Layer 462‧‧‧Contact 470‧‧‧Intermetallic Dielectric Layer 472‧‧‧BEOL Metal 480‧‧‧Passivation Layer d‧‧‧Width difference da1‧‧‧Width difference da2‧‧‧Width difference db1‧‧‧Width difference db2‧‧‧Width difference / Difference Wa1‧‧‧Width Wa2‧‧‧Width Wb1‧‧‧Width Wb2‧‧ ‧Width W1‧‧‧Width W2‧‧‧Width

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. 1 is a flowchart illustrating a method for fabricating a semiconductor structure including an isolation structure in accordance with aspects of the present disclosure. 2 is a flowchart illustrating a method for fabricating a semiconductor structure including an isolation structure in accordance with aspects of the present disclosure. 3A-3J are schematic diagrams illustrating a semiconductor structure including isolation structures at various stages of fabrication constructed in accordance with aspects of the present disclosure in one or more embodiments. 4A-4J are schematic diagrams illustrating a semiconductor structure including isolation structures at various stages of fabrication constructed in accordance with aspects of the present disclosure, in one or more embodiments. 5 is a schematic diagram illustrating a semiconductor structure including an isolation structure in accordance with aspects of the present disclosure, in one or more embodiments. 6 is a schematic diagram illustrating a semiconductor device including a semiconductor structure including an isolation structure in accordance with aspects of the present disclosure, in one or more embodiments.

40‧‧‧Semiconductor Structure

50‧‧‧Semiconductor device

400‧‧‧Substrate

402a‧‧‧First District

402b‧‧‧Second District

432‧‧‧Doped region/region

442a‧‧‧First isolation structure

442b‧‧‧Second isolation structure

450a‧‧‧First gate structure

450b‧‧‧Second gate structure

460‧‧‧Interlayer Dielectric (ILD) Layer

462‧‧‧Contact

470‧‧‧Intermetal dielectric layer

472‧‧‧Back End-of-Line (BEOL) Metals

480‧‧‧Passivation layer

Wa1‧‧‧Width

Wb1‧‧‧Width

Claims (10)

A method for fabricating a semiconductor structure, comprising: receiving a substrate; forming a patterned hard mask over the substrate, the patterned hard mask including at least one first opening; The first opening forms at least one trench in the substrate and exposes at least a portion of the substrate from the trench; performing an ion implantation on the patterned hardmask and the portion of the substrate exposed from the trench to form a doped region in the substrate; enlarge the first opening by removing a portion of the patterned hard mask to form a second opening over the trench; and form by filling the trench an isolation structure, wherein the forming the isolation structure to fill the trench further comprises: forming an insulating material to fill the trench, wherein a top surface of the isolation structure is lower than a top surface of the patterned hard mask; and Remove the patterned hard mask. The method of claim 1, wherein the ion implantation comprises implanting germanium (Ge), nitrogen (N), or argon (Ar). The method of claim 1, further comprising performing a thermal operation prior to forming the insulating material to fill the trench. A method for fabricating a semiconductor structure, comprising: receiving a substrate including a first region and a second region defined thereon; forming a patterned hard mask over the substrate, the patterned hard mask The cover includes a first opening exposing a portion of the first region and a second opening exposing a portion of the second region; removing a portion of the substrate to form a first opening in the first region through the first opening trenching and forming a second trench in the second area through the second opening; for a portion of the patterned hard mask in the first area and from the first trench in the first area performing an ion implantation on a portion of the exposed substrate; enlarging the first opening to form a third opening over the first trench and enlarging the second opening to form a fourth opening over the second trench; and forming a first isolation structure filling the first trench and a second isolation structure filling the second trench. The method of claim 4, wherein the patterned hard mask in the first region includes a first etch rate relative to an etchant after the ion implantation, the patterned hard mask in the second region The mask includes a second etch rate relative to the etchant after the ion implantation, and the first etch rate is greater than the second etch rate. The method of claim 4, wherein the first opening and the third opening include a first width difference, the second opening and the fourth opening include a second width difference, and the first width difference is greater than the second width difference Poor width. The method of claim 4, wherein the forming the first isolation structure in the first trench and the second isolation structure in the second trench further comprises: performing a thermal operation; forming an insulating material to fill the the first trench and the second trench, and a top surface of the insulating material is lower than a top surface of the patterned hard mask; and removing the patterned hard mask. The method of claim 7, performing the ion implantation to form a doped region in the first trench. A semiconductor structure comprising: a substrate including a first region and a second region defined thereon, wherein the substrate includes a first material; a first isolation structure including in the first region a first width; a second isolation structure including a second width in the second region, wherein the second isolation structure includes a recess around a top corner; and a region surrounding the substrate The first isolation structure includes the first material and a second material, wherein the first width is greater than the second width, a bottom and sidewalls of the first isolation structure are in contact with the region, and the second isolation structure has a A bottom and sidewalls are in contact with the substrate. The semiconductor structure of claim 9, wherein the second material has an atomic mass greater than an atomic mass of the first material.

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