CN102969266A - Method for manufacturing isolation structure of shallow groove - Google Patents
Method for manufacturing isolation structure of shallow groove Download PDFInfo
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- CN102969266A CN102969266A CN2011102559967A CN201110255996A CN102969266A CN 102969266 A CN102969266 A CN 102969266A CN 2011102559967 A CN2011102559967 A CN 2011102559967A CN 201110255996 A CN201110255996 A CN 201110255996A CN 102969266 A CN102969266 A CN 102969266A
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Abstract
The invention discloses a method for manufacturing an isolation structure of a shallow groove. According to the method, specific fillers are formed before a silicon nitride protection layer is formed, the specific fillers and silicon oxide protection layers on linier silicon nitride are removed by using a chemical mechanical polishing technology, and the specific fillers in isolation grooves are removed by using a wet etching technology. Accordingly, after a silicon oxide filler layer is removed by using the chemical mechanical polishing technology, only the wet etching technology is needed to remove the silicon nitride protection layer, liner silicon nitride and liner silicon oxide, that is, only the silicon nitride and the silicon oxide are needed to be removed successively in the wet etching technology, difficulties of the wet etching technology are reduced, sinking effects at edges of the isolation grooves can be effectively improved, and the flatness of wafer surface is improved.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of fleet plough groove isolation structure manufacture method.
Background technology
Along with the process node development of semiconductor fabrication process to little live width, isolation technology between semiconductor device is also by early stage selective oxidation (Local Oxidation of Silicon, LOCOS) technological development is to shallow trench isolation from (Shallow Trench Isolation, STI) technique.Because shallow ditch groove separation process directly has influence on leakage current and other electric property between the semiconductor device on the Semiconductor substrate, thereby industry always improves the performance of fleet plough groove isolation structure by the whole bag of tricks.
Please refer to Figure 1A to Fig. 1 F, it is the generalized section of each step corresponding construction of existing a kind of fleet plough groove isolation structure manufacture method.
Shown in Figure 1A, form liner oxidation silicon (pad oxide) 120 and pad silicon nitride (pad nitride) 130 in Semiconductor substrate 110, wherein, liner oxidation silicon 120 is as the protective layer of Semiconductor substrate 110, and pad silicon nitride 130 is as the barrier layer of subsequent etching and chemico-mechanical polishing (CMP) technique;
As shown in Figure 1B, the successively described liner oxidation silicon 130 of etching, pad silicon nitride 120 and part semiconductor substrate 110, to form isolated groove 110a in described Semiconductor substrate 110, the degree of depth of described isolated groove 110a is generally between 300nm～700nm;
Shown in Fig. 1 C, utilize thermal oxidation method to form silica protective layer 140 at the inwall of described isolated groove 110a, the damage that Semiconductor substrate 110 is caused to repair etching technics, and the wedge angle (corner rounding) of sphering isolated groove 110a bottom, in this thermal oxidation process, silica protective layer that also can forming section thickness on the liner oxidation silicon 130;
Shown in Fig. 1 D, utilize chemical vapor deposition (chemical vapor deposition, CVD) technique forms silica-filled layer 150 to fill isolated groove 110a, because the characteristic of chemical vapor deposition method, also can be at the silica of the suitable thickness of silica protective layer 140 surface depositions in isolated groove 110a silicon oxide deposition;
Shown in Fig. 1 E, utilize chemico-mechanical polishing (Chemical-mechanical polishing, CMP) technology to grind the silica of removing pad silicon nitride 130 surface depositions, and stop on the pad silicon nitride 130, finally form a smooth surface;
Shown in Fig. 1 F, last, by wet-etching technology the pad silicon nitride 120 of liner oxidation silicon 130 and liner oxidation silicon 130 belows is removed, until expose the surface of Semiconductor substrate 110, so far, fleet plough groove isolation structure is completed into.
Yet, although above-mentioned fleet plough groove isolation structure manufacture method can improve performance of devices and integrated level, but when removing the pad silicon nitride 120 of liner oxidation silicon 130 and liner oxidation silicon 130 belows by wet-etching technology, because the local stress of the silica at isolated groove 110a edge and the difference of material, and wet-etching technology has isotropic characteristic, cause that different silica is had the different reasons such as etch rate, thereby cause occurring the isolated groove edge and depression (divot) phenomenon (zone shown in dotted line among Fig. 1 F) occurs, this isolated groove marginal trough phenomenon will cause a lot of negative effects to device, reduce leakage current increase etc. such as gate voltage.
In order to eliminate or to improve isolated groove marginal trough phenomenon; industry also adopts another fleet plough groove isolation structure manufacture method; the method is to change the protective layer of isolated groove inwall into double-deck protective layer structure by the silica protective layer of individual layer, and is concrete with reference to figure 2A to Fig. 2 F.
Shown in Fig. 2 A, form liner oxidation silicon 220 and pad silicon nitride 230 in Semiconductor substrate 210;
Shown in Fig. 2 B, the described liner oxidation silicon 230 of etching, pad silicon nitride 220 and part semiconductor substrate 210 are to form isolated groove 210a in described Semiconductor substrate 210;
Shown in Fig. 2 C, utilize thermal oxidation method to form silica protective layer 240 in inwall and the pad silicon nitride 230 of isolated groove 210a, follow again deposit one deck silicon nitride protective layer 260, thereby form two protective layer (the oxide/nitride double liner) structures of oxidation silicon/oxidative silicon;
Shown in Fig. 2 D, then, utilize chemical vapor deposition method to form silica-filled layer 250 to fill isolated groove 210a, also can be at the silica of the suitable thickness of silicon nitride protective layer 260 surface depositions in isolated groove 210a silicon oxide deposition, that is, be formed with the three-layer thin-film structure of silica protective layer 240, silicon nitride protective layer 260 and silica-filled layer 250 in pad silicon nitride 230;
Shown in Fig. 2 E, then, need to utilize chemical Mechanical Polishing Technique to grind the silica of removing silicon nitride protective layer 260 surface depositions, and stop on the silicon nitride protective layer 260, finally form a smooth surface;
Yet; because CMP technique is flatness and the following Semiconductor substrate of protection that reaches higher; all adopt and have higher silica to the lapping liquid of the grinding rate ratio of silicon nitride; grind when finishing like this and will be parked on the silicon nitride protective layer 260 of the superiors; for this reason; need extra wet etching step to remove successively silicon nitride protective layer 260; silica protective layer 240; pad silicon nitride 230 and liner oxidation silicon 220 (shown in Fig. 2 F); this just causes this wet-etching technology difficulty to increase; i.e. impact improves the effect of isolated groove marginal trough, is unfavorable for again the flatness of crystal column surface.
Summary of the invention
The invention provides a kind of fleet plough groove isolation structure manufacture method, improving the effect of isolated groove marginal trough, and improve the flatness of crystal column surface.
For solving the problems of the technologies described above, the invention provides a kind of fleet plough groove isolation structure manufacture method, comprising:
Form liner oxidation silicon and pad silicon nitride in Semiconductor substrate, and the described liner oxidation silicon of etching, pad silicon nitride and part semiconductor substrate, isolated groove formed;
Utilize thermal oxidation method to form the silica protective layer in inwall and the pad silicon nitride of isolated groove;
Form specific filler to fill the surface of described isolated groove and capping oxidation silicon protective layer;
Utilize specific filler and silica protective layer on the chemical mechanical milling tech removal pad silicon nitride;
Utilize wet-etching technology to remove the interior specific filler of isolated groove;
Inwall and pad silicon nitride at isolated groove form silicon nitride protective layer;
Form silica-filled layer to fill isolated groove and to cover the surface of silicon nitride protective layer;
Utilize the silica-filled layer on the CMP (Chemical Mechanical Polishing) process removal silicon nitride protective layer;
Utilize wet-etching technology to remove successively silicon nitride protective layer, pad silicon nitride and liner oxidation silicon, until expose the surface of described Semiconductor substrate.
Optionally, in described fleet plough groove isolation structure manufacture method, described specific filler is the anti-reflecting layer material.
Optionally, in described fleet plough groove isolation structure manufacture method, utilize the mode of spin coating to form specific filler.
Optionally, in described fleet plough groove isolation structure manufacture method, utilize chemical mechanical milling tech to remove in the step of specific filler on the described pad silicon nitride and silica protective layer, grinding rate is 50nm/min～1000nm/min.
Optionally, in described fleet plough groove isolation structure manufacture method, described wet-etching technology adopts the specific filler in the described isolated groove of SPM solution removal.
Compared with prior art; the present invention is before forming silicon nitride protective layer; form first specific filler; the recycling chemical mechanical milling tech is removed specific filler and the silica protective layer on the pad silicon nitride; and utilize wet-etching technology to remove the interior specific filler of isolated groove; thereby guarantee to utilize CMP (Chemical Mechanical Polishing) process to remove after the silica-filled layer; only need to utilize wet-etching technology to remove silicon nitride protective layer; pad silicon nitride and liner oxidation silicon; namely; in this wet-etching technology, only need to remove silicon nitride successively and silica gets final product; reduced the difficulty of this wet-etching technology; can effectively improve the effect of isolated groove marginal trough, and improve the flatness of crystal column surface.
Description of drawings
Figure 1A～1F is the generalized section of the device of existing a kind of fleet plough groove isolation structure manufacture method;
Fig. 2 A～2F is the generalized section of the device of existing another kind of fleet plough groove isolation structure manufacture method;
Fig. 3 is the flow chart of fleet plough groove isolation structure manufacture method of the present invention;
Fig. 4 A～4F is the generalized section of the device of fleet plough groove isolation structure manufacture method of the present invention.
Embodiment
In background technology, mention; in the fleet plough groove isolation structure manufacture process of the two protective layers (oxide/nitride double liner) of oxidation silicon/oxidative silicon; because CMP technique is flatness and the following Semiconductor substrate of protection that reaches higher; all adopt and have higher silica to the lapping liquid (slurry) of the grinding rate ratio of silicon nitride; grind when finishing like this and will be parked on the silicon nitride protective layer of the superiors; for this reason; need extra wet etching step to remove successively silicon nitride protective layer; the silica protective layer; pad silicon nitride and liner oxidation silicon; cause this wet-etching technology difficulty to increase; so namely impact improves the effect of isolated groove marginal trough, is unfavorable for again the flatness of crystal column surface.
For this reason; the present invention is before forming silicon nitride protective layer; form first specific filler; the recycling chemical mechanical milling tech is removed specific filler and the silica protective layer on the pad silicon nitride; utilize wet-etching technology to remove the interior specific filler of isolated groove; thereby guarantee to utilize CMP (Chemical Mechanical Polishing) process to remove after the silica-filled layer; only need to utilize wet-etching technology to remove silicon nitride protective layer; pad silicon nitride and liner oxidation silicon; namely; in this wet-etching technology, only need to remove silicon nitride successively and silica gets final product; reduced the difficulty of this wet-etching technology; can effectively improve the effect of isolated groove marginal trough, and improve the flatness of crystal column surface.
Specifically please refer to Fig. 3, it is the flow chart of fleet plough groove isolation structure manufacture method of the present invention, and described method comprises the steps:
Step S31: form liner oxidation silicon and pad silicon nitride in Semiconductor substrate, and the described liner oxidation silicon of etching, pad silicon nitride and part semiconductor substrate, form isolated groove;
Step S32: utilize thermal oxidation method to form the silica protective layer in inwall and the pad silicon nitride of described isolated groove;
Step S33: form specific filler to fill the surface of isolated groove and capping oxidation silicon protective layer;
Step S34: utilize specific filler and described silica protective layer on the chemical mechanical milling tech removal pad silicon nitride;
Step S35: utilize wet-etching technology to remove the interior specific filler of isolated groove;
Step S36: inwall and pad silicon nitride at described isolated groove form silicon nitride protective layer;
Step S37: form silica-filled layer to fill isolated groove and to cover the surface of silicon nitride protective layer;
Step S38: utilize the silica-filled layer on the CMP (Chemical Mechanical Polishing) process removal silicon nitride protective layer;
Step S39: utilize wet-etching technology to remove successively silicon nitride protective layer, pad silicon nitride and liner oxidation silicon, until expose the surface of described Semiconductor substrate.
Below in conjunction with accompanying drawing 4A～4F the fleet plough groove isolation structure manufacture method that the present invention proposes is described in more detail, it should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-accurately ratio, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Shown in Fig. 4 A, at first, form liner oxidation silicon (pad oxide) 420 and pad silicon nitride (pad nitride) 430 in Semiconductor substrate 410.The material of described Semiconductor substrate 410 can be monocrystalline silicon, polysilicon or amorphous silicon, and certain described Semiconductor substrate 410 also can comprise insulating barrier silicon-on or silicon Germanium compound.The thickness of described liner oxidation silicon 420 for example is 50 dusts～2000 dusts, and described liner oxidation silicon 420 is as the protective layer of Semiconductor substrate 410.The thickness of described pad silicon nitride 430 for example is 50 dusts～2000 dusts, and described pad silicon nitride 430 is as the barrier layer of subsequent etching and chemico-mechanical polishing (CMP) technique.Can utilize chemical vapor deposition method to form described liner oxidation silicon 420 and pad silicon nitride 430.
Shown in Fig. 4 B, form patterned mask layer in Semiconductor substrate 410, and take described patterned mask layer as mask, the described pad silicon nitride 430 of etching, liner oxidation silicon 420 and part semiconductor substrate 410 are to form isolated groove 410a in described Semiconductor substrate 410.Better, the opening at the top of described isolated groove 410a is larger, can be so that follow-up fill process becomes simple.
Shown in Fig. 4 C; utilize thermal oxidation method to form silica protective layer 440 in inwall and the pad silicon nitride 430 of described isolated groove 410a; the damage that Semiconductor substrate 410 is caused to repair etching technics, and the wedge angle (corner rounding) of sphering isolated groove 410a bottom.Wherein, described thermal oxidation method can be that high temperature furnace pipe oxidation, rapid thermal oxidation, original position steam produce a kind of in the oxidizing process.
Shown in Fig. 4 D, next, form specific filler 470, to fill isolated groove 410a and to cover the surface of described silica protective layer 440.Described specific filler 470 is preferably anti-reflecting layer material (ARC), and it has higher grinding rate, and has good fillibility, can not produce the space, and described anti-reflecting layer material cleans removal easily in addition.In the present embodiment, can utilize the mode of spin coating to form described specific filler, those skilled in the art can select corresponding spin coating proceeding parameter according to the degree of depth of the isolated groove that will fill, will not limit at this.
Shown in Fig. 4 E, then, utilize cmp (CMP) technique to remove specific filler and the silica protective layer 440 of pad silicon nitride 430 tops, until expose the surface of described pad silicon nitride 430.Better, the grinding rate of described chemical mechanical milling tech for example is 50nm/min～1000nm/min, this chemical mechanical milling tech is parked on the pad silicon nitride 430 when finishing.
Shown in Fig. 4 F, subsequently, utilize wet etching (wet etch) technique to remove the interior specific filler of isolated groove 410a, namely expose described isolated groove 410a.In this example, described wet-etching technology adopts the specific filler in the described isolated groove 410a of SPM solution removal.
Shown in Fig. 4 G; then; utilize chemical vapor deposition method to form silicon nitride protective layer 460 in inwall and the pad silicon nitride 430 of isolated groove 410a; thereby in isolated groove 410a, form two protective layer (the oxide/nitride double liner) structures of oxidation silicon/oxidative silicon; at this moment, only has silicon nitride material (pad silicon nitride 430 and silicon nitride protective layer 460) on the liner oxidation silicon 420.
Shown in Fig. 4 H; then; utilize chemical vapor deposition method to form silica-filled layer 450 to fill isolated groove 410a; also can be at the silica of the suitable thickness of silicon nitride protective layer 460 surface depositions in isolated groove 410a silicon oxide deposition; at this moment, be formed with silicon nitride protective layer 460 and silica-filled layer 450 double-layer films structure in pad silicon nitride 430.
Shown in Fig. 4 I; next; utilize chemico-mechanical polishing (CMP) technique to remove the silica of silicon nitride protective layer 460 surface depositions; for reaching higher flatness and the following Semiconductor substrate of protection; described CMP (Chemical Mechanical Polishing) process adopts has higher silica to the lapping liquid of the grinding rate ratio of silicon nitride; and stop on the silicon nitride protective layer 460, finally form smooth surface.
At last, utilize wet-etching technology to remove silicon nitride protective layer 460, pad silicon nitride 430 and liner oxidation silicon 420, until expose the surface of described Semiconductor substrate 410, until formed the fleet plough groove isolation structure shown in Fig. 4 J.
Because the present invention is before forming silicon nitride protective layer 460; form first specific filler 470; remove again the silica protective layer on specific filler 470 and the pad silicon nitride 430; therefore; utilize CMP (Chemical Mechanical Polishing) process to remove after the silica-filled layer 450; only need to utilize wet-etching technology to remove successively silicon nitride protective layer 460, pad silicon nitride 430 and liner oxidation silicon 420; reduced the difficulty of this wet-etching technology; can effectively improve the effect of isolated groove marginal trough, and improve the flatness of crystal column surface.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can in the situation that does not break away from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (5)
1. a fleet plough groove isolation structure manufacture method is characterized in that, comprising:
Form liner oxidation silicon and pad silicon nitride in Semiconductor substrate, and the described liner oxidation silicon of etching, pad silicon nitride and part semiconductor substrate, isolated groove formed;
Utilize thermal oxidation method to form the silica protective layer in inwall and the pad silicon nitride of isolated groove;
Form specific filler to fill the surface of described isolated groove and capping oxidation silicon protective layer;
Utilize specific filler and silica protective layer on the chemical mechanical milling tech removal pad silicon nitride;
Utilize wet-etching technology to remove the interior specific filler of isolated groove;
Inwall and pad silicon nitride at isolated groove form silicon nitride protective layer;
Form silica-filled layer to fill isolated groove and to cover the surface of silicon nitride protective layer;
Utilize the silica-filled layer on the CMP (Chemical Mechanical Polishing) process removal silicon nitride protective layer;
Utilize wet-etching technology to remove successively silicon nitride protective layer, pad silicon nitride and liner oxidation silicon, until expose the surface of described Semiconductor substrate.
2. fleet plough groove isolation structure manufacture method as claimed in claim 1 is characterized in that, described specific filler is the anti-reflecting layer material.
3. fleet plough groove isolation structure manufacture method as claimed in claim 2 is characterized in that, utilizes the mode of spin coating to form described specific filler.
4. such as the described fleet plough groove isolation structure manufacture method of any one in the claims 1 to 3; it is characterized in that; utilize chemical mechanical milling tech to remove in the step of specific filler on the described pad silicon nitride and silica protective layer, grinding rate is 50nm/min～1000nm/min.
5. fleet plough groove isolation structure manufacture method as claimed in claim 1 is characterized in that, described wet-etching technology adopts the specific filler in the described isolated groove of SPM solution removal.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112331610A (en) * | 2020-11-12 | 2021-02-05 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor structure |
| CN112670235A (en) * | 2020-12-23 | 2021-04-16 | 华虹半导体(无锡)有限公司 | STI planarization method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20020031890A1 (en) * | 2000-08-28 | 2002-03-14 | Takayuki Watanabe | Semiconductor device of STI structure and method of fabricating MOS transistors having consistent threshold voltages |
| KR20060002136A (en) * | 2004-07-01 | 2006-01-09 | 주식회사 하이닉스반도체 | Method for fabricating isolation layer of semiconductor device |
| US20070293017A1 (en) * | 2006-06-15 | 2007-12-20 | Chin-Cheng Yang | Method of fabricating shallow trench isolation structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020031890A1 (en) * | 2000-08-28 | 2002-03-14 | Takayuki Watanabe | Semiconductor device of STI structure and method of fabricating MOS transistors having consistent threshold voltages |
| KR20060002136A (en) * | 2004-07-01 | 2006-01-09 | 주식회사 하이닉스반도체 | Method for fabricating isolation layer of semiconductor device |
| US20070293017A1 (en) * | 2006-06-15 | 2007-12-20 | Chin-Cheng Yang | Method of fabricating shallow trench isolation structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112331610A (en) * | 2020-11-12 | 2021-02-05 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor structure |
| CN112331610B (en) * | 2020-11-12 | 2023-08-25 | 上海华虹宏力半导体制造有限公司 | Method for preparing semiconductor structure |
| CN112670235A (en) * | 2020-12-23 | 2021-04-16 | 华虹半导体(无锡)有限公司 | STI planarization method |
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Application publication date: 20130313 |