CN101154618A - Method for forming device isolation region - Google Patents
Method for forming device isolation region Download PDFInfo
- Publication number
- CN101154618A CN101154618A CNA2007101265885A CN200710126588A CN101154618A CN 101154618 A CN101154618 A CN 101154618A CN A2007101265885 A CNA2007101265885 A CN A2007101265885A CN 200710126588 A CN200710126588 A CN 200710126588A CN 101154618 A CN101154618 A CN 101154618A
- Authority
- CN
- China
- Prior art keywords
- silicon nitride
- nitride layer
- dusts
- layer
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Element Separation (AREA)
Abstract
The invention relates to a method for forming a part isolating zone, firstly an oxidizing lining layer and a first silicon nitride layer are formed in turn on a silicon underlay, the oxidizing lining layer, the first silicon nitride and the silicon underlay are etched to form a groove, an insulating oxidizing layer is formed on the first silicon nitride layer, the insulating oxidizing layer can be filled fully in the groove; a second silicon nitride layer is formed on the insulating oxidizing layer, the second silicon nitride layer, the insulating oxidizing layer and the first silicon nitride layer are rubbed to remove the first silicon nitride layer and the oxidizing lining layer and form a shallow groove isolating structure. After the steps are finished, and because one silicon nitride layer is deposited on a silicon oxide layer, when the silicon oxide layer and the silicon nitride layer are rubbed, the speed for rubbing the silicon nitride is slower than that for rubbing the silicon oxide, thereby the depressed condition of the silicon oxide in the shallow groove can be improved after the rubbing process is over.
Description
Technical field
The present invention relates to a kind of method that forms device isolation region, particularly the manufacture method of shallow trench isolation of semiconductor devices.
Background technology
Along with reducing of integrated circuit size, the device of forming circuit must be placed more thick and fast, to adapt to the confined space available on the chip.Because present research is devoted to increase the density of active device on the unit are of Semiconductor substrate, becomes more important so the effective insulation between circuit is isolated.The method that forms area of isolation in the prior art mainly contains carrying out local oxide isolation (LOCOS) technology or shallow trench isolation from (STI) technology.LOCOS technology is at wafer surface deposit one deck silicon nitride, and then carries out etching, and the part recessed region is carried out the oxidation growth silica, and active device generates in the determined zone of silicon nitride.For isolation technology, the effective carrying out local oxide isolation of LOCOS technology in circuit still has problems, one of them problem is exactly " beak " phenomenon in the silicon nitride marginal growth, and this is owing to the hot expansibility difference between silicon nitride in the process of oxidation and the silicon causes.This " beak " taken actual space, increased the volume of circuit, and in oxidizing process, wafer produced stress rupture.Therefore LOCOS technology only is applicable to the design and the manufacturing of large-size device.
Shallow trench isolation has multinomial processing procedure and electrical isolation advantage from (STI) technology than carrying out local oxide isolation (LOCOS) technology, comprise and to reduce the integrated level that the area that takies silicon wafer surface increases device simultaneously, keep surface flatness and less channel width erosion etc.Therefore, the following element of present 0.18 μ m for example the active area isolation layer of MOS circuit adopt shallow ditch groove separation process to make mostly.
Figure 1A to Fig. 1 D for existing make shallow trench isolation from process.Semiconductor integrated circuit includes source region and the isolated area between active area usually, and device normally forms in active area.Be used for the storage of data at some active region of substrate surface, be referred to as memory cell areas here; And some active region is used for peripheral control circuit, is referred to as periphery circuit region here.Usually between the active area of memory cell areas and periphery circuit region, all form fleet plough groove isolation structure to play insulation and the buffer action between the active area.Shown in Figure 1A, silicon substrate 100 and 110 surf zone be corresponding periphery circuit region 10 and memory cell areas 11 respectively, by thermal oxidation method, forms pad silicon oxide layers 102 at silicon substrate 100 and 110 surfaces; At silicon oxide layer 102 surface deposition silicon nitride layers 103; Then, on silicon nitride layer 103, form patterned light blockage layer 104 definition isolated areas.Shown in Figure 1B, be mask with photoresist layer 104, etches both silicon nitride layer 103, pad silicon oxide layer 102, silicon substrate 100,110; In the silicon substrate 100 of periphery circuit region 10, form shallow trench 108, in the silicon substrate 110 of memory cell areas 11, form shallow trench 105, because periphery circuit region 10 is active device non-dense set districts, memory cell areas 11 is active device compact districts, therefore, the shallow trench 108 of periphery circuit region 10 is wideer than the shallow trench 105 of memory cell areas 11.Shown in Fig. 1 C, form lining silicon oxide layer 107 at the bottom and the sidewall of shallow trench 108,105 with thermal oxidation method; On silicon nitride layer 103, form insulating oxide 106 by usefulness high-density plasma chemical vapour-phase deposition method (HDP-CVD), and insulating oxide 106 is filled up shallow trench 108,105.Shown in Fig. 1 D, utilize cmp (CMP) method that insulating oxide 106 is ground, to expose until silicon nitride layer 103 surfaces, depression 111 appears in the insulating oxide 106 in shallow trench 108.Shown in Fig. 1 E, wet etching is removed silicon nitride layer 103 and pad silicon oxide layer 102, forms fleet plough groove isolation structure 109.
Existing shallow trench isolation from manufacture method specifically to please refer to application number be described in 200410057166 the disclosed technical scheme of Chinese patent application.
Fig. 2 is the periphery circuit region photo that prior art is taken when multiplication factor is 150 times with light microscope.As shown in Figure 2,, when multiplication factor is 150 times the periphery circuit region fleet plough groove isolation structure that forms with said method is observed with light microscope, finding has depression and residual polycrystalline silicon phenomenon.This is because periphery circuit region is active device non-dense set district, therefore it is bigger to be used to isolate the shallow trench width of active device at periphery circuit region, the shallow trench width of some periphery circuit region reaches more than the 20um, after the insulating oxide of being filled in the shallow trench ground, very serious depression can appear in insulating oxide.For example, when being that the depression of the degree of depth greater than 700 dusts can appear in insulating oxide after the insulating oxide of being filled in the shallow trench of 100um ground to width.
In the process of existing making fleet plough groove isolation structure, because after having deposited insulating oxide, insulating oxide in the shallow trench is lower than the insulating oxide on the silicon nitride layer, when insulating oxide is ground to silicon nitride layer, can carry out grinding clean by full scale clearance to silicon nitride layer to guarantee the insulating oxide on the silicon nitride layer, when silicon nitride layer was carried out grinding, also can the insulating oxide in the shallow trench also be ground, because the speed of grinding silicon nitride layer is less than the speed of grinding insulating oxide, depressed phenomenon can appear in the insulating oxide in the shallow trench.Because memory cell areas is the device compact district, be used for shallow trench width that active device isolates generally all below 1um, so cup depth is very little, can not cause any harmful effect to successive process.But periphery circuit region is active device non-dense set district, some shallow trench width is greater than 20um, to serious depressed phenomenon occurring after insulating oxide grinds in the shallow trench of such width, cause leakage current, and then in successive process, produce the residual of polysilicon and cause short circuit between active device.
Summary of the invention
The problem that the present invention solves provides a kind of method that forms device isolation region, prevent because the shallow trench width of periphery circuit region is bigger, after being ground, the insulating oxide in the shallow trench can produce serious depressed phenomenon, cause leakage current, and then in successive process, produce the residual of polysilicon and cause short circuit between active device.
For addressing the above problem, the invention provides a kind of method that forms device isolation region, comprise the following steps: on silicon substrate, to form successively the pad oxide and first silicon nitride layer; Etching pad oxide, first silicon nitride layer and silicon substrate form groove; On first silicon nitride layer, form insulating oxide, and insulating oxide is filled full groove; On insulating oxide, form second silicon nitride layer; Grind second silicon nitride layer and insulating oxide to the first silicon nitride layer; Remove first silicon nitride layer and pad silicon oxide layer, form fleet plough groove isolation structure.
Optionally, the thickness of described second silicon nitride layer is 20 dust to 80 dusts, and concrete thickness is 20 dusts, 30 dusts, 40 dusts, 50 dusts, 60 dusts, 70 dusts or 80 dusts for example.
Optionally, in boiler tube, feed gas SiH
2Cl
2And NH
3React and form second silicon nitride layer, described SiH
2Cl
2And NH
3Proportionate relationship be SiH
2Cl
2: NH
3Equal 3: 4, the temperature that forms second silicon nitride layer is 600 ℃ to 700 ℃, and sedimentation time is 4 hours to 6 hours.
Optionally, form silicon oxide layer with the high density plasma CVD method.
Optionally, second silicon nitride layer and silicon oxide layer are carried out cmp, the speed of grinding second silicon nitride layer be 20 dusts/minute to 100 dusts/minute, the speed of grinding insulating oxide be 1500 dusts/minute to 3000 dusts/minute.
Optionally, remove first silicon nitride layer and pad silicon oxide layer with wet process.
Compared with prior art, the present invention has the following advantages: owing to deposited one deck silicon nitride layer on insulating oxide, when insulating oxide and silicon nitride layer are ground, it is slow that the speed ratio of grinding silicon nitride grinds the speed of insulating oxide, therefore after grinding end, insulating oxide depression situation is improved in the shallow trench of periphery circuit region, and leakage phenomenon can not produce, and then can not produce the residual of polysilicon and cause short circuit between active device in successive process.
Description of drawings
Figure 1A to Fig. 1 E is the schematic diagram that prior art is made fleet plough groove isolation structure;
Fig. 2 is the periphery circuit region photo that prior art is taken when amplifying 150 times with light microscope;
Fig. 3 is the periphery circuit region photo that the present invention takes when amplifying 150 times with light microscope;
Fig. 4 is the flow chart that the present invention makes fleet plough groove isolation structure;
Fig. 5 A to Fig. 5 F is the schematic diagram that the present invention makes fleet plough groove isolation structure.
Embodiment
Along with semiconductor technology enters the deep-submicron epoch, the following device active region isolation of 0.18 μ m adopts shallow ditch groove separation process to make mostly.Shallow ditch groove separation process solves the effective ways that carrying out local oxide isolation causes " beak " problem in the MOS circuit.But, because the depth-to-width ratio of the shallow trench of deep-submicron element is than higher, simultaneously method possesses high density plasma CVD (HDP-CVD) that " etching " and " deposition " two functions are arranged, therefore when depositing, also can carry out etching reaction with deposit flaking, make the high density plasma CVD method have the good ditch ability of filling out, therefore be applied in the insulating oxide that forms in the fleet plough groove isolation structure.
With the high density plasma CVD method shallow trench of periphery circuit region being carried out insulation oxide fills, because periphery circuit region is active device non-dense set district, therefore to be used to isolate the shallow trench width of active device bigger for periphery circuit region, some shallow trench width reaches more than the 20um, after insulating oxide grinds in to the shallow trench of such width, can produce serious depression in the insulating oxide, cause leakage current, and can in successive process, produce the residual of polysilicon and cause short circuit between active device.The present invention is a depression situation of improving insulating oxide in the periphery circuit region shallow trench, at insulating oxide surface deposition one deck silicon nitride layer, and then insulating oxide and silicon nitride layer is carried out cmp.For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 4 is the flow chart that the present invention makes fleet plough groove isolation structure.As shown in Figure 4, execution in step S201 upwards forms the pad oxide and first silicon nitride layer successively on silicon substrate; Execution in step S202, etching pad oxide, first silicon nitride layer and silicon substrate form groove; Execution in step S203 forms insulating oxide on first silicon nitride layer, and insulating oxide is filled full groove; Execution in step S204 forms second silicon nitride layer on insulating oxide; Execution in step S205 grinds second silicon nitride layer and insulating oxide to the first silicon nitride layer; Execution in step S206 removes first silicon nitride layer and pad silicon oxide layer, forms fleet plough groove isolation structure.
Fig. 5 A to Fig. 5 F is the schematic diagram that the present invention makes fleet plough groove isolation structure.Shown in Fig. 5 A, silicon substrate 200 and 210 surf zone be corresponding periphery circuit region 20 and memory cell areas 21 respectively, by thermal oxidation method, forms pad silicon oxide layers 202 at silicon substrate 200 and 210 surfaces; Filling up silicon oxide layer 202 surface depositions first silicon nitride layer 203 with chemical vapour deposition technique; Then, on first silicon nitride layer 203, form patterned light blockage layer 204 definition shallow trench figures 209.
Shown in Fig. 5 B, be mask with photoresist layer 204, etching first silicon nitride layer 203, pad silicon oxide layer 202 and silicon substrate 200,210; In the silicon substrate 200 of periphery circuit region 20, form shallow trench 211, in the silicon substrate 210 of memory cell areas 21, form shallow trench 205, because periphery circuit region 20 is active device non-dense set districts, memory cell areas 21 is active device compact districts, therefore, the shallow trench 211 of periphery circuit region 20 is wideer than the shallow trench 205 of memory cell areas 21.
Shown in Fig. 5 C, form lining silicon oxide layer 207 at the bottom and the sidewall of shallow trench 211,205 with thermal oxidation method; On first silicon nitride layer 203, form insulating oxide 206 by usefulness high-density plasma chemical vapour-phase deposition method (HDP-CVD), and insulating oxide 206 is filled full shallow trench 211,205, described insulating oxide layer material preferred oxygen silicon; After having deposited insulating oxide 206, insulating oxide 206 is not smooth, and the insulating oxide 206 on insulating oxide 206 to the first silicon nitride layers 203 in the shallow trench 211,205 is low; Shallow trench 211,205 width are big more, and insulating oxide 206 and the difference in height between the insulating oxide 206 on first silicon nitride layer 203 in the shallow trench 211,205 are big more.
Shown in Fig. 5 D,, prevent from after the insulating oxide 206 in the shallow trench 211,205 is ground, can produce serious depressed phenomenon at insulating oxide 206 surface depositions second silicon nitride layer 208; Deposit second silicon oxide layer 208 on uneven insulating oxide 206 again, insulating oxide 206 and the insulating oxide 206 and second silicon nitride layer 208 on second silicon nitride layer, 208 to the first silicon nitride layers 203 in the same shallow trench 211,205 are low.
In the present embodiment, in boiler tube, feed gas SiH
2Cl
2And NH
3Reaction forms second silicon nitride layer 208, the wherein SiH
2Cl
2: NH
3Equal 3: 4, except that embodiment, also available ALD Atomic layer deposition method deposits second silicon nitride layer 208.SiH wherein
2Cl
2And NH
3The temperature that reaction forms second silicon nitride layer 208 is 600 ℃ to 700 ℃, actual temp for example, 600 ℃, 650 ℃ or 700 ℃.SiH
2Cl
2And NH
3It is 4 hours to 6 hours that reaction forms the 208 used times of second silicon nitride layer, can adopt for example 4 hours, 5 hours or 6 hours.The thickness of described second silicon nitride layer 208 is 20 dust to 80 dusts, and concrete example is as 20 dusts, 30 dusts, 40 dusts, 50 dusts, 65 dusts, 70 dusts, 80 dusts.
Shown in Fig. 5 E, utilize chemical and mechanical grinding method that the insulating oxide 206 and second silicon nitride layer 208 are ground, expose until first silicon nitride layer, 203 surfaces; Because the insulating oxide 206 on first silicon nitride layer 203 and second silicon nitride layer 208 are higher than the insulating oxide 206 and second silicon nitride layer 208 in the shallow trench 211,205, when grinding, remove high part earlier, just earlier the insulating oxide 206 on first silicon nitride layer 203 and second silicon nitride layer 208 are ground away; When be ground to shallow trench 211,205 in second silicon nitride layer 208 surface the time, second silicon nitride layer on first silicon nitride layer 203 has been ground fully, begin insulating oxide 206 is ground, and this moment, shallow trench 211,205 parts just began second silicon nitride layer 208 is ground; Since grind the speed of second silicon nitride layer 208 and be 20 dusts/minute to 100 dusts/minute less than speed 1500 dusts that grind insulating oxide 206/minute to 3000 dusts/minute, when insulating oxide 206 on first silicon nitride layer 203 is milled to first silicon nitride layer 203 and first silicon nitride layer 203 was carried out grinding, 211,205 districts have just begun insulating oxide 206 is ground at shallow trench, therefore after grinding is finished, do not cave in the shallow trench 205 of memory cell areas 21, depression 213 degree of depth that occur in the shallow trench 211 of periphery circuit region 20 are less than 200 dusts.
In the present embodiment, with chemical mechanical milling method the insulating oxide 206 and second silicon nitride layer 208 are ground, the speed of grinding insulating oxide 206 be 1500 dusts/minute to 3000 dusts/minute, concrete speed for example 1500 dusts/minute, 1700 dusts/minute, 2000 dusts/minute, 2200 dusts/minute, 2500 dusts/minute, 2800 dusts/minute or 3000 dusts/minute.And the speed of grinding second silicon nitride layer 208 be 20 dusts/minute to 100 dusts/minute, concrete speed for example 20 dusts/minute, 40 dusts/minute, 60 dusts/minute, 80 dusts/minute or 100 dusts/minute.
Shown in Fig. 5 F, wet etching is removed first silicon nitride layer 203 and pad silicon oxide layer 202, forms fleet plough groove isolation structure 212.
The present invention makes the preferred embodiment of fleet plough groove isolation structure.Continue with reference to figure 5A to Fig. 5 F, shown in Fig. 5 A, silicon substrate 200 and 210 surf zone be corresponding periphery circuit region 20 and memory cell areas 21 respectively, by thermal oxidation method, fills up silicon oxide layers 202 at silicon substrate 200 and 210 surface formation; Filling up silicon oxide layer 202 surface depositions first silicon nitride layer 203 with chemical vapour deposition technique; Then, on first silicon nitride layer 203, form patterned light blockage layer 204 definition shallow trench figures 209.
Shown in Fig. 5 B, be mask with photoresist layer 204, etching first silicon nitride layer 203, pad silicon oxide layer 202 and silicon substrate 200,210; In the silicon substrate 200 of periphery circuit region 20, form shallow trench 211, in the silicon substrate 210 of memory cell areas 21, form shallow trench 205, because periphery circuit region 20 is active device non-dense set districts, memory cell areas 21 is active device compact districts, therefore, the shallow trench 211 of periphery circuit region 20 is wideer than the shallow trench 205 of memory cell areas 21.
Shown in Fig. 5 C, form lining silicon oxide layer 207 at the bottom and the sidewall of shallow trench 211,205 with thermal oxidation method; By forming insulating oxide 206 in shallow trench 204 205 and on first silicon nitride layer 203 with high-density plasma chemical vapour-phase deposition method (HDP-CVD).
Shown in Fig. 5 D, in boiler tube, feed gas SiH
2Cl
2And NH
3, be 600 ℃ to 700 ℃ in temperature, the time be under 4 hours to 6 hours the condition reaction to form thickness be 60 dusts, second silicon nitride layer 208, the wherein SiH
2Cl
2: NH
3Equal 3: 4, second silicon nitride layer 208 can prevent can to produce serious depressed phenomenon after the insulating oxide 206 in the shallow trench 211,205 is ground; Deposit second silicon oxide layer 208 on uneven insulating oxide 206 again, insulating oxide 206 and the insulating oxide 206 and second silicon nitride layer 208 on second silicon nitride layer, 208 to the first silicon nitride layers 203 in the same shallow trench 211,205 are low.
Shown in Fig. 5 E, utilize chemical and mechanical grinding method that the insulating oxide 206 and second silicon nitride layer 208 are ground, expose until first silicon nitride layer, 203 surfaces; Because the insulating oxide 206 on first silicon nitride layer 203 and second silicon nitride layer 208 are higher than the insulating oxide 206 and second silicon nitride layer 208 in the shallow trench 211,205, when grinding, remove high part earlier, just earlier the insulating oxide 206 on first silicon nitride layer 203 and second silicon nitride layer 208 are ground away; When be ground to shallow trench 211,205 in second silicon nitride layer 208 surface the time, second silicon nitride layer on first silicon nitride layer 203 has been ground fully, begin insulating oxide 206 is ground, and this moment, shallow trench 211,205 parts just began second silicon nitride layer 208 is ground; Since grind the speed of second silicon nitride layer 208 and be 20 dusts/minute to 100 dusts/minute less than speed 1500 dusts that grind insulating oxide 206/minute to 3000 dusts/minute, when insulating oxide 206 on first silicon nitride layer 203 is milled to first silicon nitride layer 203 and first silicon nitride layer 203 was carried out grinding, at shallow trench 211,205 districts have just begun insulating oxide 206 is ground, therefore after grinding is finished, do not cave in the shallow trench 205 of memory cell areas 21, depression 213 degree of depth that occur in the shallow trench 211 of periphery circuit region 20 are less than 50 dusts, even have only 30 dusts.
Shown in Fig. 5 F, wet etching is removed first silicon nitride layer 203 and pad silicon oxide layer 202, forms fleet plough groove isolation structure 212.
Fig. 3 is the peripheral circuit area photo that the present invention takes when amplifying 150 times with light microscope.As shown in Figure 3, form insulating oxide with high-density plasma chemical vapor deposition method (HDP-CVD), and insulating oxide fills up shallow trench; In boiler tube, feed gas SiH
2Cl
2And NH
3, SiH
2Cl
2: NH
3Equaling 3: 4, is 600 ℃ to 700 ℃ in temperature, and sedimentation time is SiH under 4 hours to 6 hours conditions
2Cl
2And NH
3Reaction, the silicon nitride layer that forms thickness and be 60 dusts is in the insulating oxide laminar surface; The insulating oxide and second silicon nitride layer are carried out cmp; Peripheral circuit area is observed when multiplication factor is 150 times with light microscope after forming fleet plough groove isolation structure, occurred without any depression and residual polycrystalline silicon.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. a method that forms device isolation region comprises the following steps:
On silicon substrate, form the pad oxide and first silicon nitride layer successively;
Etching pad oxide, first silicon nitride layer and silicon substrate form groove;
On first silicon nitride layer, form insulating oxide, and insulating oxide is filled full groove;
On insulating oxide, form second silicon nitride layer;
Grind second silicon nitride layer and insulating oxide to the first silicon oxide layer;
Remove first silicon nitride layer and pad silicon oxide layer, form fleet plough groove isolation structure.
2. the method for formation device isolation region according to claim 1 is characterized in that: the thickness of described second silicon nitride layer is 20 dust to 80 dusts.
3. the method for formation device isolation region according to claim 2 is characterized in that: the thickness of described second silicon nitride layer is 20 dusts, 30 dusts, 40 dusts, 50 dusts, 60 dusts, 70 dusts or 80 dusts.
4. the method for formation device isolation region according to claim 3 is characterized in that: feed gas SiH in boiler tube
2Cl
2And NH
3React and form second silicon nitride layer, described SiH
2Cl
2And NH
3Proportionate relationship be SiH
2Cl
2: NH
3Equal 3: 4.
5. the method for formation device isolation region according to claim 4 is characterized in that: feed gas SiH in boiler tube
2Cl
2And NH
3Reacting the temperature that forms second silicon nitride layer is 600 ℃ to 700 ℃, and the time is 4 hours to 6 hours.
6. the method for formation device isolation region according to claim 1 is characterized in that: form insulating oxide with the high density plasma CVD method.
7. according to the method for each described formation device isolation region of claim 1 to 6, it is characterized in that: second silicon nitride layer and insulating oxide are carried out cmp.
8. the method for formation device isolation region according to claim 7 is characterized in that: the speed of grinding second silicon nitride layer be 20 dusts/minute to 100 dusts/minute.
9. the method for formation device isolation region according to claim 7 is characterized in that: the speed of grinding insulating oxide be 1500 dusts/minute to 3000 dusts/minute.
10. the method for formation device isolation region according to claim 1 is characterized in that: remove first silicon nitride layer and pad silicon oxide layer with wet process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710126588A CN100576492C (en) | 2006-09-30 | 2007-06-22 | Form the method for device isolation region |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610116876 | 2006-09-30 | ||
| CN200610116876.8 | 2006-09-30 | ||
| CN200710126588A CN100576492C (en) | 2006-09-30 | 2007-06-22 | Form the method for device isolation region |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101154618A true CN101154618A (en) | 2008-04-02 |
| CN100576492C CN100576492C (en) | 2009-12-30 |
Family
ID=39256172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710126588A Active CN100576492C (en) | 2006-09-30 | 2007-06-22 | Form the method for device isolation region |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100576492C (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437047A (en) * | 2011-08-29 | 2012-05-02 | 上海华力微电子有限公司 | Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method |
| CN102446963A (en) * | 2010-10-15 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Composite tunneling dielectric layer and manufacturing method thereof and non-volatile memory |
| CN102019577B (en) * | 2009-09-17 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Optimization method of chemical mechanical polishing process |
| CN103021926A (en) * | 2012-12-24 | 2013-04-03 | 上海宏力半导体制造有限公司 | Formation method of STI (shallow trench isolation) structure and formation method of memory |
| CN104576500A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for increasing overhang height of surface of shallow trench isolation structure |
| CN104752363A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of flash memory |
| CN106501899A (en) * | 2015-09-07 | 2017-03-15 | 北京北方微电子基地设备工艺研究中心有限责任公司 | A kind of lithographic method of silicon dioxide |
| CN109075119A (en) * | 2015-01-23 | 2018-12-21 | 维耶尔公司 | Microdevice in system substrate is integrated |
| CN109461696A (en) * | 2018-10-15 | 2019-03-12 | 上海华虹宏力半导体制造有限公司 | A kind of production method of fleet plough groove isolation structure |
| CN111697942A (en) * | 2020-05-13 | 2020-09-22 | 杭州见闻录科技有限公司 | Cavity processing technology for MEMS device, bulk acoustic wave resonator and manufacturing technology thereof |
| CN113299767A (en) * | 2021-05-21 | 2021-08-24 | 江苏东海半导体科技有限公司 | Groove type Schottky device and manufacturing method thereof |
| US11728302B2 (en) | 2015-01-23 | 2023-08-15 | Vuereal Inc. | Selective micro device transfer to receiver substrate |
| US11735623B2 (en) | 2015-01-23 | 2023-08-22 | Vuereal Inc. | Micro device integration into system substrate |
-
2007
- 2007-06-22 CN CN200710126588A patent/CN100576492C/en active Active
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102019577B (en) * | 2009-09-17 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Optimization method of chemical mechanical polishing process |
| CN102446963A (en) * | 2010-10-15 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Composite tunneling dielectric layer and manufacturing method thereof and non-volatile memory |
| CN102437047B (en) * | 2011-08-29 | 2014-08-13 | 上海华力微电子有限公司 | Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method |
| CN102437047A (en) * | 2011-08-29 | 2012-05-02 | 上海华力微电子有限公司 | Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method |
| CN103021926A (en) * | 2012-12-24 | 2013-04-03 | 上海宏力半导体制造有限公司 | Formation method of STI (shallow trench isolation) structure and formation method of memory |
| CN103021926B (en) * | 2012-12-24 | 2017-04-12 | 上海华虹宏力半导体制造有限公司 | Formation method of STI (shallow trench isolation) structure and formation method of memory |
| CN104576500A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for increasing overhang height of surface of shallow trench isolation structure |
| CN104752363B (en) * | 2013-12-31 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | The forming method of flash memory |
| CN104752363A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of flash memory |
| US11728302B2 (en) | 2015-01-23 | 2023-08-15 | Vuereal Inc. | Selective micro device transfer to receiver substrate |
| US11728306B2 (en) | 2015-01-23 | 2023-08-15 | Vuereal Inc. | Selective micro device transfer to receiver substrate |
| US11735546B2 (en) | 2015-01-23 | 2023-08-22 | Vuereal Inc. | Selective micro device transfer to receiver substrate |
| US11735623B2 (en) | 2015-01-23 | 2023-08-22 | Vuereal Inc. | Micro device integration into system substrate |
| US11735547B2 (en) | 2015-01-23 | 2023-08-22 | Vuereal Inc. | Selective micro device transfer to receiver substrate |
| US11735545B2 (en) | 2015-01-23 | 2023-08-22 | Vuereal Inc. | Selective micro device transfer to receiver substrate |
| CN109075119A (en) * | 2015-01-23 | 2018-12-21 | 维耶尔公司 | Microdevice in system substrate is integrated |
| CN109075119B (en) * | 2015-01-23 | 2023-05-26 | 维耶尔公司 | Integrated device manufacturing method |
| CN106501899A (en) * | 2015-09-07 | 2017-03-15 | 北京北方微电子基地设备工艺研究中心有限责任公司 | A kind of lithographic method of silicon dioxide |
| CN109461696A (en) * | 2018-10-15 | 2019-03-12 | 上海华虹宏力半导体制造有限公司 | A kind of production method of fleet plough groove isolation structure |
| CN111697942B (en) * | 2020-05-13 | 2022-04-08 | 见闻录(浙江)半导体有限公司 | Cavity processing technology for MEMS device, bulk acoustic wave resonator and manufacturing technology thereof |
| WO2021227208A1 (en) * | 2020-05-13 | 2021-11-18 | 杭州见闻录科技有限公司 | Cavity machining process for mems device, bulk acoustic wave resonator and manufacturing process therefor |
| CN111697942A (en) * | 2020-05-13 | 2020-09-22 | 杭州见闻录科技有限公司 | Cavity processing technology for MEMS device, bulk acoustic wave resonator and manufacturing technology thereof |
| CN113299767B (en) * | 2021-05-21 | 2022-04-08 | 江苏东海半导体股份有限公司 | Groove type Schottky device and manufacturing method thereof |
| CN113299767A (en) * | 2021-05-21 | 2021-08-24 | 江苏东海半导体科技有限公司 | Groove type Schottky device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100576492C (en) | 2009-12-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100576492C (en) | Form the method for device isolation region | |
| CN100539080C (en) | Form the method for multi-crystal silicon floating bar structure by autoregistration | |
| US7700455B2 (en) | Method for forming isolation structure in semiconductor device | |
| CN101207064A (en) | Method for forming device isolation region | |
| CN104282616A (en) | Method of forming a shallow trench isolation structure | |
| CN101459108B (en) | Method for forming shallow groove isolation structure and etching method for forming shallow groove | |
| CN100576490C (en) | The formation method of fleet plough groove isolation structure | |
| CN101459107A (en) | Method for forming shallow groove isolation structure and etching | |
| CN101577242B (en) | Shallow trench isolation structure and forming method thereof | |
| CN107017161B (en) | Method for reducing dishing recess in STI-CMP process | |
| US7598562B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN105161450A (en) | Double-shallow-trench isolation forming method | |
| CN100449729C (en) | Method for forming isolation structure of shallow plough groove | |
| CN102097356B (en) | Method for making shallow trench isolation structure | |
| CN101996921B (en) | STI forming method | |
| CN104716035A (en) | Chemical mechanical polishing method | |
| CN114121776B (en) | Manufacturing method of semiconductor isolation structure | |
| CN102543702B (en) | Formation method of metal gate | |
| CN102087990A (en) | Shallow trench isolation method | |
| CN110120364A (en) | The preparation method of fleet plough groove isolation structure | |
| CN101051620A (en) | Method for producing semiconductor device and mask film for said method | |
| CN101728307B (en) | Method for manufacturing shallow trench isolation structure | |
| CN101459106B (en) | Forming method of shallow groove isolation structure | |
| CN101459109B (en) | Method for preparing shallow groove isolation structure | |
| CN102201361A (en) | Method for reducing dislocation effectively and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111117 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |