CN113299767B - Groove type Schottky device and manufacturing method thereof - Google Patents
Groove type Schottky device and manufacturing method thereof Download PDFInfo
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- CN113299767B CN113299767B CN202110556185.4A CN202110556185A CN113299767B CN 113299767 B CN113299767 B CN 113299767B CN 202110556185 A CN202110556185 A CN 202110556185A CN 113299767 B CN113299767 B CN 113299767B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 29
- 230000004888 barrier function Effects 0.000 claims abstract description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 238000001259 photo etching Methods 0.000 claims abstract description 15
- 230000008021 deposition Effects 0.000 claims abstract description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 11
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 11
- 238000004544 sputter deposition Methods 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 229910001092 metal group alloy Inorganic materials 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000010931 gold Substances 0.000 claims abstract description 4
- 229910052737 gold Inorganic materials 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 230000001413 cellular effect Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 210000004027 cell Anatomy 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
Abstract
The invention relates to a groove type Schottky device and a manufacturing method thereof. The method comprises the following steps: 1) growing an oxide layer on the epitaxial wafer; 2) photoetching and etching the groove; 3) generating gate oxide in the groove; 4) filling the groove with polycrystalline silicon; 5) back etching of the polycrystalline silicon; 6) removing the oxide layer by a wet method; 7) high-temperature thermal oxidation; 8) SiN deposition and ILD silicon dioxide layer deposition; 9) photoetching a Schottky contact hole, and removing wet silicon dioxide; 10) dry etching the SiN/thermal oxide layer; 11) sputtering Schottky barrier metal; 12) removing the barrier metal alloy/barrier metal; 13) HPD deposition; 14) sputtering contact metal; 15) photoetching and etching the contact metal; 16) and thinning the back gold. The advantages are that: the utilization of the cellular area is maximized, and the matching degree with the process flow is high; the barrier metal is better accumulated in the groove; avoiding a leakage path.
Description
Technical Field
The invention relates to a groove type Schottky device and a manufacturing method thereof, in particular to a groove type Schottky diode structure and a manufacturing method thereof.
Background
The trench schottky diode is a common power device of a semiconductor, and is invented by utilizing the MOS effect of metal-semiconductor-silicon. The method is mainly characterized in that the grooves are clamped off in advance through the MOS effect along with the rise of reverse voltage, the electric field strength is reduced to zero before reaching the silicon surface, the surface breakdown is avoided, and the blocking capability is improved.
In the prior art, the manufacturing process of the trench schottky diode is as follows: growing an oxide layer as a hard mask layer, photoetching a groove, etching the groove, filling polycrystalline silicon, etching polycrystalline silicon back, photoetching a contact hole, etching the contact hole, sputtering barrier metal alloy, removing the barrier metal, depositing contact metal, photoetching the contact metal, etching the contact metal and the like.
In the prior art, the etching depth of the contact hole, the in-chip uniformity of the etching rate and the barrier thickness must be accurately controlled; there are cases where the contact metal makes direct contact to the silicon causing leakage (fig. 1).
Disclosure of Invention
The invention provides a groove type Schottky device and a manufacturing method thereof, aiming at overcoming the defects in the prior art and avoiding a leakage channel caused by direct contact between contact metal and silicon.
The technical solution of the invention is as follows: a trench type Schottky device is structurally characterized in that a cellular structure of a trench type Schottky diode structure is hexagonal, the top of a trench is in an inclined angle, and a barrier layer metal interface is lower than a contact metal layer interface in the vertical direction.
A manufacturing method of a groove type Schottky device comprises the following process steps:
1) growing an oxide layer on the epitaxial wafer;
2) carrying out groove photoetching and etching;
3) generating gate oxide in the groove;
4) filling the groove with polysilicon;
5) carrying out polysilicon back etching, and controlling the polysilicon to be lower than an MESA interface in the vertical direction;
6) removing the oxide layer by adopting a wet process;
7) carrying out high-temperature thermal oxidation;
8) SiN deposition and ILD silicon dioxide layer deposition are carried out;
9) carrying out Schottky contact hole photoetching and wet silicon dioxide removal;
10) performing dry etching on the SiN/thermal oxide layer;
11) performing Schottky barrier metal sputtering;
12) removing the barrier metal alloy/barrier metal;
13) HPD deposition is carried out, the top of HDP is lower than MESA in the vertical direction;
14) carrying out contact metal sputtering;
15) carrying out contact metal photoetching and etching;
16) and carrying out back gold thinning to obtain the groove type Schottky diode device.
Preferably, the step 1) is to maintain the temperature of 900-1100 ℃, the oxygen flow of 4-12L/min and the growth thickness of 1000-5000A in furnace tube equipment.
Preferably, the width of the groove in the step 2) is 0.3-0.8 um, and the depth is 0.8-1.7 um.
Preferably, the step 3) is to maintain the temperature of 900-1100 ℃, the oxygen flow of 4-12L/min and the growth thickness of 600-4000A in furnace tube equipment.
Preferably, the step 4) is to deposit polysilicon by using an LPCVD furnace tube, and simultaneously perform N-type doping concentration E22.
Preferably, the step 5) controls the polysilicon to be 0.1 to 0.5 μm lower than the MESA interface in the vertical direction.
Preferably, the step 7) is to maintain the temperature at 900-1100 ℃, the oxygen flow at 4-12L/min and the growth thickness at 0.3-0.5 μm in furnace tube equipment.
Preferably, the step 8) is to deposit SiN with a thickness of 500-2000A by using an LPCVD furnace tube, and to deposit ILD silicon dioxide with a thickness of 4000-15000A by using an APCVD method while doping B, P elements.
Preferably, the step 12) is to deposit HDP in HDP processing equipment at a temperature of 300-500 ℃, and finally the top of the HDP is 0.05-0.45 μm lower than the MESA in the vertical direction.
The invention has the advantages that: 1) the hexagonal staggered structure is adopted to realize the maximization of the utilization of the cell area of the groove type Schottky cell, and the matching degree of the structure and the process flow is higher;
2) polysilicon back-etching control and subsequent high-temperature thermal oxidation are designed in the process flow, and the method is mainly used for adjusting the appearance of the top of the groove, opening the groove and better accommodating the accumulation of barrier metal in the groove in the subsequent barrier metal sputtering process;
3) the HDP deposition and back-etching process control is designed in the process flow and is mainly used for adjusting the depth of the contact metal in the groove, so that the depth of the contact metal is always shallower than that of the barrier layer, and a leakage channel caused by direct contact of the contact metal and silicon can be avoided.
Drawings
Fig. 1 is a schematic structural diagram of a prior art trench schottky diode.
Fig. 2 is a schematic diagram of a cell structure of a trench schottky device (trench schottky diode structure) according to the present invention.
Fig. 3 is a cross-sectional view of fig. 2.
Fig. 4 is a process flow diagram of a method for manufacturing a trench schottky device (trench schottky diode device) according to the present invention.
In the figure, 1 is a gate oxide, 2 is a polysilicon electrode, 3 is an ILD dielectric layer, 4 is a barrier layer, and 5 is a contact metal layer.
Detailed Description
The present invention will be described in further detail with reference to examples and specific embodiments.
As shown in fig. 2, a trench schottky device has a hexagonal cell structure, and as shown in fig. 3, the top feature of the trench has an inclination angle, and the barrier metal layer interface is lower than the contact metal layer interface in the vertical direction.
Experiments prove that the hexagonal cell structure is adopted to realize the maximization of area utilization, and the best adaptability to the subsequent process flow can be ensured. And the HDP process is added after the barrier metal is formed, so that the interface of the barrier metal is ensured to be permanently lower than the interface of the contact metal by 0.1-0.3 um in the vertical direction, and the direct contact between the contact metal and silicon to cause a leakage channel can be avoided. The finally obtained structure can reach the balance of performance and yield, and is the optimal scheme realized by the invention.
As shown in fig. 4, a method for manufacturing a trench schottky device includes the following steps:
1) growing an oxide layer on the epitaxial wafer, specifically in furnace tube equipment, keeping the temperature at 900-1100 ℃, the oxygen flow at 4-12L/min, and growing the oxide layer to a thickness of 1000-5000A;
2) carrying out groove photoetching and etching, wherein the width of the groove is 0.3-0.8 um, and the depth is 0.8-1.7 um;
3) generating gate oxide in the groove, specifically, in furnace tube equipment, keeping the temperature at 900-1100 ℃, the oxygen flow at 4-12L/min, and the growth thickness at 600-4000A;
4) filling the groove with polysilicon, specifically, depositing polysilicon by using an LPCVD furnace tube, and simultaneously performing N-type doping concentration E22;
5) carrying out polysilicon back etching, and controlling the interface of the polysilicon and the MESA, wherein the polysilicon is 0.1-0.5 μm lower than the MESA in the vertical direction;
6) removing the oxide layer by adopting a wet process;
7) performing high-temperature thermal oxidation for 0.3-0.5 μm, specifically maintaining the temperature at 900-1100 ℃ in a furnace tube device, the oxygen flow at 4-12L/min, and the growth thickness at 0.3-0.5 μm;
8) SiN deposition and ILD silicon dioxide layer deposition are carried out, specifically, the SiN thickness is about 500-2000A by adopting LPCVD furnace tube deposition, the ILD silicon dioxide is deposited by adopting an APCVD mode and is simultaneously doped with B, P elements, and the thickness is about 4000-15000A;
9) carrying out Schottky contact hole photoetching and wet silicon dioxide removal;
10) performing dry etching on the SiN/thermal oxide layer;
11) performing Schottky barrier metal sputtering;
12) removing the barrier metal alloy/barrier metal;
13) carrying out HPD deposition (high density plasma chemical vapor deposition), specifically, in special HDP process equipment, keeping the temperature at 300-500 ℃ to deposit HDP, and finally, in the vertical direction, the top of the HDP is 0.05-0.45 mu m lower than MESA;
14) carrying out contact metal sputtering;
15) carrying out contact metal photoetching and etching;
16) and carrying out back gold thinning to obtain the groove type Schottky diode device.
And 5) controlling polycrystalline silicon back etching and 7) performing high-temperature thermal oxidation, wherein the high-temperature thermal oxidation is mainly used for adjusting the appearance of the top of the groove, opening the groove and better accommodating the accumulation of barrier metal in the groove in the subsequent barrier metal sputtering process.
Step 13) HDP deposition and step 14) back etching HDP process control, mainly used for adjusting the depth of the contact metal in the groove, so that the depth of the contact metal is always shallower than that of the barrier layer, and a leakage channel caused by direct contact of the contact metal and silicon is avoided.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the inventive concept of the present invention, and these changes and modifications are all within the scope of the present invention.
Claims (9)
1. A manufacturing method of a groove type Schottky device is characterized by comprising the following processing steps:
1) growing an oxide layer on the epitaxial wafer;
2) carrying out groove photoetching and etching;
3) generating gate oxide in the groove;
4) filling the groove with polysilicon;
5) carrying out polysilicon back etching, and controlling the polysilicon to be lower than an MESA interface in the vertical direction;
6) removing the oxide layer by adopting a wet process;
7) carrying out high-temperature thermal oxidation;
8) SiN deposition and ILD silicon dioxide layer deposition are carried out;
9) carrying out Schottky contact hole photoetching and wet silicon dioxide removal;
10) performing dry etching on the SiN or thermal oxide layer;
11) performing Schottky barrier metal sputtering;
12) removing the barrier metal alloy and the barrier metal;
13) performing high density plasma chemical vapor deposition, wherein the top of HDP is lower than MESA in the vertical direction;
14) carrying out contact metal sputtering;
15) carrying out contact metal photoetching and etching;
16) carrying out back gold thinning to obtain a groove type Schottky diode device;
the cell structure of the groove type Schottky diode device is hexagonal, the top appearance of the groove has an inclination angle, and the metal interface of the barrier layer is lower than the interface of the contact metal layer in the vertical direction.
2. The method as claimed in claim 1, wherein the step 1) is performed by maintaining a temperature of 900-1100 ℃, an oxygen flow of 4-12L/min, and a growth thickness of 1000-5000A in a furnace.
3. The method as claimed in claim 1, wherein the trench width in step 2) is 0.3-0.8 um and the depth in step 2) is 0.8-1.7 um.
4. The method as claimed in claim 1, wherein the step 3) is performed by maintaining the temperature of 900-1100 ℃, the oxygen flow rate of 4-12L/min, and the growth thickness of 600-4000A in a furnace tube apparatus.
5. The method as claimed in claim 1, wherein the step 4) is performed by depositing polysilicon in an LPCVD furnace while performing N-type doping concentration E22.
6. The method as claimed in claim 1, wherein the step 5) controls the polysilicon to be lower than the MESA interface by 0.1-0.5 μm in the vertical direction.
7. The method as claimed in claim 1, wherein the step 7) is performed by maintaining the temperature of 900-1100 ℃, the oxygen flow rate of 4-12L/min, and the growth thickness of 0.3-0.5 μm in a furnace.
8. The method as claimed in claim 1, wherein the step 8) is performed by depositing SiN to a thickness of 500-2000A by LPCVD furnace tube, depositing ILD silicon dioxide by APCVD while doping B, P element to a thickness of 4000-15000A.
9. The method as claimed in claim 1, wherein the step 12) is performed by maintaining the HDP processing equipment at a temperature of 300-500 ℃ to deposit the HDP, and finally the top of the HDP is 0.05-0.45 μm lower than the MESA in the vertical direction.
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