CN110931569A - Semiconductor device with Schottky metal junction and manufacturing method thereof - Google Patents
Semiconductor device with Schottky metal junction and manufacturing method thereof Download PDFInfo
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- CN110931569A CN110931569A CN201911171044.XA CN201911171044A CN110931569A CN 110931569 A CN110931569 A CN 110931569A CN 201911171044 A CN201911171044 A CN 201911171044A CN 110931569 A CN110931569 A CN 110931569A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 113
- 239000002184 metal Substances 0.000 title claims abstract description 113
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 15
- 238000001312 dry etching Methods 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 9
- 238000004151 rapid thermal annealing Methods 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 5
- 150000002739 metals Chemical class 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 121
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910052697 platinum Inorganic materials 0.000 description 5
- 239000002131 composite material Substances 0.000 description 4
- 238000005036 potential barrier Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Abstract
The invention discloses a semiconductor device with a Schottky metal junction and a manufacturing method thereof, wherein the semiconductor device comprises a substrate and an epitaxial layer formed on the surface of the substrate, a plurality of grooves are formed in the epitaxial layer, polycrystalline silicon is filled in each groove, a gate oxide layer is formed between the polycrystalline silicon and the grooves, a first metal layer is formed on the upper surface of the polycrystalline silicon, a second metal layer is formed on the upper surface of the epitaxial layer adjacent to the polycrystalline silicon, the first metal layer is further formed on the upper surface of the epitaxial layer, and the Schottky barrier formed by the second metal layer and the epitaxial layer is different from the Schottky barrier formed by the first metal layer and the epitaxial layer in size. According to the invention, two different barrier metals are used as Schottky contacts, when the device blocks reversely, the Schottky barrier current is reduced by utilizing the electric field shielding effect of the high-barrier Schottky metal on the low-barrier Schottky metal, and when the device is conducted in the forward direction, the device has lower conduction voltage drop due to the low-barrier Schottky metal.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device with a Schottky metal junction and a manufacturing method thereof.
Background
As is well known, Schottky diodes, named by the inventor Schottky (Schottky), are fabricated using the metal-semiconductor barrier principle formed by metal-semiconductor contact. The characteristics of the Schottky device are mainly influenced by a Schottky contact Barrier, for example, reverse breakdown voltage, reverse current, forward conduction voltage drop and the like of the Schottky device are all related to the size of the Barrier of a selected Schottky metal, at present, a conventional TMBS (Trench MOS Barrier Diode) device adopts a titanium metal Barrier structure, the contact potential of the Schottky Barrier Diode is about 0.69V, the leakage current of the Schottky device is about 10 microamperes for a conventional 100V device, and the conduction voltage drop of the Schottky device is about 0.6V. However, for the high voltage 150-300V device, the leakage current of the device is required to be as low as possible in the power supply system, the leakage current at normal temperature needs to be less than 1 microampere, and for the titanium schottky metal, the leakage current less than 1 microampere is difficult to achieve.
Because titanium metal has a lower Schottky barrier, platinum has a higher Schottky barrier, and a small amount of platinum metal can promote the contact barrier of the Schottky metal, in order to improve the leakage current of the Schottky diode, it is proposed to dope platinum in the titanium metal to obtain lower leakage current, but the alloy Schottky contact barrier is only subjected to barrier height adjustment, the alloy Schottky contact barrier height is between the titanium Schottky barrier and the platinum Schottky contact barrier, and after platinum doping, the improvement of the Schottky barrier height increases the device turn-on voltage on the premise of obtaining lower leakage current.
Therefore, it is desirable to provide a semiconductor device having a schottky metal junction and a method for fabricating the same that can achieve a low leakage current without affecting the turn-on voltage of the device.
Disclosure of Invention
The invention aims to provide a semiconductor device with a Schottky metal junction, which can obtain lower leakage current on the premise of not influencing the turn-on voltage of a device.
Another object of the present invention is to provide a method for manufacturing a semiconductor device having a schottky metal junction, which can achieve a low leakage current without affecting the turn-on voltage of the device.
In order to solve the above technical problem, according to an aspect of the present invention, a semiconductor device with a schottky metal junction is provided, which includes a substrate and an epitaxial layer formed on a surface of the substrate, wherein a plurality of trenches are formed on the epitaxial layer, each trench is filled with polysilicon, a gate oxide layer is formed between the polysilicon and the trench, a first metal layer is formed on an upper surface of the polysilicon, a second metal layer is formed on an upper surface of the epitaxial layer adjacent to the polysilicon, the first metal layer is further formed on the upper surface of the epitaxial layer, and a schottky barrier formed by the second metal layer and the epitaxial layer is different from a schottky barrier formed by the first metal layer and the epitaxial layer.
The further technical scheme is as follows: the first metal layer is formed in the middle of the upper surface of the epitaxial layer between every two grooves, and the second metal layers are formed on two sides of the first metal layer.
The further technical scheme is as follows: the width of the second metal layer is 0.1-0.8 μm.
The further technical scheme is as follows: the depth of the groove is 0.5um-5 um.
In order to solve the above technical problem, according to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device having a schottky metal junction, including:
a. growing an oxide layer on an epitaxial layer of a substrate, spin-coating photoresist on the oxide layer, and exposing the oxide layer to expose a trench etching window;
b. etching the groove etching window area on the oxide layer by using a dry etching process until the groove etching window area is exposed out of the epitaxial layer;
c. depositing a dielectric layer on the epitaxial layer, and etching the dielectric layer back by adopting a dry etching process so as to leave a part of the dielectric layer on the groove etching window;
d. etching the epitaxial layer by using a dry etching process to form a plurality of grooves on the epitaxial layer;
e. growing a gate oxide layer on the side wall of each groove, depositing polycrystalline silicon in the grooves, and reversely etching the polycrystalline silicon;
f. depositing a silicon dioxide passivation layer on the oxide layer, and etching the passivation layer with a hole layer until the epitaxial layer is exposed;
g. sputtering first metal on the epitaxial layer, and removing unreacted first metal by a wet method after rapid thermal annealing;
h. and etching to remove the dielectric layer, sputtering a second metal on the dielectric layer, and removing the unreacted second metal after rapid thermal annealing.
The further technical scheme is as follows: the dielectric layer is made of silicon nitride.
The further technical scheme is as follows: the temperature of the thermal annealing in the step h is lower than that of the thermal annealing in the step g.
Compared with the prior art, the semiconductor device with the Schottky metal junction obtains lower leakage current on the premise of not influencing the turn-on voltage of the device, two different metal layers are formed on the epitaxial layer, the Schottky barrier formed by the second metal layer and the epitaxial layer has different size from the Schottky barrier formed by the first metal layer and the epitaxial layer, i.e., it uses two different barrier metals as schottky contacts, in the case of reverse blocking of the device, the electric field shielding effect of the high-barrier schottky metal on the low-barrier schottky metal can be utilized, meanwhile, the Schottky barrier current is further reduced by combining the groove electric field shielding effect of the groove Schottky diode, when the device is conducted in the forward direction, the Schottky diode with the low barrier is preferentially conducted, and the Schottky metal with the low barrier still has lower conduction voltage drop.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor device with a schottky metal junction according to an embodiment of the present invention.
Fig. 2 is a flow chart illustrating a method of fabricating a semiconductor device with schottky metal junctions according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood by those skilled in the art, the present invention is further described with reference to the accompanying drawings and examples.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device 10 having a schottky metal junction according to an embodiment of the present invention. In the embodiment shown in the drawings, the semiconductor device 10 includes a substrate 1 and an epitaxial layer 2 formed on the surface of the substrate 1, a plurality of trenches 3 are formed on the epitaxial layer 2, each trench 3 is filled with polysilicon 4, a gate oxide layer 5 is formed between the polysilicon 4 and the trench 3, a first metal layer 6 is formed on the upper surface of the polysilicon 4, a second metal layer 7 is formed on the upper surface of the epitaxial layer 2 adjacent to the polysilicon 4, the first metal layer 6 is further formed on the upper surface of the epitaxial layer 2, and a schottky barrier formed by the second metal layer 7 and the epitaxial layer 2 is different in size from a schottky barrier formed by the first metal layer 6 and the epitaxial layer 2. Preferably, in this embodiment, an N-type epitaxial layer is formed on the N + substrate, and the depth of the trench 3 is 0.5um to 5 um.
Understandably, in the present invention, the first metal layer 6 and the second metal layer 7 are formed of two different metal materials on the surface of the epitaxial layer 2. Based on the design, two different barrier metals are used as Schottky contact, under the condition that the device blocks reversely, the Schottky metal with the high barrier can be used for shielding the electric field of the Schottky metal with the low barrier, and meanwhile, the Schottky barrier current is further reduced by combining the groove electric field shielding effect of the groove Schottky diode, when the device is conducted in the forward direction, the Schottky diode with the low barrier is preferentially conducted, and the device still has lower conduction voltage drop due to the Schottky metal with the low barrier.
In this embodiment, the first metal layer 6 is formed in the middle of the upper surface of the epitaxial layer 2 between every two trenches 3, and the second metal layers 7 are formed on two sides of the first metal layer 6. Preferably, the first metal layer 6 and the second metal layer 7 may be formed of a metal material such as titanium, nickel, platinum, aluminum, etc., and the width of the second metal layer 7 is 0.1-0.8 μm.
Fig. 2 is a schematic flow chart illustrating a method for fabricating the semiconductor device with schottky metal junctions according to an embodiment of the present invention. In the embodiment shown in the drawings, the manufacturing method comprises the following steps:
s101, growing an oxide layer on the epitaxial layer of the substrate, spin-coating photoresist on the oxide layer, and exposing the oxide layer to expose the trench etching window.
In this step, an oxide layer of 500A-10000A is grown on the epitaxial layer, and the epitaxial layer is formed on the substrate surface, preferably, an N-type epitaxial layer is formed on an N + substrate.
And S102, etching the groove etching window area on the oxide layer by using a dry etching process until the epitaxial layer is exposed.
The dry etching process is a process of decomposing and ionizing etching gas through gas discharge, and etching the substrate by the generated active groups and ions. In this step, the dry etching process is used to etch the exposure region, that is, the trench etching window region on the oxide layer obtained in step S101 is etched, which is well known to those skilled in the art and will not be described herein again.
S103, depositing a dielectric layer on the epitaxial layer, and etching back the dielectric layer by adopting a dry etching process so as to leave a part of the dielectric layer on the groove etching window.
In the step, the dielectric layer is made of materials such as silicon nitride and the like, such as non-silicon dioxide, and the width of the residual dielectric layer can be adjusted according to the thickness of the deposited dielectric layer and the thickness of the oxide layer, and the width of the residual dielectric layer is 0.1-0.8 mu m.
And S104, etching the epitaxial layer by using a dry etching process to form a plurality of grooves on the epitaxial layer.
In this step, a plurality of trenches are etched on the exposed epitaxial layer, preferably, the trenches have a depth of 0.5um to 5 um.
And S105, growing a gate oxide layer on the side wall of each groove, depositing polycrystalline silicon in the groove, and performing reverse etching on the polycrystalline silicon.
In the step, a polysilicon layer remained after the reverse etching is arranged in the groove after the reverse etching is carried out on the polysilicon, and the thickness of the gate oxide layer is determined by the withstand voltage of the device.
And S106, depositing a silicon dioxide passivation layer on the oxide layer, and etching the passivation layer with a hole layer until the epitaxial layer is exposed.
In this step, the layer of cavities etches the exposed epitaxial layer as the contact window of the first metal layer.
S107, sputtering first metal on the epitaxial layer, and removing the unreacted first metal by a wet method after rapid thermal annealing.
In the step, metal sputtering and rapid thermal annealing are carried out on the epitaxial layer, the first metal and the epitaxial layer exposed by etching of the pore layer and the polycrystalline silicon form barrier alloy, and the unreacted metal layer is removed by wet etching after the thermal annealing. The wet etching is a process for removing a material of a surface layer of the silicon wafer to be etched by using a chemical etching solution.
And S108, etching to remove the dielectric layer, sputtering a second metal on the dielectric layer, and removing the unreacted second metal after rapid thermal annealing.
The temperature of the thermal annealing in step S108 is lower than that of the thermal annealing in step S107 to avoid an influence on the barrier alloy formed in step S107.
In the step, a dry etching process is adopted to etch and remove the dielectric layer, namely the silicon nitride layer, then metal sputtering and rapid thermal annealing are carried out on the region where the dielectric layer is removed, the second metal and the epitaxial layer exposed by the removed dielectric layer form a barrier alloy, the unreacted metal layer is removed by wet etching after the thermal annealing, and the Schottky barrier metal formed by the first metal and the epitaxial layer is different from the Schottky barrier metal formed by the second metal and the epitaxial layer.
Therefore, the manufacturing method of the invention adopts the surface composite Schottky metal structure, and the contact separation of the composite metal layer is carried out by the side wall technology, so that the photoetching level required by the device manufacturing can be obviously reduced to form the composite Schottky metal structure, the production cost can be reduced, and the market competitiveness is stronger. The width of the dielectric layer determines the width proportion of the composite metal layer, and further influences parameters such as conduction voltage drop and leakage current of the double-layer metal to the device.
The manufacturing method of the semiconductor device with the Schottky metal junction adopts different metals to carry out processes such as metal sputtering twice, rapid thermal annealing, etching and the like to form a bimetal contact structure, can utilize the Schottky metal with a high barrier to shield the electric field of the Schottky metal with a low barrier under the condition of reverse blocking of a device, and simultaneously further reduces the Schottky barrier current by combining the groove electric field shielding effect of the groove Schottky diode and reduces the leakage current of the Schottky diode by about 1-100 times; when the device is conducted in the forward direction, the Schottky diode with the low potential barrier is preferentially conducted, although the effective flow guiding area is reduced, the potential barrier voltage drop is dominant under the condition of small current, the influence of epitaxial resistance can be ignored, and the Schottky metal with the low potential barrier still has lower conduction voltage drop, so that the semiconductor device with the Schottky metal junction can effectively reduce the conduction voltage drop of the device under the condition of not improving the electric leakage of the device.
The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Various equivalent changes and modifications can be made by those skilled in the art based on the above embodiments, and all equivalent changes and modifications within the scope of the claims should fall within the protection scope of the present invention.
Claims (7)
1. A semiconductor device having a schottky metal junction, characterized in that: the semiconductor device comprises a substrate and an epitaxial layer formed on the surface of the substrate, wherein a plurality of grooves are formed in the epitaxial layer, polycrystalline silicon is filled in each groove, a gate oxide layer is formed between the polycrystalline silicon and the grooves, a first metal layer is formed on the upper surface of the polycrystalline silicon, a second metal layer is formed on the upper surface of the epitaxial layer adjacent to the polycrystalline silicon, the first metal layer is further formed on the upper surface of the epitaxial layer, and the Schottky barrier formed by the second metal layer and the epitaxial layer is different from the Schottky barrier formed by the first metal layer and the epitaxial layer.
2. The semiconductor device with a schottky metal junction as claimed in claim 1, wherein: the first metal layer is formed in the middle of the upper surface of the epitaxial layer between every two grooves, and the second metal layers are formed on two sides of the first metal layer.
3. The semiconductor device with a schottky metal junction as claimed in claim 1, wherein: the width of the second metal layer is 0.1-0.8 μm.
4. The semiconductor device with a schottky metal junction as claimed in claim 1, wherein: the depth of the groove is 0.5um-5 um.
5. A method of fabricating a semiconductor device having a schottky metal junction, the method comprising:
a. growing an oxide layer on an epitaxial layer of a substrate, spin-coating photoresist on the oxide layer, and exposing the oxide layer to expose a trench etching window;
b. etching the groove etching window area on the oxide layer by using a dry etching process until the groove etching window area is exposed out of the epitaxial layer;
c. depositing a dielectric layer on the epitaxial layer, and etching the dielectric layer back by adopting a dry etching process so as to leave a part of the dielectric layer on the groove etching window;
d. etching the epitaxial layer by using a dry etching process to form a plurality of grooves on the epitaxial layer;
e. growing a gate oxide layer on the side wall of each groove, depositing polycrystalline silicon in the grooves, and reversely etching the polycrystalline silicon;
f. depositing a silicon dioxide passivation layer on the oxide layer, and etching the passivation layer with a hole layer until the epitaxial layer is exposed;
g. sputtering first metal on the epitaxial layer, and removing unreacted first metal by a wet method after rapid thermal annealing;
h. and etching to remove the dielectric layer, sputtering a second metal on the dielectric layer, and removing the unreacted second metal after rapid thermal annealing.
6. The method of manufacturing a semiconductor device having a schottky metal junction according to claim 5, wherein: the dielectric layer is made of silicon nitride.
7. The method of manufacturing a semiconductor device having a schottky metal junction according to claim 5, wherein: the temperature of the thermal annealing in the step h is lower than that of the thermal annealing in the step g.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113299767A (en) * | 2021-05-21 | 2021-08-24 | 江苏东海半导体科技有限公司 | Groove type Schottky device and manufacturing method thereof |
| CN113903813A (en) * | 2021-09-30 | 2022-01-07 | 上海芯导电子科技股份有限公司 | Schottky diode, manufacturing method thereof and electronic device |
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2019
- 2019-11-26 CN CN201911171044.XA patent/CN110931569A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113299767A (en) * | 2021-05-21 | 2021-08-24 | 江苏东海半导体科技有限公司 | Groove type Schottky device and manufacturing method thereof |
| CN113299767B (en) * | 2021-05-21 | 2022-04-08 | 江苏东海半导体股份有限公司 | Groove type Schottky device and manufacturing method thereof |
| CN113903813A (en) * | 2021-09-30 | 2022-01-07 | 上海芯导电子科技股份有限公司 | Schottky diode, manufacturing method thereof and electronic device |
| CN113903813B (en) * | 2021-09-30 | 2024-02-09 | 上海芯导电子科技股份有限公司 | Schottky diode, preparation method thereof and electronic equipment |
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