CN105529372A - Tmbs device and manufacturing method thereof - Google Patents
Tmbs device and manufacturing method thereof Download PDFInfo
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- CN105529372A CN105529372A CN201610024810.XA CN201610024810A CN105529372A CN 105529372 A CN105529372 A CN 105529372A CN 201610024810 A CN201610024810 A CN 201610024810A CN 105529372 A CN105529372 A CN 105529372A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 230000007547 defect Effects 0.000 claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 claims abstract description 57
- 239000002184 metal Substances 0.000 claims abstract description 57
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 238000000407 epitaxy Methods 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 34
- 238000005468 ion implantation Methods 0.000 claims description 30
- 239000002131 composite material Substances 0.000 claims description 21
- 239000012528 membrane Substances 0.000 claims description 21
- HTCXJNNIWILFQQ-UHFFFAOYSA-M emmi Chemical compound ClC1=C(Cl)C2(Cl)C3C(=O)N([Hg]CC)C(=O)C3C1(Cl)C2(Cl)Cl HTCXJNNIWILFQQ-UHFFFAOYSA-M 0.000 claims description 18
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 15
- 239000010936 titanium Substances 0.000 claims description 15
- 229910052719 titanium Inorganic materials 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 230000001105 regulatory effect Effects 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000004151 rapid thermal annealing Methods 0.000 claims description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 7
- 238000005275 alloying Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 114
- 239000011229 interlayer Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a TMBS device, which comprises an N-type semiconductor substrate and a plurality of grooves, wherein an N-type epitaxial layer is formed on the N-type semiconductor substrate; the plurality of grooves are formed in the N-type epitaxial layer; a gate dielectric layer is formed on the internal surfaces of the grooves; polysilicon gates are filled into the grooves; controllable lattice defects of which the densities and the depths can be adjusted are formed on the surface of the N-type epitaxial layer out of the grooves; a schottky metal contact is formed on the surfaces of the controllable lattice defects; a forward conductive voltage of the TMBS device is lowered by adjusting the densities and the depths of the controllable lattice defects; a front metal layer covers the a schottky metal contact and the polysilicon gate surfaces and leads out a positive electrode; and a back metal layer is formed on the back surface of the N-type semiconductor substrate and leads out a negative electrode. The invention further discloses a manufacturing method of the TMBS device. According to the TMBS device and the manufacturing method thereof, the forward conductive voltage of the device can be lowered; and the performance of the device can be improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of trench MOS barrier Schottky diode (TrenchMOSBarrierControlledSchocttkyRectifier, TMBS) device; The invention still further relates to a kind of manufacture method of TMBS device.
Background technology
TMBS device adds trench gate mosfet structure relative to the Schottky diode of planar structure, surface between the groove of trench gate mosfet just forms Schottky contacts, trench gate mosfet is used for carrying out having lateral depletion when the reverse bias of Schottky diode to the N-type epitaxy layer between groove, thus can reverse breakdown voltage be improved, so also can adopt more high-dopant concentration or thinner N-type epitaxy layer, thus forward conduction resistance and the forward conduction voltage (VF) of device can be reduced.
The reduction of forward conduction voltage contributes to the performance improving device, and the forward conduction voltage how further reducing device on the basis of existing device is the research topic of the application.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of TMBS device, can reduce the forward conduction voltage of device, improve the performance of device.For this reason, the present invention also provides a kind of manufacture method of TMBS device.
For solving the problems of the technologies described above, TMBS device provided by the invention comprises:
N type semiconductor substrate, described N type semiconductor substrate is formed with N-type epitaxy layer.
In described N-type epitaxy layer, be formed with multiple groove, the interior surface in each described groove is formed with gate dielectric layer, in each described groove being formed with described gate dielectric layer, be filled with polysilicon gate.
Described N-type epitaxy layer surface outside each described groove is formed with controlled lattice defect, and density and the degree of depth of described controlled lattice defect can adjust.
Be formed with Schottky metal contact on described controlled lattice defect surface, reduced the forward conduction voltage of TMBS device by the density and the degree of depth adjusting described controlled lattice defect.
Front metal layer covers described Schottky metal contact and described polycrystalline silicon gate surface, and described front metal layer draws positive pole.
Be formed with metal layer on back at the back side of described N type semiconductor substrate, described metal layer on back draws negative pole.
Further improvement is, described N type semiconductor substrate is N-type silicon substrate, and described N-type epitaxy layer is N-type silicon epitaxy layer.
Further improvement is, described controlled lattice defect is formed by Si ion implantation, by the density regulating the dosage of described Si ion implantation to regulate described controlled lattice defect, by regulating the degree of depth of controlled lattice defect described in the energy adjustment of described Si ion implantation.
Further improvement is, the dosage of described Si ion implantation is 1e13cm
-2~ 1e16cm
-2.
Further improvement is, the dosage of described Si ion implantation is 10kev ~ 200kev.
Further improvement is, the thickness of described N-type epitaxy layer is 2 microns ~ 10 microns, and resistivity is 0.1 ohmcm ~ 2 ohmcm.
Further improvement is, the degree of depth of described groove is 0.5 micron ~ 5 microns.
Further improvement is, described gate dielectric layer is gate oxide.
Further improvement is, described gate dielectric layer is gate oxide, and the thickness of described gate dielectric layer is 500 Ethylmercurichlorendimide ~ 10000 Ethylmercurichlorendimides.
Further improvement is, what the described N-type epitaxy layer of described Schottky metal contact to be the composite membrane that is made up of the titanium of bottom and the titanium nitride of top layer with surface have described controlled lattice defect carried out that rapid thermal annealing formed contacts.
Further improvement is, the thickness of the bottom titanium of described composite membrane is 100 Ethylmercurichlorendimide ~ 300 Ethylmercurichlorendimides, and the thickness of the top layer titanium nitride of described composite membrane is 1200 Ethylmercurichlorendimide ~ 8000 Ethylmercurichlorendimides.
Further improvement is, the temperature of described rapid thermal annealing is 650 DEG C ~ 750 DEG C.
For solving the problems of the technologies described above, the manufacture method of TMBS device provided by the invention comprises the steps:
Step one, the N type semiconductor substrate providing surface to be formed with N-type epitaxy layer.
Step 2, in described N-type epitaxy layer, form multiple groove.
Step 3, interior surface in each described groove form gate dielectric layer, in each described groove being formed with described gate dielectric layer, fill polysilicon gate.
Step 4, described N-type epitaxy layer surface outside each described groove form controlled lattice defect, and density and the degree of depth of described controlled lattice defect can adjust.
Step 5, form Schottky metal contact on described controlled lattice defect surface, reduced the forward conduction voltage of TMBS device by the density and the degree of depth adjusting described controlled lattice defect.
Step 6, formation front metal layer, described front metal layer covers described Schottky metal contact and described polycrystalline silicon gate surface, and described front metal layer draws positive pole.
Step 7, carry out thinning back side to described N type semiconductor substrate and the back side of described N type semiconductor substrate after thinning forms metal layer on back, described metal layer on back draws negative pole.
Further improvement is, the substrate of N type semiconductor described in step one is N-type silicon substrate, and described N-type epitaxy layer is N-type silicon epitaxy layer.
Further improvement is, forms described groove and comprise as follows step by step in step 2:
Step 21, form hard mask layers on described N-type epitaxy layer surface.
Step 22, photoetching process is adopted to define the forming region of described groove at described hard mask layers surface coating photoresist.
Step 23, with described photoresist for mask etches described hard mask layers, the described hard mask layers of described groove forming region is removed by this etching technics, described groove forms extra-regional described hard mask layers and retains.
Step 24, remove described photoresist, form each described groove with described hard mask layers for mask carries out etching to described N-type epitaxy layer.
Further improvement is, described controlled lattice defect is formed by Si ion implantation, by the density regulating the dosage of described Si ion implantation to regulate described controlled lattice defect, by regulating the degree of depth of controlled lattice defect described in the energy adjustment of described Si ion implantation.
Further improvement is, the dosage of described Si ion implantation is 1e13cm
-2~ 1e16cm
-2.
Further improvement is, the dosage of described Si ion implantation is 10kev ~ 200kev.
Further improvement is, also comprises the steps: before the described controlled lattice defect of formation
Step 41, the employing thermal oxidation technology described N-type epitaxy layer surface outside each described groove forms sacrificial oxide layer.
Step 42, remove described sacrificial oxide layer to remove the uncontrollable lattice damage in the described N-type epitaxy layer surface outside each described groove.
Further improvement is, the thickness of described N-type epitaxy layer is 2 microns ~ 10 microns, and resistivity is 0.1 ohmcm ~ 2 ohmcm.
Further improvement is, the degree of depth of described groove is 0.5 micron ~ 5 microns.
Further improvement is, described gate dielectric layer is gate oxide.
Further improvement is, described gate dielectric layer is gate oxide, and the thickness of described gate dielectric layer is 500 Ethylmercurichlorendimide ~ 10000 Ethylmercurichlorendimides.
Further improvement is, the step forming described Schottky metal contact in step 5 is:
The titanium of bottom and the titanium nitride of top layer is formed successively, the titanium of bottom and the titanium nitride composition composite membrane of top layer on described controlled lattice defect surface.
Carry out described N-type epitaxy layer that rapid thermal anneal process makes described composite membrane and surface have a described controlled lattice defect to contact and form described Schottky metal contact.
Further improvement is, the thickness of the bottom titanium of described composite membrane is 100 Ethylmercurichlorendimide ~ 300 Ethylmercurichlorendimides, and the thickness of the top layer titanium nitride of described composite membrane is 1200 Ethylmercurichlorendimide ~ 8000 Ethylmercurichlorendimides.
Further improvement is, the temperature of described rapid thermal annealing is 650 DEG C ~ 750 DEG C.
Further improvement is, adopts chemical wet etching to carry out graphically forming described positive pole to described front metal layer in step 6.
Further improvement is, the graphical of described front metal layer carries out hydrogen annealing process afterwards to do alloying.
Further improvement is, the hydrogen annealing temperature of described alloying is 400 degrees Celsius ~ 450 degrees Celsius, and the time is 15 minutes ~ 90 minutes.
The present invention introduces controlled lattice defect by the N-type epitaxy layer surface between groove, this controlled lattice defect can affect the microstructure in Schottky metal contact forming process, thus the forward conduction voltage of device can be reduced, thus greatly can improve the performance of device.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of embodiment of the present invention TMBS device;
Fig. 2 A-Fig. 2 F is device architecture schematic diagram in each step of manufacture method of embodiment of the present invention TMBS device.
Embodiment
As shown in Figure 1, be the structural representation of embodiment of the present invention TMBS device; Embodiment of the present invention TMBS device comprises:
N type semiconductor substrate 1, described N type semiconductor substrate 1 is formed with N-type epitaxy layer 2.Goodly be chosen as, described N type semiconductor substrate 1 is N-type silicon substrate, and described N-type epitaxy layer 2 is N-type silicon epitaxy layer.The thickness of described N-type epitaxy layer 2 is 2 microns ~ 10 microns, and resistivity is 0.1 ohmcm ~ 2 ohmcm.
In described N-type epitaxy layer 2, be formed with multiple groove 101, the interior surface in each described groove 101 is formed with gate dielectric layer 3, in each described groove 101 being formed with described gate dielectric layer 3, be filled with polysilicon gate 4.Goodly be chosen as, the degree of depth of described groove 101 is 0.5 micron ~ 5 microns, and described gate dielectric layer 3 is gate oxide, and the thickness of described gate dielectric layer 3 is 500 Ethylmercurichlorendimide ~ 10000 Ethylmercurichlorendimides.
Described N-type epitaxy layer 2 surface outside each described groove 101 is formed with controlled lattice defect, and density and the degree of depth of described controlled lattice defect can adjust.Described controlled lattice defect is formed by Si ion implantation, by the density regulating the dosage of described Si ion implantation to regulate described controlled lattice defect, by regulating the degree of depth of controlled lattice defect described in the energy adjustment of described Si ion implantation.The dosage of described Si ion implantation is 1e14cm
-2~ 1e17cm
-2.The dosage of described Si ion implantation is 10kev ~ 200kev.
Be formed with Schottky metal contact 5 on described controlled lattice defect surface, reduced the forward conduction voltage of TMBS device by the density and the degree of depth adjusting described controlled lattice defect.Goodly be chosen as, what the described N-type epitaxy layer 2 of described Schottky metal contact 5 to be the composite membrane that is made up of the titanium of bottom and the titanium nitride of top layer with surface have described controlled lattice defect carried out that rapid thermal annealing formed contacts.The thickness of the bottom titanium of described composite membrane is 100 Ethylmercurichlorendimide ~ 300 Ethylmercurichlorendimides, and the thickness of the top layer titanium nitride of described composite membrane is 1200 Ethylmercurichlorendimide ~ 8000 Ethylmercurichlorendimides.The temperature of described rapid thermal annealing is 650 DEG C ~ 750 DEG C.
Front metal layer 6 covers described Schottky metal contact 5 and described polysilicon gate 4 surface, and described front metal layer 6 draws positive pole.
Be formed with metal layer on back 7 at the back side of described N type semiconductor substrate 1, described metal layer on back 7 draws negative pole.
As shown in Fig. 2 A to Fig. 2 F, it is device architecture schematic diagram in each step of manufacture method of embodiment of the present invention TMBS device.The manufacture method of embodiment of the present invention TMBS device comprises the steps:
Step one, as shown in Figure 2 A, provide the N type semiconductor substrate 1 that surface is formed with N-type epitaxy layer 2.
Goodly be chosen as, described N type semiconductor substrate 1 is N-type silicon substrate, and described N-type epitaxy layer 2 is N-type silicon epitaxy layer.The thickness of described N-type epitaxy layer 2 is 2 microns ~ 10 microns, and resistivity is 0.1 ohmcm ~ 2 ohmcm.
Step 2, as shown in Figure 2 A, in described N-type epitaxy layer 2, form multiple groove 101.
Goodly to be chosen as, formed described groove 101 comprise following step by step:
Step 21, form hard mask layers on described N-type epitaxy layer 2 surface, the material of described hard mask layers can be silica or silicon nitride.
Step 22, photoetching process is adopted to define the forming region of described groove 101 at described hard mask layers surface coating photoresist.
Step 23, with described photoresist for mask etches described hard mask layers, the described hard mask layers of described groove 101 forming region is removed by this etching technics, described hard mask layers outside described groove 101 forming region retains.
Step 24, remove described photoresist, form each described groove 101 with described hard mask layers for mask carries out etching to described N-type epitaxy layer 2, the etching of described groove 101 is dry etching.
Goodly be chosen as, the degree of depth of described groove 101 is 0.5 micron ~ 5 microns.
After forming described groove 101, remove described hard mask layers, sacrificial oxide layer is formed and wet method removal, for repairing the damage produced when dry etching forms described groove 101 afterwards in the lower surface of described groove 101 and described N-type epitaxy layer 2 surface of side and described groove 101 outside.
Step 3, as shown in Figure 2 B, the interior surface in each described groove 101 forms gate dielectric layer 3, in each described groove 101 being formed with described gate dielectric layer 3, fill polysilicon gate 4.
Goodly be chosen as, described gate dielectric layer 3 is gate oxide, and adopt thermal oxidation technology to be formed, the thickness of described gate dielectric layer 3 is 500 Ethylmercurichlorendimide ~ 10000 Ethylmercurichlorendimides.
Described gate dielectric layer 3 can extend to the surface of the described N-type epitaxy layer 2 of described groove 101 outside simultaneously; When depositing polysilicon forms described polysilicon gate 4, polysilicon also can extend to the surface of the described gate dielectric layer 3 of described groove 101 outside simultaneously; Need after polysilicon deposition to adopt dry back carving technology to be removed by the polysilicon of described groove 101 outside, and make the polysilicon surface in described groove 101 region equal with the surface of described groove 101 perimeter.The dry back carving technology of polysilicon adopts described gate dielectric layer 3 to be etch stop layer.
Step 4, first formation controlled lattice defect before also carry out following steps:
Step 41, as shown in Figure 2 C, form interlayer film (ILD), carry out contact hole definition and etching afterwards, the described interlayer film of TMBS nmosfet formation region and described gate dielectric layer 3 are all removed and are come out on described N-type epitaxy layer 3 surface outside the described polysilicon gate 4 in described groove 101 region of described TMBS nmosfet formation region and described groove 101 by contact hole definition and etching technics; Described TMBS nmosfet formation region still covers described interlayer film outward.
Afterwards, as shown in Figure 2 D, described N-type epitaxy layer 2 surface of thermal oxidation technology outside each described groove 101 is adopted to form sacrificial oxide layer 102.
Step 42, as shown in Figure 2 D, remove described sacrificial oxide layer 102 to remove the uncontrollable lattice damage in described N-type epitaxy layer 2 surface outside each described groove 101.
Carry out step afterwards: as shown in Figure 2 E, described N-type epitaxy layer 2 surface outside each described groove 101 forms controlled lattice defect, and density and the degree of depth of described controlled lattice defect can adjust.
Goodly be chosen as, described controlled lattice defect is formed by Si ion implantation, by the density regulating the dosage of described Si ion implantation to regulate described controlled lattice defect, by regulating the degree of depth of controlled lattice defect described in the energy adjustment of described Si ion implantation.The dosage of described Si ion implantation is 1e13cm
-2~ 1e16cm
-2.The dosage of described Si ion implantation is 10kev ~ 200kev.
Step 5, as shown in Figure 2 F, is formed Schottky metal contact 5 on described controlled lattice defect surface, is reduced the forward conduction voltage of TMBS device by the density and the degree of depth adjusting described controlled lattice defect.
The step forming described Schottky metal contact 5 is:
The titanium of bottom and the titanium nitride of top layer is formed successively, the titanium of bottom and the titanium nitride composition composite membrane of top layer on described controlled lattice defect surface.The thickness of the bottom titanium of described composite membrane is 100 Ethylmercurichlorendimide ~ 300 Ethylmercurichlorendimides, and the thickness of the top layer titanium nitride of described composite membrane is 1200 Ethylmercurichlorendimide ~ 8000 Ethylmercurichlorendimides.
Carry out described N-type epitaxy layer 2 that rapid thermal anneal process makes described composite membrane and surface have a described controlled lattice defect to contact and form described Schottky metal contact 5.The temperature of described rapid thermal annealing is 650 DEG C ~ 750 DEG C.
Step 6, formation front metal layer 6, described front metal layer 6 covers described Schottky metal contact 5 and described polysilicon gate 4 surface, adopts chemical wet etching graphically to form positive pole to described front metal layer 6 afterwards.
Then hydrogen annealing (H2-Anneal) is utilized to do alloying (alloy) afterwards.It may be noted that the hydrogen annealing step of this alloying is comparatively large for device performance impact, temperature and time needs careful selection, and in the embodiment of the present invention, hydrogen annealing temperature is 400 degrees Celsius ~ 450 degrees Celsius, and the time is 15 minutes ~ 90 minutes.
Step 7, carry out thinning back side to described N type semiconductor substrate 1 and the back side of described N type semiconductor substrate 1 after thinning forms metal layer on back 7, described metal layer on back 7 draws negative pole.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (29)
1. a TMBS device, is characterized in that, comprising:
N type semiconductor substrate, described N type semiconductor substrate is formed with N-type epitaxy layer;
In described N-type epitaxy layer, be formed with multiple groove, the interior surface in each described groove is formed with gate dielectric layer, in each described groove being formed with described gate dielectric layer, be filled with polysilicon gate;
Described N-type epitaxy layer surface outside each described groove is formed with controlled lattice defect, and density and the degree of depth of described controlled lattice defect can adjust;
Be formed with Schottky metal contact on described controlled lattice defect surface, reduced the forward conduction voltage of TMBS device by the density and the degree of depth adjusting described controlled lattice defect;
Front metal layer covers described Schottky metal contact and described polycrystalline silicon gate surface, and described front metal layer draws positive pole;
Be formed with metal layer on back at the back side of described N type semiconductor substrate, described metal layer on back draws negative pole.
2. TMBS device as claimed in claim 1, it is characterized in that: described N type semiconductor substrate is N-type silicon substrate, described N-type epitaxy layer is N-type silicon epitaxy layer.
3. TMBS device as claimed in claim 2, it is characterized in that: described controlled lattice defect is formed by Si ion implantation, by the density regulating the dosage of described Si ion implantation to regulate described controlled lattice defect, by regulating the degree of depth of controlled lattice defect described in the energy adjustment of described Si ion implantation.
4. TMBS device as claimed in claim 3, is characterized in that: the dosage of described Si ion implantation is 1e13cm
-2~ 1e16cm
-2.
5. TMBS device as claimed in claim 3, is characterized in that: the dosage of described Si ion implantation is 10kev ~ 200kev.
6. TMBS device as claimed in claim 2, is characterized in that: the thickness of described N-type epitaxy layer is 2 microns ~ 10 microns, and resistivity is 0.1 ohmcm ~ 2 ohmcm.
7. TMBS device as claimed in claim 6, is characterized in that: the degree of depth of described groove is 0.5 micron ~ 5 microns.
8. TMBS device as claimed in claim 1, is characterized in that: described gate dielectric layer is gate oxide.
9. TMBS device as claimed in claim 7, it is characterized in that: described gate dielectric layer is gate oxide, the thickness of described gate dielectric layer is 500 Ethylmercurichlorendimide ~ 10000 Ethylmercurichlorendimides.
10. TMBS device as claimed in claim 3, is characterized in that: to be the composite membrane that be made up of the titanium of bottom and the titanium nitride of top layer with the surperficial described N-type epitaxy layer with described controlled lattice defect carry out described Schottky metal contact that rapid thermal annealing formed contacts.
11. TMBS devices as claimed in claim 10, is characterized in that: the thickness of the bottom titanium of described composite membrane is 100 Ethylmercurichlorendimide ~ 300 Ethylmercurichlorendimides, and the thickness of the top layer titanium nitride of described composite membrane is 1200 Ethylmercurichlorendimide ~ 8000 Ethylmercurichlorendimides.
12. TMBS devices as claimed in claim 10, is characterized in that: the temperature of described rapid thermal annealing is 650 DEG C ~ 750 DEG C.
The manufacture method of 13. 1 kinds of TMBS devices, is characterized in that, comprises the steps:
Step one, the N type semiconductor substrate providing surface to be formed with N-type epitaxy layer;
Step 2, in described N-type epitaxy layer, form multiple groove;
Step 3, interior surface in each described groove form gate dielectric layer, in each described groove being formed with described gate dielectric layer, fill polysilicon gate;
Step 4, described N-type epitaxy layer surface outside each described groove form controlled lattice defect, and density and the degree of depth of described controlled lattice defect can adjust;
Step 5, form Schottky metal contact on described controlled lattice defect surface, reduced the forward conduction voltage of TMBS device by the density and the degree of depth adjusting described controlled lattice defect;
Step 6, formation front metal layer, described front metal layer covers described Schottky metal contact and described polycrystalline silicon gate surface, and described front metal layer draws positive pole;
Step 7, carry out thinning back side to described N type semiconductor substrate and the back side of described N type semiconductor substrate after thinning forms metal layer on back, described metal layer on back draws negative pole.
The manufacture method of 14. TMBS devices as claimed in claim 13, it is characterized in that: the substrate of N type semiconductor described in step one is N-type silicon substrate, described N-type epitaxy layer is N-type silicon epitaxy layer.
The manufacture method of 15. TMBS devices as described in claim 13 or 14, is characterized in that: formed in step 2 described groove comprise following step by step:
Step 21, form hard mask layers on described N-type epitaxy layer surface;
Step 22, photoetching process is adopted to define the forming region of described groove at described hard mask layers surface coating photoresist;
Step 23, with described photoresist for mask etches described hard mask layers, the described hard mask layers of described groove forming region is removed by this etching technics, described groove forms extra-regional described hard mask layers and retains;
Step 24, remove described photoresist, form each described groove with described hard mask layers for mask carries out etching to described N-type epitaxy layer.
The manufacture method of 16. TMBS devices as claimed in claim 14, it is characterized in that: described controlled lattice defect is formed by Si ion implantation, by the density regulating the dosage of described Si ion implantation to regulate described controlled lattice defect, by regulating the degree of depth of controlled lattice defect described in the energy adjustment of described Si ion implantation.
The manufacture method of 17. TMBS devices as claimed in claim 16, is characterized in that: the dosage of described Si ion implantation is 1e13cm
-2~ 1e16cm
-2.
The manufacture method of 18. TMBS devices as claimed in claim 16, is characterized in that: the dosage of described Si ion implantation is 10kev ~ 200kev.
The manufacture method of 19. TMBS devices as described in claim 14 or 16, is characterized in that: also comprised the steps: before the described controlled lattice defect of formation
Step 41, the employing thermal oxidation technology described N-type epitaxy layer surface outside each described groove forms sacrificial oxide layer;
Step 42, remove described sacrificial oxide layer to remove the uncontrollable lattice damage in the described N-type epitaxy layer surface outside each described groove.
The manufacture method of 20. TMBS devices as claimed in claim 14, is characterized in that: the thickness of described N-type epitaxy layer is 2 microns ~ 10 microns, and resistivity is 0.1 ohmcm ~ 2 ohmcm.
The manufacture method of 21. TMBS devices as claimed in claim 20, is characterized in that: the degree of depth of described groove is 0.5 micron ~ 5 microns.
The manufacture method of 22. TMBS devices as claimed in claim 13, is characterized in that: described gate dielectric layer is gate oxide.
The manufacture method of 23. TMBS devices as claimed in claim 21, is characterized in that: described gate dielectric layer is gate oxide, and the thickness of described gate dielectric layer is 500 Ethylmercurichlorendimide ~ 10000 Ethylmercurichlorendimides.
The manufacture method of 24. TMBS devices as claimed in claim 16, is characterized in that: the step forming described Schottky metal contact in step 5 is:
The titanium of bottom and the titanium nitride of top layer is formed successively, the titanium of bottom and the titanium nitride composition composite membrane of top layer on described controlled lattice defect surface;
Carry out described N-type epitaxy layer that rapid thermal anneal process makes described composite membrane and surface have a described controlled lattice defect to contact and form described Schottky metal contact.
The manufacture method of 25. TMBS devices as claimed in claim 24, is characterized in that: the thickness of the bottom titanium of described composite membrane is 100 Ethylmercurichlorendimide ~ 300 Ethylmercurichlorendimides, and the thickness of the top layer titanium nitride of described composite membrane is 1200 Ethylmercurichlorendimide ~ 8000 Ethylmercurichlorendimides.
The manufacture method of 26. TMBS devices as claimed in claim 24, is characterized in that: the temperature of described rapid thermal annealing is 650 DEG C ~ 750 DEG C.
The manufacture method of 27. TMBS devices as claimed in claim 13, is characterized in that: adopt chemical wet etching to carry out graphically forming described positive pole to described front metal layer in step 6.
The manufacture method of 28. TMBS devices as claimed in claim 27, is characterized in that: the graphical of described front metal layer carries out hydrogen annealing process afterwards to do alloying.
The manufacture method of 29. TMBS devices as claimed in claim 28, is characterized in that: the hydrogen annealing temperature of described alloying is 400 degrees Celsius ~ 450 degrees Celsius, and the time is 15 minutes ~ 90 minutes.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107170837A (en) * | 2017-06-20 | 2017-09-15 | 广微集成技术（深圳）有限公司 | A kind of semiconductor devices and manufacture method |
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| JPH1041527A (en) * | 1996-07-23 | 1998-02-13 | Toshiba Corp | Semiconductor device and its manufacture |
| US20090309181A1 (en) * | 2008-06-12 | 2009-12-17 | Force Mos Technology Co. Ltd. | Trench schottky with multiple epi structure |
| CN201741702U (en) * | 2010-07-01 | 2011-02-09 | 江阴新顺微电子有限公司 | Schottky diode with gird protection structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1041527A (en) * | 1996-07-23 | 1998-02-13 | Toshiba Corp | Semiconductor device and its manufacture |
| US20090309181A1 (en) * | 2008-06-12 | 2009-12-17 | Force Mos Technology Co. Ltd. | Trench schottky with multiple epi structure |
| CN201741702U (en) * | 2010-07-01 | 2011-02-09 | 江阴新顺微电子有限公司 | Schottky diode with gird protection structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107170837A (en) * | 2017-06-20 | 2017-09-15 | 广微集成技术（深圳）有限公司 | A kind of semiconductor devices and manufacture method |
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