CN109713046A - A kind of trench schottky diode and its manufacturing method - Google Patents
A kind of trench schottky diode and its manufacturing method Download PDFInfo
- Publication number
- CN109713046A CN109713046A CN201811572160.8A CN201811572160A CN109713046A CN 109713046 A CN109713046 A CN 109713046A CN 201811572160 A CN201811572160 A CN 201811572160A CN 109713046 A CN109713046 A CN 109713046A
- Authority
- CN
- China
- Prior art keywords
- layer
- groove
- schottky diode
- concentration
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of trench schottky diode, including a N- epitaxial layer and a N+ substrate layer, the N- epitaxial layer is set to the top of the N+ substrate layer；The concentration of dopant of the N- epitaxial layer linearly changes in vertical direction, and the concentration of dopant at N+ substrate layer is maximum；The present invention provides a kind of trench schottky diode manufacturing methods.The present invention has the advantages that improving the reverse blocking voltage of Schottky diode.
Description
Technical field
The present invention relates to semi-conductor discrete device field, a kind of trench schottky diode and its manufacturing method are referred in particular to.
Background technique
The abbreviation of Schottky diode (Schottky Barrier Diode) is SBD, be using metal and semiconductor it
Between a kind of majority carrier device for working of contact berrier.Due to this diode and common P-N junction configuration diode
It compares, has the characteristics that forward voltage drop is small, speed is fast, therefore collect in modern communication, ultrahigh-speed device, microwave circuit and high speed
At in circuit have extensive use.
For Schottky diode, influencing most important two parameters of power consumption is forward voltage drop VF and reversed leakage respectively
Electric current IR.For the Schottky diode of silicon epitaxy process, forward voltage drop VF depends on potential barrier alloy-layer, the epitaxial conditions used
(epitaxy layer thickness and resistivity) and active region area.The epitaxial conditions for the Schottky diode of specific standard
Optimization space it is relatively limited, and by increase active region area come reduce forward voltage drop VF and device miniaturization requirement mutually rush
It is prominent, and diode capacitance can be also improved, so that increasing circuit is lost, while being also contemplated that when forward voltage reduces, reversely
Leakage current can become larger.
In response to the above problems, traditional way is to be changed using trench technique and MOS structure around Schottky barrier
The field distribution of drift region inhibits schottky barrier junction surface peak electric field strength between MOS structure, so that peak value electric field goes out
In present device body, the optimization of the forward and reverse electrical parameter characteristic of Schottky diode may be implemented.But traditional way there are
Following disadvantage: the non-uniform electric in Schottky diode causes the reverse blocking effect of Schottky diode to need to be mentioned
It rises.
Summary of the invention
One of the technical problem to be solved in the present invention is to provide a kind of trench schottky diode, for promoting Xiao Te
The reverse blocking voltage of based diode.
The present invention is realized in one of technical problem: a kind of trench schottky diode, including a N- epitaxial layer with
And a N+ substrate layer, the N- epitaxial layer are set to the top of the N+ substrate layer；The concentration of dopant of the N- epitaxial layer is being hung down
Histogram is to linear change, and the concentration of dopant at N+ substrate layer is maximum.
Further, the N- epitaxial layer is equipped with the groove of a plurality of active areas and the groove of two termination environments；Each institute
The spacing stated between the groove of active area is equal, and the spacing of the groove of adjacent two active area is greater than the ditch of two termination environments
The spacing of slot；The N- epitaxial layer upper surface of the trench wall and termination environment is equipped with the grid oxide layer that a thickness is greater than 50nm, and
Full phosphorous doped polysilicon is filled in the groove；The trench depth is greater than 0.5um.
Further, the upper surface of the active area is equipped with a barrier metal layer, and it is blunt that the termination environment upper surface is equipped with one
Change layer；The top of the barrier metal layer and passivation layer is equipped with an anode metal layer.
Further, the lower section of the N+ substrate layer is equipped with a cathode metal layer.
The second technical problem to be solved by the present invention is to provide a kind of trench schottky diode manufacturing method, be used for
Promote the reverse blocking voltage of Schottky diode.
The present invention is realized in the twos' of technical problem: a kind of trench schottky diode manufacturing method, the method
Include the following steps:
Step S1, N- epitaxial layer is set to the top of N+ substrate layer；N- epitaxial layer and N+ substrate layer, which mix, doping
Agent；The dopant concentration of the dopant of N- epitaxial layer is less than the first concentration of setting, and linearly changes in vertical direction, more dense down
It spends higher；The dopant concentration of the dopant of N+ substrate layer is greater than the first concentration of setting and is less than the second concentration of setting；
Step S2, in one oxide layer of N- epitaxial layer disposed thereon, and a plurality of trench openings are formed in oxide layer；
Step S3, the groove and two terminals for generating a plurality of active areas are etched on N- epitaxial layer by trench openings
The groove in area, then removes removing oxide layer；
Step S4, a grid oxide layer, and deposit polycrystalline silicon are generated in N- epitaxial layer upper surface and trench wall；
Step S5, the grid oxide layer and polysilicon of the N- epitaxial layer upper surface of active area are removed, removal termination environment is higher than N-
The polysilicon of epitaxial layer upper surface；
Step S6, a passivation layer is deposited in the upper surface of termination environment；
Step S7, after the upper surface of active area sputters a barrier metal layer, sputtering one anode metal layer covering potential barrier gold
Belong to layer and passivation layer；
Step S8, a cathode metal layer is generated in the lower section of N+ substrate layer.
Further, in the step S1, first concentration is 1 × 1019A/cm3, the second concentration is 1 × 1021A/
cm3。
Further, in the step S3, the spacing between the groove of each active area is equal；Adjacent two is described active
The spacing of the groove in area is greater than the spacing of the groove of two termination environments.
Further, in the step S3, the depth of the groove is greater than 0.5um.
Further, the step S4 specifically: use the side of thermal oxide in N- epitaxial layer upper surface and trench wall
Formula generates the grid oxide layer that a thickness is not less than 50nm, and deposits phosphorous doped polysilicon.
Further, the step S5 specifically: N- epi-layer surface is deposited on by the removal of polycrystalline dry etch process
Phosphorous doped polysilicon.
The present invention has the advantages that
1, linearly changed by the dopant concentration of the dopant of N- epitaxial layer in vertical direction, concentration is higher more down, makes
The electric field for obtaining N- epitaxial layer is uniformly distributed in the horizontal direction, and then promotes the reverse blocking voltage of Schottky diode.
2, linearly changed by the dopant concentration of the dopant of N- epitaxial layer in vertical direction, concentration is higher more down, makes
It obtains and realizes high-concentration dopant on N- epitaxial layer, and then make Schottky diode that there is lower forward conduction resistance.
3, by etching the groove of active area and termination environment simultaneously, the size of trench schottky diode is reduced,
Reduce manufacturing cost.
4, by etching the groove of two termination environments, the resistance to pressure of trench schottky diode is improved, so that
The reliability of trench schottky diode greatly promotes.
Detailed description of the invention
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is oxide layer etching schematic diagram of the present invention.
Fig. 2 is groove and trench termination etching schematic diagram of the present invention.
Fig. 3 is etching polysilicon schematic diagram of the present invention.
Fig. 4 is passivation layer etching schematic diagram of the present invention.
Fig. 5 is trench schottky diode structural schematic diagram of the present invention.
Fig. 6 is N- epitaxial layer concentration of dopant schematic diagram of the present invention.
Description of symbols:
100- trench schottky diode, 1-N- epitaxial layer, 2-N+ substrate layer, 3- oxide layer, the groove of 4- active area, 5-
The groove of termination environment, 6- grid oxide layer, 7- phosphorous doped polysilicon, 8- passivation layer, 9- anode metal layer, 10- cathode metal layer, 11- gesture
Base metal layer, 12- active area, the termination environment 13-, 14- trench openings.
Specific embodiment
It please refers to shown in Fig. 1 to Fig. 6, a kind of preferred embodiment of trench schottky diode 100 of the present invention, including a N-
Epitaxial layer 1 and a N+ substrate layer 2, the N- epitaxial layer 1 are set to the top of the N+ substrate layer 2；The N- epitaxial layer 1 is mixed
Miscellaneous dose of concentration linearly changes in vertical direction, and the concentration of dopant at N+ substrate layer 2 is maximum；The dopant be phosphorus or
Arsenic, the resistivity of N- epitaxial layer 1 and N+ substrate layer 2 can be changed by doping dopant, and then change electric conductivity；N+ substrate layer
2 concentration of dopant is greater than the concentration of dopant of N- epitaxial layer 1, and the concentration of dopant of N+ substrate layer 2 is greater than 1 × 1019A/
cm3, the concentration of dopant of N- epitaxial layer 1 is less than 1 × 1019A/cm3。
The N- epitaxial layer 1 is equipped with the groove 4 of a plurality of active areas and (the bicyclic groove end of groove 5 of two termination environments
End)；Spacing between the groove 4 of each active area is equal, and the spacing of the groove 4 of adjacent two active area is greater than described in two
The spacing of the groove 5 of termination environment；It is big that 1 upper surface of N- epitaxial layer of groove 4 (5) inner wall and termination environment 13 is equipped with a thickness
Full phosphorous doped polysilicon 7 is filled in the grid oxide layer 6 of 50nm, and in the groove 4 (5)；Groove 4 (5) depth is greater than 0.5um.
By simultaneously etch the groove 4 of active area and the groove 5 of termination environment, reduce the size of trench schottky diode 100,
Reduce manufacturing cost；By etching the groove 5 of two termination environments, the resistance to of trench schottky diode 100 is improved
Pressure property, so that the reliability of trench schottky diode 100 greatly promotes.
The upper surface of the active area 12 is equipped with a barrier metal layer 11, and 13 upper surface of termination environment is equipped with a passivation layer
8；The top of the barrier metal layer 11 and passivation layer 8 is equipped with an anode metal layer 9.
The lower section of the N+ substrate layer 2 is equipped with a cathode metal layer 10.
The second technical problem to be solved by the present invention is to provide a kind of trench schottky diode manufacturing method, be used for
Promote the reverse blocking voltage of Schottky diode.
A kind of preferred embodiment of trench schottky diode manufacturing method of the present invention, includes the following steps:
Step S1, N- epitaxial layer 1 is set to the top of N+ substrate layer 2；N- epitaxial layer 1 and N+ substrate layer 2, which mix, to be had
Dopant；The dopant concentration of the dopant of N- epitaxial layer 1 is less than the first concentration of setting, and linearly changes in vertical direction, more
Concentration is higher down；The dopant concentration of the dopant of N- epitaxial layer 1 linearly changes in vertical direction crosses layering production difference all
Realization is merged after the N- epitaxial layer 1 of dopant concentration；The dopant concentration of the dopant of N+ substrate layer 2 is greater than the of setting
One concentration and the second concentration for being less than setting；Linearly changed by the dopant concentration of the dopant of N- epitaxial layer 1 in vertical direction,
Concentration is higher more down, so that the electric field of N- epitaxial layer 1 is uniformly distributed in the horizontal direction, and then promotes the trench schottky
The reverse blocking voltage of diode 100；So that realizing high-concentration dopant on the N- epitaxial layer 1, and then make groove Xiao
Special based diode 100 has lower forward conduction resistance；
Step S2, in 1 disposed thereon of N- epitaxial layer, one oxide layer 3, and a plurality of ditches are formed in oxide layer 3 by photoetching
Slot window 14；
Step S3, using trench etch process, a plurality of active areas are generated on N- epitaxial layer 1 by trench openings 14
Groove 4 and the groove of two termination environments 5 (bicyclic trench termination), then remove removing oxide layer 3；By etching active area simultaneously
And the groove 4 (5) of termination environment, the size of the trench schottky diode 100 is reduced, manufacturing cost is reduced；
Step S4, a grid oxide layer 6, and deposit polycrystalline silicon are generated in 1 upper surface of N- epitaxial layer and groove 4 (5) inner wall；
Step S5, the grid oxide layer 6 and polysilicon 7 for removing 1 upper surface of N- epitaxial layer of active area 12, remove termination environment 13
Higher than the polysilicon 7 of 1 upper surface of N- epitaxial layer；
Step S6, a passivation layer 8 is deposited in the upper surface of termination environment 13；
Step S7, after the upper surface of active area 12 sputters a barrier metal layer 11, one anode metal layer 9 of sputtering covers gesture
Base metal layer 11 and passivation layer 8；
Step S8, a cathode metal layer 10 is generated in the lower section of N+ substrate layer 2, last test scribing that is, will batch production
The trench schottky diode 100 be divided into and minimum use unit.
In the step S1, first concentration is 1 × 1019A/cm3, the second concentration is 1 × 1021A/cm3, i.e. N+ lining
2 high-concentration dopant phosphorus or arsenic of bottom, 1 low concentration doping phosphorus or arsenic of N- epitaxial layer；The dopant is phosphorus or arsenic, by mixing
The resistivity of miscellaneous dose of changeable N- epitaxial layer 1 and N+ substrate layer 2, and then change electric conductivity；The N- epitaxial layer 1 and N+ lining
Bottom 2 is manufactured by silicon.
In the step S3, the spacing between the groove 4 of each active area is equal；The groove of adjacent two active area
4 spacing is greater than the spacing of the groove 5 of two termination environments；The spacing of the groove 5 of two termination environments can be according to different rule
The pressure voltage of the trench schottky diode of lattice optimizes.
In the step S3, the depth of the groove 4 (5) is greater than 0.5um.
The step S4 specifically: raw by the way of thermal oxide in 1 upper surface of N- epitaxial layer and groove 4 (5) inner wall
It is not less than the grid oxide layer 6 of 50nm at a thickness, and deposits phosphorous doped polysilicon 7；The performance of MOS transistor is dependent on grid oxide layer 6
Thickness, the reduction of 6 thickness of grid oxide layer, enhances the current driving ability of transistor, improves speed and power characteristic, therefore drop
Low 6 thickness of gate oxide can effectively improve transistor performance, however thin grid oxide layer 6 can aggravate electric current tunneling effect and drop
Suboxides layer reliability.
The step S5 specifically: the p-doped for being deposited on 1 surface of N- epitaxial layer by the removal of polycrystalline dry etch process is more
Crystal silicon 7.
The step S6 specifically: deposit silicon dioxide passivation layer 8 on N- epitaxial layer 1, covered by photoetching process removal
Cover the silicon dioxide passivation layer 8 on 12 surface of active area.
The step S8 specifically: one cathode is generated by sputtering or multiple layer metal evaporation in the lower section of N+ substrate layer 2
Metal layer 10.
In conclusion the present invention has the advantages that
1, linearly changed by the dopant concentration of the dopant of N- epitaxial layer in vertical direction, concentration is higher more down, makes
The electric field for obtaining N- epitaxial layer is uniformly distributed in the horizontal direction, and then promotes the reverse blocking voltage of Schottky diode.
2, linearly changed by the dopant concentration of the dopant of N- epitaxial layer in vertical direction, concentration is higher more down, makes
It obtains and realizes high-concentration dopant on N- epitaxial layer, and then make Schottky diode that there is lower forward conduction resistance.
3, by etching the groove of active area and termination environment simultaneously, the size of trench schottky diode is reduced,
Reduce manufacturing cost.
4, by etching the groove of two termination environments, the resistance to pressure of trench schottky diode is improved, so that
The reliability of trench schottky diode greatly promotes.
Although specific embodiments of the present invention have been described above, those familiar with the art should be managed
Solution, we are merely exemplary described specific embodiment, rather than for the restriction to the scope of the present invention, it is familiar with this
The technical staff in field should be covered of the invention according to modification and variation equivalent made by spirit of the invention
In scope of the claimed protection.
Claims (10)
1. a kind of trench schottky diode, it is characterised in that: including a N- epitaxial layer and a N+ substrate layer, the N- extension
Layer is set to the top of the N+ substrate layer；The concentration of dopant of the N- epitaxial layer linearly changes in vertical direction, and close to N+
Concentration of dopant at substrate layer is maximum.
2. a kind of trench schottky diode as described in claim 1, it is characterised in that: the N- epitaxial layer is equipped with a plurality of
The groove of active area and the groove of two termination environments；Spacing between the groove of each active area is equal, described in adjacent two
The spacing of the groove of active area is greater than the spacing of the groove of two termination environments；The N- extension of the trench wall and termination environment
Layer upper surface is equipped with the grid oxide layer that a thickness is greater than 50nm, and full phosphorous doped polysilicon is filled in the groove；The trench depth
Greater than 0.5um.
3. a kind of trench schottky diode as described in claim 1, it is characterised in that: the upper surface of the active area is equipped with
One barrier metal layer, the termination environment upper surface are equipped with a passivation layer；The top of the barrier metal layer and passivation layer is equipped with
One anode metal layer.
4. a kind of trench schottky diode as described in claim 1, it is characterised in that: the lower section of the N+ substrate layer is equipped with
One cathode metal layer.
5. a kind of trench schottky diode manufacturing method, it is characterised in that: described method includes following steps:
Step S1, N- epitaxial layer is set to the top of N+ substrate layer；N- epitaxial layer and N+ substrate layer, which mix, dopant；N-
The dopant concentration of the dopant of epitaxial layer is less than the first concentration of setting, and linearly changes in vertical direction, and concentration is more more down
It is high；The dopant concentration of the dopant of N+ substrate layer is greater than the first concentration of setting and is less than the second concentration of setting；
Step S2, in one oxide layer of N- epitaxial layer disposed thereon, and a plurality of trench openings are formed in oxide layer；
Step S3, the groove for generating a plurality of active areas and two termination environments are etched on N- epitaxial layer by trench openings
Then groove removes removing oxide layer；
Step S4, a grid oxide layer, and deposit polycrystalline silicon are generated in N- epitaxial layer upper surface and trench wall；
Step S5, the grid oxide layer and polysilicon of the N- epitaxial layer upper surface of active area are removed, removal termination environment is higher than N- extension
The polysilicon of layer upper surface；
Step S6, a passivation layer is deposited in the upper surface of termination environment；
Step S7, after the upper surface of active area sputters a barrier metal layer, one anode metal layer of sputtering covers barrier metal layer
And passivation layer；
Step S8, a cathode metal layer is generated in the lower section of N+ substrate layer.
6. a kind of trench schottky diode manufacturing method as claimed in claim 5, it is characterised in that: in the step S1,
First concentration is 1 × 1019A/cm3, the second concentration is 1 × 1021A/cm3。
7. a kind of trench schottky diode manufacturing method as claimed in claim 5, it is characterised in that: in the step S3,
Spacing between the groove of each active area is equal；The spacing of the groove of adjacent two active area is greater than two termination environments
Groove spacing.
8. a kind of trench schottky diode manufacturing method as claimed in claim 5, it is characterised in that: in the step S3,
The depth of the groove is greater than 0.5um.
9. a kind of trench schottky diode manufacturing method as claimed in claim 5, it is characterised in that: the step S4 is specific
Are as follows: the grid oxide layer that a thickness is not less than 50nm is generated by the way of thermal oxide in N- epitaxial layer upper surface and trench wall,
And deposit phosphorous doped polysilicon.
10. a kind of trench schottky diode manufacturing method as claimed in claim 5, it is characterised in that: the step S5 tool
Body are as follows: the phosphorous doped polysilicon of N- epi-layer surface is deposited on by the removal of polycrystalline dry etch process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811572160.8A CN109713046A (en) | 2018-12-21 | 2018-12-21 | A kind of trench schottky diode and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811572160.8A CN109713046A (en) | 2018-12-21 | 2018-12-21 | A kind of trench schottky diode and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109713046A true CN109713046A (en) | 2019-05-03 |
Family
ID=66257107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811572160.8A Pending CN109713046A (en) | 2018-12-21 | 2018-12-21 | A kind of trench schottky diode and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109713046A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113903813A (en) * | 2021-09-30 | 2022-01-07 | 上海芯导电子科技股份有限公司 | Schottky diode, manufacturing method thereof and electronic device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060118833A1 (en) * | 2004-12-08 | 2006-06-08 | Stmicroelectronics S.A. | Vertical unipolar component periphery |
| CN101015059A (en) * | 2004-07-15 | 2007-08-08 | 飞兆半导体公司 | Schottky diode structure to reduce capacitance and switching losses and method of making same |
| CN102637595A (en) * | 2011-02-15 | 2012-08-15 | 陈自雄 | Trench schottky diode and manufacturing method thereof |
| KR101463078B1 (en) * | 2013-11-08 | 2014-12-04 | 주식회사 케이이씨 | Schottky barrier diode and fabricating method thereof |
| CN106449775A (en) * | 2016-10-31 | 2017-02-22 | 复旦大学 | GaN-based hybrid PIN Schottky diode and production method thereof |
-
2018
- 2018-12-21 CN CN201811572160.8A patent/CN109713046A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101015059A (en) * | 2004-07-15 | 2007-08-08 | 飞兆半导体公司 | Schottky diode structure to reduce capacitance and switching losses and method of making same |
| US20060118833A1 (en) * | 2004-12-08 | 2006-06-08 | Stmicroelectronics S.A. | Vertical unipolar component periphery |
| CN102637595A (en) * | 2011-02-15 | 2012-08-15 | 陈自雄 | Trench schottky diode and manufacturing method thereof |
| KR101463078B1 (en) * | 2013-11-08 | 2014-12-04 | 주식회사 케이이씨 | Schottky barrier diode and fabricating method thereof |
| CN106449775A (en) * | 2016-10-31 | 2017-02-22 | 复旦大学 | GaN-based hybrid PIN Schottky diode and production method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113903813A (en) * | 2021-09-30 | 2022-01-07 | 上海芯导电子科技股份有限公司 | Schottky diode, manufacturing method thereof and electronic device |
| CN113903813B (en) * | 2021-09-30 | 2024-02-09 | 上海芯导电子科技股份有限公司 | Schottky diode, preparation method thereof and electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107482050B (en) | Terminal structure of power device and manufacturing method thereof | |
| CN114068331B (en) | SGT terminal structure for improving BV stability and preparation method thereof | |
| CN109801958B (en) | Silicon carbide groove Schottky diode device and preparation method thereof | |
| US9443926B2 (en) | Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor | |
| US20160260844A1 (en) | Trench semiconductor device having multiple trench depths and method | |
| CN116387362A (en) | HJD integrated SiC UMOSFET device and preparation method thereof | |
| CN105655402A (en) | Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same | |
| CN105789331A (en) | Semiconductor rectifying device and manufacturing method therefor | |
| CN104103518A (en) | Method for manufacturing semiconductor power device | |
| TWI772714B (en) | Semiconductor device and method of manufacturing the same | |
| CN109065637B (en) | Groove Schottky barrier diode and manufacturing method thereof | |
| CN109713046A (en) | A kind of trench schottky diode and its manufacturing method | |
| CN110931569A (en) | Semiconductor device with Schottky metal junction and manufacturing method thereof | |
| CN103378171A (en) | Groove Schottky semiconductor device and preparation method thereof | |
| CN215342615U (en) | Full super junction MOSFET device structure | |
| CN103531617B (en) | One kind has channel terminal structure Schottky device and preparation method thereof | |
| CN111799336B (en) | SiC MPS diode device and preparation method thereof | |
| CN210607276U (en) | Groove type power device based on Schottky structure | |
| CN104733526A (en) | Channel type MOS P-N junction diode structure and manufacturing method thereof | |
| RU122204U1 (en) | Schottky Diode with Groove Structure | |
| CN203339171U (en) | Inclined trench superpotential barrier rectifying device | |
| CN113345954A (en) | Full super junction MOSFET device structure and manufacturing method thereof | |
| CN103367396A (en) | Super junction Schottky semiconductor device and preparation method thereof | |
| CN102222619B (en) | Semiconductor device manufacturing method | |
| CN103378178B (en) | Schottky semiconductor device with groove structures and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190503 |
|
| RJ01 | Rejection of invention patent application after publication |