CN109065637B - Groove Schottky barrier diode and manufacturing method thereof - Google Patents
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- 230000004888 barrier function Effects 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 56
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 claims description 4
- 230000007797 corrosion Effects 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000004026 adhesive bonding Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 abstract description 9
- 238000000926 separation method Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 12
- 230000007423 decrease Effects 0.000 description 9
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- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000011031 large-scale manufacturing process Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Abstract
A trench Schottky barrier diode comprises an active region in the middle and a stop region surrounding the active region, wherein the active region is sequentially provided with an N-type substrate layer, an N-type epitaxial layer, a gate oxide layer, a Schottky metal layer, an anode metal layer and a cathode metal layer from bottom to top; be equipped with a plurality of trenches and boss on the N type epitaxial layer, trench and boss lateral separation set up, and the deposit has the BPSG buffer layer between the gate oxide of boss and positive pole metal layer, and it has phosphorus-doped conductive polycrystalline silicon layer to fill in the trench, trench depth 1.3 mu m, trench width 0.5 mu m, trench interval 1.5 mu m and the thickness 1000A of oxide in the trench. According to the invention, by controlling the shape of the groove, the depth of the groove, the width of the active region between the grooves and the thickness of the oxide layer in the groove, the groove Schottky barrier diode with low reverse leakage, good voltage reverse blocking capability and good reliability is obtained. The invention also discloses a manufacturing method of the trench Schottky barrier diode, which has less steps and low manufacturing cost.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a trench Schottky barrier diode and a manufacturing method thereof.
Background
The rectifier device is used as an alternating current to direct current conversion device, and requires unidirectional conduction characteristics, namely low starting voltage and small conduction resistance during forward conduction, and high blocking voltage and small reverse leakage during reverse bias. Schottky barrier diodes have been used for decades in power applications as rectifying devices, which are well suited for switching power supplies and high frequency applications due to their low forward turn-on voltage and fast switching speed.
Schottky barrier diodes are fabricated using the metal-semiconductor junction principle of metal-to-semiconductor contact. Conventional planar schottky barrier diode devices are typically constructed by forming a schottky barrier interface from a low doping concentration N-epitaxial layer and a top deposited metal layer. The work function difference between metal and N-type single crystal silicon forms a potential barrier, and the height of the potential barrier determines the characteristics of the schottky barrier diode. The lower potential barrier can reduce the forward conduction starting voltage, but can increase the reverse leakage and reduce the reverse blocking voltage; conversely, a higher potential barrier increases the forward conduction starting voltage, reduces reverse leakage, and enhances reverse blocking capability.
However, the conventional planar schottky barrier diode has the disadvantage of poor blocking capability due to the effect of barrier lowering caused by the mirror force under the reverse bias. The trench type schottky diode is a trench type MOS schottky barrier diode invented by utilizing the MOS effect of metal-semiconductor-silicon (see the attached figure 1 in the specification) on the basis of a planar diode. The method is mainly characterized in that the grooves are pinched off in advance through the MOS effect along with the rise of reverse voltage, the electric field strength is reduced to zero before reaching the silicon surface, the surface breakdown is avoided, and the blocking capability is improved. In addition, compared with a planar diode, the planar diode has other incomparable advantages which are mainly shown in that the ESD and surge current resistance is enhanced, the chip area is smaller, and under the same substrate and metal conditions, the reverse leakage current is lower, the VF is lower and the like.
Disclosure of Invention
In order to solve the problems of low performance and reliability, large reverse leakage and poor reverse blocking capability of the trench Schottky barrier diode in the prior art, the invention provides the trench Schottky barrier diode with low reverse leakage, good voltage reverse blocking capability and good reliability by controlling the shape of the trench, the depth of the trench, the width of an active region between the trenches and the thickness of an oxide layer in the trench.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows: a trench Schottky barrier diode comprises an active region in the middle and a stop region surrounding the active region, wherein the active region is sequentially provided with a cathode metal layer, an N-type substrate layer, an N-type epitaxial layer, a gate oxide layer, a Schottky metal layer and an anode metal layer from bottom to top; the N-type epitaxial layer is provided with a plurality of grooves and bosses which are arranged at intervals transversely, BPSG buffer layers of 3% B and 4% P are deposited between a gate oxide layer and an anode metal layer of the bosses, phosphorus-doped conductive polycrystalline silicon layers are filled in the grooves, the depth of the grooves is 1.3 mu m, the width of the grooves is 0.5 mu m, the space between the grooves is 1.5 mu m, and the thickness of oxides in the grooves is equal to
The ideal device electrical parameters of 53V of breakdown voltage, 6 muA of leakage density and 0.44V of forward conduction voltage are obtained by controlling the size of the groove of the diode and the thickness of the oxide in the groove, the parameters are stable, the performance is reliable,is suitable for large-scale production.
The invention also provides a manufacturing method of the groove Schottky barrier diode, which comprises the following steps:
s1, growing a lightly doped N-type epitaxial layer on an N-type substrate layer;
s2, performing primary oxidation on the N-type epitaxial layer to form a primary oxidation layer;
s3, coating photoresist on the primary oxide layer, and defining a groove pattern by aligning exposure;
s4, selectively removing the primary oxide layer which is not protected by the photoresist by adopting a dry etching method, and controlling the thickness of the primary oxide layer to be smaller than that of the primary oxide layer
Exposing the N-type epitaxial layer corresponding to the groove pattern, and removing the photoresist;
s5, etching the N-type epitaxial layer corresponding to the exposed groove pattern by adopting a dry etching method to form grooves, wherein bosses are formed between the grooves by the N-type epitaxial layer protected by the primary oxide layer;
s6, pre-grid is carried out in the whole structure to form a pre-grid oxide layer, and then pre-grid oxidation corrosion is carried out; s7, carrying out gate oxidation in the whole structure to form a gate oxide layer;
s8, carrying out polycrystalline silicon deposition in the whole structure to form a polycrystalline silicon layer;
s9, carrying out polysilicon-phosphorus doping in the whole structure, forming a conductive polycrystalline silicon layer after thermal annealing, carrying out back etching on the conductive polycrystalline silicon layer at the boss part, completely removing a gate oxide layer and the polycrystalline silicon layer on the upper part of the oxide layer, and simultaneously enabling the top surface of the conductive polycrystalline silicon layer in the groove to be flush with the top surface of the boss;
s10, depositing BPSG with the concentration of 3% B and the concentration of 4% P on the boss to form a buffer layer;
s11, coating photoresist on the surface of the whole structure, performing contact hole photoetching in an alignment exposure manner by adopting a method of combining dry etching and wet etching to keep the periphery of the outermost periphery of the groove, and completely etching the oxide layer of the active region between the grooves;
s12, sputtering to form a Schottky barrier metal layer in the groove region by adopting a sputtering method, wherein the Schottky barrier metal layer is a titanium metal layer;
s13, depositing an anode metal layer on the surface of the whole structure, wherein the anode metal layer is an Al/Si/Cu metal layer and has the thickness of 4 microns; gluing, photoetching and corroding metal, and controlling the thickness of the anode metal layer to be 2.8 mu m;
s14, thinning the substrate by adopting a method of grinding the bottom surface of the monocrystalline silicon substrate, and depositing a cathode metal layer on the bottom surface of the monocrystalline silicon substrate to obtain the groove Schottky barrier diode, wherein the cathode metal layer is a Ti/Ni/Ag metal layer.
Preferably, in step S2, the thickness of the primary oxide layer is
Preferably, in step S5, the trench depth is 1.3 μm, the trench width is 0.5 μm, and the width of the active region between the trenches is 1.5 μm; the depth of the trench is controlled to be 1.3 μm, because the breakdown voltage characteristic curve of the device changes in an's' shape along with the increase of the depth of the trench, when the depth of the trench is relatively small, the breakdown voltage of the device increases relatively slowly and then increases rapidly, but when the depth of the trench is relatively deep, the increase of the breakdown voltage of the device gradually decreases, and the electric field intensity value of the schottky junction surface close to the trench decreases along with the increase of the depth of the trench, so the leakage current decreases along with the increase of the depth of the trench, but the decrease of the leakage current decreases when the depth of the trench reaches a certain value, which is mainly that the decrease of the surface electric field intensity value also decreases. Then, for the forward on voltage, the parasitic resistance of the device increases due to the increase of the depth of the trench, so that the forward on voltage of the device increases. In summary, we should fully consider the variation of these three key parameters when designing the device, and control the depth of the trench to be 1.3 μm; the width between the trenches is controlled to be 1.5 μm, because the breakdown voltage of the device is increased and then kept basically unchanged due to the increase of the distance between the trenches, and finally, when the distance between the trenches is larger, the breakdown voltage is reduced along with the increase of the distance. However, as schottky, we need not only to care about the breakdown voltage, but also cannot ignore the reverse leakage current and the forward on voltage, the leakage current increases with the increase of the distance between the trenches of the device, the largest influencing factor for the forward on voltage is the effective schottky junction area of the device, and the proportion of the effective schottky junction area of the device to the total area of the device increases with the increase of the distance between the trenches of the device, so the forward on voltage of the device decreases with the increase of the trench distance.
In summary, the influence of the inter-trench width on the breakdown voltage of the device is not monotonous, and the breakdown voltage, the leakage current density and the forward conduction voltage of the device are fully considered to select a selection which best meets the application requirement; the thickness of the trench oxide layer is controlled to be
Because the breakdown voltage of the device is increased and then reduced along with the increase of the thickness of the oxide layer in the groove, the invention finally controls the thickness of the oxide layer of the groove to be equal to
The width of the trench is 0.5 μm, which is the leading position in the existing trench etching process.
Preferably, in step S7, the gate oxide layer has a thickness of
Preferably, in step S8, the polysilicon layer has a thickness of
Compared with the prior art, the invention has the following beneficial effects: according to the invention, through a large number of experiments, the depth of a groove of the groove Schottky barrier diode is controlled to be 1.3 mu m, the width of the groove is controlled to be 0.5 mu m, the distance between the grooves is controlled to be 1.5 mu m, and the thickness of oxide in the groove is controlled
The trench Schottky barrier diode with ideal device electrical parameters of 53V breakdown voltage, 6 muA leakage density, 0.44V forward conduction voltage and the like is obtained, the parameters are stable, the performance is reliable, the reverse leakage is low, the voltage reverse blocking capability is good, and the reliability is good, and the trench Schottky barrier diode is suitable for large-scale production. According to the preparation method of the trench Schottky barrier diode, pre-gate oxidation and pre-gate oxidation corrosion are carried out before gate oxidation, so that the obtained trench is regular in shape and smooth in bottom surface, and a solid foundation is laid for excellent electrical properties of the trench Schottky. This thin layer will be the insulator between the gate and the channel, called the oxide gate, to distinguish it from the thicker oxide field that was originally grown. As feature sizes of integrated circuits decrease, the thickness of the gate oxide layer is also scaled down, mainly to prevent short-channel effects. If the channel length is continuously reduced and the thickness is not reduced proportionally, the threshold voltage is not stable.
Drawings
Figure 1 is a schematic cross section of a trench schottky barrier diode structure.
Wherein, 1, a substrate layer; 2. an epitaxial layer; 3. a gate oxide layer; 4. a Schottky barrier metal layer; 5. an anode metal layer; 6. a cathode metal layer; 7. a buffer layer; 8. a conductive polysilicon layer.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In order to facilitate the understanding of the technical solutions of the present invention for those skilled in the art, the technical solutions of the present invention will now be described in further detail with reference to the accompanying drawings.
As shown in fig. 1, a trench schottky barrier diode includes an active region in the middle and a stop region surrounding the active region, wherein the active region is sequentially provided with a cathode metal layer, a 6N-type substrate layer 1, an N-type epitaxial layer 2, a gate oxide layer 3, a schottky metal layer 4 and an anode metal layer 5 from bottom to top; the N-type epitaxial layer 2 is provided with a plurality of grooves and bosses which are arranged at intervals transversely, BPSG buffer layers 7 with the concentration of 3 percent B and 4 percent P are deposited between the gate oxide layers 3 and the anode metal layers 5 of the bosses, phosphorus-doped conductive polycrystalline silicon layers 8 are filled in the grooves, the depth of the grooves is 1.3 mu m, the width of the grooves is 0.5 mu m, the space between the grooves is 1.5 mu m, and the thickness of oxides in the grooves is 1.5 mu m
A method for manufacturing a trench Schottky barrier diode comprises the following steps:
step S1, growing a lightly doped N-type epitaxial layer 2 on the N-type substrate layer 1, wherein the thickness of the N-type epitaxial layer is 4.3 mu m;
step S2, performing preliminary oxidation on the N-type epitaxial layer to form a preliminary oxidation layer, and controlling the thickness of the oxidation layer to be
The purpose is toThe subsequent exposure of the groove pattern is facilitated;
step S3, coating photoresist on the primary oxide layer, and defining a groove pattern by aligning with the photoresist coated primary oxide layer;
step S4, selectively removing the initial oxide layer not protected by the photoresist by dry etching method, and controlling the thickness of the initial oxide layer to be less than
Exposing the N-type epitaxial layer corresponding to the groove pattern, and removing the photoresist;
step S7, performing gate oxidation in the whole structure to form a gate oxide layer, and controlling the thickness of the oxide layer to be
Step S8, depositing polysilicon to form polysilicon layer in the whole structure, and controlling the thickness of the polysilicon layer to be
Step S9, polysilicon phosphorus doping is carried out in the whole structure, a conductive polysilicon layer is formed after thermal annealing, and then back etching is carried out on the conductive polysilicon layer, so that the top surface of the conductive polysilicon layer in the groove is flush with the top surface of the boss;
step S10, depositing BPSG of 3% B and 4% P on the boss to form a buffer layer;
step S11, coating photoresist on the surface of the whole structure, aligning exposure to photoetching and reserving the periphery of the outermost periphery of the groove by adopting a method of combining dry etching and wet etching, etching all the oxide layers of the active regions between the grooves, and controlling the thickness of the oxide layers to be less than that of the oxide layers
Step S12, forming a Schottky barrier metal layer in the trench region by sputtering, wherein the Schottky barrier metal layer is a titanium metal layer, and the thickness of the Schottky barrier metal layer is controlled to be
And annealing at 750 deg.C for 30 s;
step S13, depositing an anode metal layer on the surface of the whole structure, wherein the anode metal layer is an Al/Si/Cu metal layer and has the thickness of 4 mu m; gluing, photoetching and corroding the anode metal layer, and controlling the thickness of the anode metal layer to be 2.8 mu m;
and step S14, thinning the substrate by adopting a method of grinding the bottom surface of the monocrystalline silicon substrate, and depositing a cathode metal layer on the bottom surface of the monocrystalline silicon substrate to obtain the groove Schottky barrier diode, wherein the cathode metal layer is a Ti/Ni/Ag metal layer.
In step S2, the oxide layer has a thickness of
In step S5, the depth of the trench is 1.3 μm, the width of the trench is 0.5 μm, and the width of the active region between the trenches is 1.5 μm.
In step S9, the gate oxide layer has a thickness of
In step S8, the polysilicon layer has a thickness of
In step S10, the buffer layer has a thickness of
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not intended to limit the present invention in any way, so that any person skilled in the art can make changes or modifications to the equivalent embodiments using the above disclosure. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, without departing from the technical solution of the present invention, still belong to the protection scope of the technical solution of the present invention.
Claims (5)
1. A manufacturing method of a trench Schottky barrier diode comprises an active region in the middle and a cut-off region surrounding the active region, wherein a cathode metal layer (6), an N-type substrate layer (1), an N-type epitaxial layer (2), a gate oxide layer (3), a Schottky metal layer (4) and an anode metal layer (5) are sequentially arranged in the active region from bottom to top; be equipped with a plurality of slots and boss on N type epitaxial layer (2), slot and boss horizontal interval set up, and the deposit has BPSG buffer layer (7) of 3% B and 4% P between gate oxide (3) and positive pole metal level (5) of boss, and it has phosphorus doping electrically conductive polycrystalline silicon layer (8), its characterized in that to fill at the ditch inslot: the depth of the trench is 1.3 μm, the width of the trench is 0.5 μm, the pitch of the trenches is 1.5 μm and the thickness of the oxide in the trench is
The method is characterized by comprising the following steps:
s1, growing a lightly doped N-type epitaxial layer on an N-type substrate layer;
s2, carrying out primary oxidation on the N-type epitaxial layer to form an oxide layer;
s3, coating photoresist on the oxide layer, and defining a groove pattern by aligning exposure;
s4, selectively removing the oxide layer which is not protected by the photoresist by adopting a dry etching method, and controlling the thickness of the oxide layer to be smaller than that of the oxide layer
Exposing the N-type epitaxial layer corresponding to the groove pattern, and removing the photoresist;
s5, etching the N-type epitaxial layer corresponding to the exposed groove pattern by adopting a dry etching method to form grooves, wherein bosses are formed between the grooves by the N-type epitaxial layer protected by the oxide layer;
s6, pre-grid is carried out in the whole structure to form a pre-grid oxide layer, and then pre-grid oxidation corrosion is carried out;
s7, carrying out gate oxidation in the whole structure to form a gate oxide layer;
s8, carrying out polycrystalline silicon deposition in the whole structure to form a polycrystalline silicon layer;
s9, carrying out polysilicon phosphorus doping in the whole structure, forming a conductive polysilicon layer after thermal annealing, and carrying out back etching on the conductive polysilicon layer at the boss part to enable the top surface of the conductive polysilicon layer in the groove to be flush with the top surface of the boss;
s10, depositing BPSG with the concentration of 3% B and the concentration of 4% P on the boss to form a buffer layer;
s11, coating photoresist on the surface of the whole structure, performing contact hole photoetching in an alignment exposure manner by adopting a method of combining dry etching and wet etching to keep the periphery of the outermost periphery of the groove, and completely etching the oxide layer of the active region between the grooves;
s12, sputtering to form a Schottky barrier metal layer in the groove region by adopting a sputtering method, wherein the Schottky barrier metal layer is a titanium metal layer;
s13, depositing an anode metal layer on the surface of the whole structure, wherein the anode metal layer is an Al/Si/Cu metal layer and has the thickness of 4 microns; gluing, photoetching and corroding metal, and controlling the thickness of the anode metal layer to be 2.8 mu m;
s14, thinning the substrate by adopting a method of grinding the bottom surface of the monocrystalline silicon substrate, and depositing a cathode metal layer on the bottom surface of the monocrystalline silicon substrate to obtain the groove Schottky barrier diode, wherein the cathode metal layer is a Ti/Ni/Ag metal layer.
2. The method of manufacturing a trench schottky barrier diode as described in claim 1, wherein: in step S2, the oxide layer has a thickness of
3. The method of manufacturing a trench schottky barrier diode as described in claim 1, wherein: in step S5, the trench depth is 1.3 μm, the trench width is 0.5 μm, and the width of the active region between the trenches is 1.5 μm.
4. The method of manufacturing a trench schottky barrier diode as described in claim 1, wherein: in step S7, the gate oxide layer has a thickness of
5. The method of manufacturing a trench schottky barrier diode as described in claim 1, wherein: in step S8, the polysilicon layer has a thickness of
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| EP1178539A2 (en) * | 2000-06-29 | 2002-02-06 | SILICONIX Incorporated | Schottky field-effect transistor |
| CN103094358A (en) * | 2011-11-01 | 2013-05-08 | 比亚迪股份有限公司 | Schottky diode and manufacturing method thereof |
| CN103681316A (en) * | 2012-09-14 | 2014-03-26 | 北大方正集团有限公司 | Deep-trench Schottky barrier diode and process method thereof |
| JP2017028150A (en) * | 2015-07-24 | 2017-02-02 | サンケン電気株式会社 | Semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1178539A2 (en) * | 2000-06-29 | 2002-02-06 | SILICONIX Incorporated | Schottky field-effect transistor |
| CN103094358A (en) * | 2011-11-01 | 2013-05-08 | 比亚迪股份有限公司 | Schottky diode and manufacturing method thereof |
| CN103681316A (en) * | 2012-09-14 | 2014-03-26 | 北大方正集团有限公司 | Deep-trench Schottky barrier diode and process method thereof |
| JP2017028150A (en) * | 2015-07-24 | 2017-02-02 | サンケン電気株式会社 | Semiconductor device |
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