CN103681316A - Deep-trench Schottky barrier diode and process method thereof - Google Patents
Deep-trench Schottky barrier diode and process method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 67
- 230000008569 process Effects 0.000 title claims abstract description 42
- 230000004888 barrier function Effects 0.000 title claims abstract description 24
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 46
- 239000000956 alloy Substances 0.000 claims abstract description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 239000011241 protective layer Substances 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims description 39
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 239000003595 mist Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 5
- 230000008021 deposition Effects 0.000 abstract description 3
- 230000002159 abnormal effect Effects 0.000 abstract 1
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 230000000873 masking effect Effects 0.000 description 9
- 238000012360 testing method Methods 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002894 chemical waste Substances 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000006056 electrooxidation reaction Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000010330 laser marking Methods 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 150000003254 radicals Chemical class 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004347 surface barrier Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- H01L29/66143—Schottky diodes
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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Abstract
The invention discloses a deep-trench Schottky barrier diode and a process method thereof. The method comprises the following steps: carrying out silicon trench etching, grid oxide layer growth, polysilicon deposition and etching back, insulating-medium deposition, Schottky barrier contact formation and protective layer treatment on a semiconductor silicon epitaxial wafer to obtain a deep-trench Schottky barrier diode wafer; carrying out alloy treatment on the deep-trench Schottky barrier diode wafer, and then carrying out back treatment on the alloyed deep-trench Schottky barrier diode wafer to obtain the deep-trench Schottky barrier diode, wherein the main process time for the alloy treatment is from 45 to 180 minutes. Compared with the prior art, the deep-trench Schottky barrier diode and the process method thereof, disclosed by the invention, have the advantage of longer main process time for the alloy treatment, so that stress and mobile charges in the deep-trench Schottky barrier diode wafer can be released to the greatest extent to avoid abnormal fluctuation of reverse leakage parameters of the deep-trench Schottky barrier diode. Therefore, the effects of reducing reverse leakage current and enhancing the yield of products can be reached.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of deep trench Schottky diode and manufacturing process thereof.
Background technology
Schottky diode (Schottky Barrier Diode, SBD), is called again metal-semiconductor diode or surface barrier diode, is the majority carrier diode that a kind of metal-semiconductor junction that utilizes metal to contact with semiconductor and form is made.
Schottky diode has low-power consumption, large electric current, superfast characteristic, when adding lower forward bias voltage to it, just can produce larger forward current, if but while adding to it reverse biased continuing to increase, can produce larger reverse leakage electric current.In order to reduce the reverse leakage electric current of Schottky diode, improve quality and the reliability of Schottky diode, industry has proposed the Schottky diode of zanjon slot type, by insert polysilicon or metal in groove, carry out the reverse leakage electric current of pinching Schottky diode, thereby reach the object that reduces Schottky diode reverse leakage electric current.
At present, industry often adopts following methods to make deep trench Schottky diode, described method mainly comprises the following steps: semiconductor silicon epitaxial wafer is carried out silicon groove etching, gate oxidation layer growth, polysilicon deposit and returns the formation, protective layer processing etc. of quarter, dielectric deposit, Schottky Barrier Contact, obtain deep trench Schottky diode wafer; Described deep trench Schottky diode wafer is carried out to alloy treatment, and the deep trench Schottky diode wafer of alloy after processing carry out back side processing, obtain deep trench Schottky diode; Wherein, described alloy treatment is the important reparation step in deep trench Schottky diode manufacturing process, is mainly: by high temperature, (as 425 ℃ of left and right) lead to N in deep trench Schottky diode production environment
2or N
2and H
2the mode of mist, discharge in deep trench Schottky diode manufacturing process the stress that the techniques such as on silicon chip digging groove produce and silicon chip carried out to the movable charge that the techniques such as etching produce, reaching the object that reduces deep trench Schottky diode reverse leakage electric current.
But, because main process time of alloy treatment described in prior art is only about 30 minutes, time is shorter, cannot fully discharge stress and movable charge in deep trench Schottky diode wafer, thereby cause the reverse leakage electric current of prepared deep trench Schottky diode still larger, device performance is not good.
Summary of the invention
The embodiment of the present invention provides a kind of deep trench Schottky diode and manufacturing process thereof, in order to solve the larger problem of deep trench Schottky diode reverse leakage electric current existing in prior art.
A manufacturing process for deep trench Schottky diode, comprises the following steps:
Semiconductor silicon epitaxial wafer is carried out to formation and the protective layer of silicon groove etching, gate oxidation layer growth, polysilicon deposit and time quarter, dielectric deposit, Schottky Barrier Contact and process, obtain deep trench Schottky diode wafer;
Described deep trench Schottky diode wafer is carried out to alloy treatment, and wherein, the main process time of described alloy treatment is 45 ~ 180 minutes;
Deep trench Schottky diode wafer after alloy is processed carries out back side processing, obtains deep trench Schottky diode.
Further, the main process time of described alloy treatment is 60 ~ 120 minutes.
Further, the main process time of described alloy treatment is 60 minutes or 90 minutes.
Particularly, the technical process of described alloy treatment is to lead to N in the technique production environment of deep trench Schottky diode
2or N
2and H
2mist.
A deep trench Schottky diode, wherein, described deep trench Schottky diode is to utilize the manufacturing process of above-mentioned deep trench Schottky diode to be made.
Beneficial effect of the present invention is:
The embodiment of the present invention provides a kind of deep trench Schottky diode and manufacturing process thereof, by the main process time of the alloy treatment relating in deep trench Schottky diode manufacturing process is carried out to proper extension, thereby stress and movable charge in deep trench Schottky diode wafer have been reduced to a greater degree, improved the stability of device production technique, avoid the unusual fluctuations of deep trench Schottky diode reverse leakage parameter, reached the effect that reduces deep trench Schottky diode reverse leakage electric current, improves product yield and quality.
Accompanying drawing explanation
Figure 1 shows that the manufacturing process idiographic flow schematic diagram of deep trench Schottky diode in the embodiment of the present invention one;
Figure 2 shows that the manufacturing process deep trench Schottky diode being made and the reverse leakage current parameters comparison diagram that adopts the prepared deep trench Schottky diode of prior art that adopt deep trench Schottky diode described in the embodiment of the present invention one;
Figure 3 shows that the manufacturing process deep trench Schottky diode being made and the forward voltage drop comparative bid parameter that adopts the prepared deep trench Schottky diode of prior art that adopt deep trench Schottky diode described in the embodiment of the present invention one;
Figure 4 shows that the manufacturing process deep trench Schottky diode being made and the reverse breakdown voltage comparative bid parameter that adopts the prepared deep trench Schottky diode of prior art that adopt deep trench Schottky diode described in the embodiment of the present invention one.
Embodiment
For Schottky diode, when it being carried out to yield test, generally need to test the parameters such as its forward voltage drop, reverse breakdown voltage, reverse leakage electric current, the reverse leakage electric current of wherein controlling Schottky diode is very crucial, although the reverse leakage electric current of prepared Schottky diode can reach tens to 100 microamperes in prior art, but in fact, in order further to improve the stability of Schottky diode manufacture craft, the power consumption that reduces Schottky diode, raising switching speed, the reverse leakage electric current of Schottky diode is the smaller the better.
For this reason, the embodiment of the present invention provides a kind of manufacturing process of deep trench Schottky diode, described method mainly comprises the following steps: semiconductor silicon epitaxial wafer is carried out silicon groove etching, gate oxidation layer growth, polysilicon deposit and returns the formation, protective layer processing etc. of quarter, dielectric deposit, Schottky Barrier Contact, obtain deep trench Schottky diode wafer; Described deep trench Schottky diode wafer is carried out to alloy treatment, and the deep trench Schottky diode wafer of alloy after processing carry out back side processing, obtain deep trench Schottky diode, wherein, the main process time of described alloy treatment is 45 ~ 180 minutes; By the main process time of the alloy treatment operation relating in deep trench Schottky diode manufacturing process in prior art is carried out to corresponding prolongation, thereby stress and movable charge in deep trench Schottky diode wafer have been reduced to a greater degree, improved the stability of device production technique, avoid the unusual fluctuations of deep trench Schottky diode reverse leakage parameter, reached the effect that reduces reverse leakage electric current, improves product yield and quality.
Below in conjunction with Figure of description, embodiments of the present invention is further illustrated, but the present invention is not limited to the following examples.
Embodiment mono-:
It should be noted that, the embodiment of the present invention one is the detailed description to the manufacturing process of deep trench Schottky diode described in the embodiment of the present invention, as shown in Figure 1, manufacturing process idiographic flow schematic diagram for deep trench Schottky diode described in the embodiment of the present invention one, said method comprising the steps of:
Step 101: epitaxial wafer cleans.
Particularly, in this step 101, need to epitaxial wafer raw material test, laser marking and brushing piece clean, the epitaxial wafer after the cleaning that obtains needing, described epitaxial wafer is generally semiconductor silicon epitaxial wafer.
Step 102: oxidation masking layer growth, the photoetching of masking layer figure, etching, remove photoresist and clean.
Particularly, in this step 102, need to carry out the operations such as oxidation masking layer growth, the photoetching of masking layer figure and etching to the semiconductor silicon epitaxial wafer after cleaning, while carrying out oxidation masking layer growth on the semiconductor silicon epitaxial wafer after cleaning, the material of described oxidation masking layer can be SiO
2.
Further, before carrying out the operations such as the photoetching of masking layer figure and etching, need on described oxidation masking layer, deposit one deck photoresist layer, described photoresist can be photoresist.
Particularly, due to dry etching have anisotropy good, select than high, reproducible, without chemical waste fluid, cleanliness factor advantages of higher, therefore, in method described in the embodiment of the present invention one, when carrying out the etching operation of masking layer figure, preferentially adopt dry etching, as reactive ion etching (Reactive Ion Etching, RIE) or the method such as Assisted by Ion Beam free radical etching (Inductively Coupled Plasma, ICP).
Step 103: silicon groove etching and cleaning.
Particularly, in this step 103, can adopt dry etching, as RIE carries out the etching operation of silicon groove to the resulting semiconductor silicon epitaxial wafer of step 102.
Step 104: sacrificial oxide layer is grown and divested.
Particularly, in this step 104, the operation such as need to carry out sacrificial oxide layer growth on the resulting semiconductor silicon epitaxial wafer of step 103 and divest, described sacrificial oxide layer material can be SiO
2.In this step 104, by growth sacrificial oxide layer the operating process that divested, reach and modify after the etching operation of step 103 the surperficial object of silicon groove in resulting semiconductor silicon epitaxial wafer.
Step 105: gate oxidation layer growth and polysilicon deposit.
Particularly, in this step 105, need on the resulting semiconductor silicon epitaxial wafer of step 104, carry out the growth of grid oxic horizon, and adopt the methods such as chemical vapour deposition (CVD) (Chemical Vapor Deposition, CVD) to carry out deposit spathic silicon on the grid oxic horizon after growth.
Step 106: polysilicon returns quarter.
Particularly, in this step 106, can adopt to anti-carve etching technique and remove after the operation of step 105 unwanted part in formed polysilicon.The described etching technique that anti-carves is not used any photo anti-corrosion agent material, but the time that foundation sets is carried out downward etching to the polysilicon generating equably.
Step 107: dielectric deposit.
Particularly, in this step 107, can adopt CVD method to generate needed insulating medium layer on the resulting semiconductor silicon epitaxial wafer of step 106.
Step 108: contact hole graph photoetching, etching, remove photoresist and clean.
The object of this step 108 is to open the contact silicon plane of schottky diode device, when carrying out the operation of this step 108, has both needed the insulating medium layer etching at contact hole place totally, can not cause too large damage to substrate silicon again.Particularly, in this step 108, still can adopt dry etching, as RIE carries out the etching operation of contact hole graph.
Step 109: clean before barrier metal deposit.
This step 109 is one of the steps that form the most critical of Schottky Barrier Contact, directly affects performance and the speed of schottky diode device; Particularly, in this step 109, in order to make Schottky Barrier Contact good, can adopt wet processing, as the substrate silicon that the HF acid that utilizes dilution is exposed after to step 108 etching is carried out the cleaning before deposit, to remove the SiO on substrate silicon surface
2oxide layer.
Step 110: barrier metal deposit and annealing.
Particularly, described barrier metal can be Ti metal etc., in this step 110, can adopt the method for vacuum evaporation or sputter to carry out deposit barrier metal in the substrate silicon after step 109 is cleaned, simultaneously in order to make the Si in barrier metal and backing material carry out effecting reaction, form the Schottky Barrier Contact needing, need to after deposit barrier metal, to it, carry out annealing in process.
Step 111: front side aluminum deposit.
Particularly, in this step 111, can adopt electron beam evaporation process on the resulting semiconductor silicon epitaxial wafer of step 110, to carry out the deposit of aluminium.
Step 112: front side aluminum photoetching, etching, remove photoresist and clean.
Particularly, in this step 112, still can adopt dry etching, as RIE etc. carries out the etching operation of front side aluminum.
Step 113: protective layer dielectric deposition.
Particularly, described protective layer medium can be Si
3n
4, tetraethoxysilane (TEOS) or SiO
2deng, be mainly used in isolating steam, prevent that metal level is corroded or prevents unexpected scuffing etc.
Step 114: the photoetching of protective layer figure, etching, remove photoresist and clean.
Particularly, in this step 114, still can adopt dry etching, as RIE etc. carries out the etching operation of protective layer figure.
It should be noted that, after completing steps 101 ~ step 114, can obtain deep trench Schottky diode wafer.
Step 115: alloy treatment, wherein, the main process time of described alloy treatment is 45～180 minutes.
This step 115 is important reparation steps in deep trench Schottky diode manufacture craft described in the present embodiment one, main by high temperature to logical N in deep trench Schottky diode production environment
2or N
2and H
2the mode of mist, discharge stress and movable charge in deep trench Schottky diode wafer, reach the object that reduces deep trench Schottky diode reverse leakage electric current.
Particularly, in this step 115, the main process time of alloy treatment is 45 ~ 180 minutes; Compared with prior art, at other technological parameters, all under unaltered prerequisite, increased the main process time of alloy treatment.
Further, in order to take into account the make efficiency of deep trench Schottky diode and the quality of deep trench Schottky diode, the main process time of described alloy treatment, without long, can be 60 ~ 120 minutes; Preferably, the main process time of described alloy treatment can be 60 minutes or 90 minutes.
Step 116: silicon chip back side attenuate, the corrosion of back side silicon.
Particularly, can adopt the methods such as grinding, grinding, chemico-mechanical polishing, electrochemical corrosion, plasma-assisted chemical corrosion to carry out silicon chip back side reduction processing to the deep trench Schottky diode wafer after alloy treatment, to reach the effect of attenuate silicon chip, thickness thinning is determined by packaging technology.
Step 117: back metal evaporation.
Particularly, can adopt vacuum vapor deposition method at the back side of the resulting deep trench Schottky diode wafer of step 116, to carry out the evaporation of electrode metal, obtain deep trench Schottky diode.
Step 118: visual examination and electric parameters testing etc.
Particularly, in this step 118, when the deep trench Schottky diode to making carries out electric parameters testing, generally need to test the parameters such as its forward voltage drop, reverse breakdown voltage, reverse leakage electric current.
As shown in Figure 2, in order to utilize the manufacturing process of deep trench Schottky diode described in the embodiment of the present invention one, (take main process time of alloy treatment is 60 minutes, temperature is that 425 ℃ of left and right are example) the deep trench Schottky diode being made and the reverse leakage current parameters comparison diagram that adopts the prepared deep trench Schottky diode of prior art (the main process time of alloy treatment is 30 minutes, and temperature is 425 ℃ of left and right).
In the deep trench Schottky diode reverse leakage current parameters comparison diagram shown in Fig. 2, transverse axis represents the quantity (unit: individual) of test products, and the longitudinal axis represents the size (unit: ampere) of reverse leakage electric current; As seen from Figure 2, described in the employing embodiment of the present invention one, the reverse leakage electric current of the prepared more than 95% deep trench Schottky diode of method can be at 10 microampere (1.00 * 10
-5a) following (representative value reality is lower), and adopt the reverse leakage electric current of the deep trench Schottky diode that only has 1% left and right in the resulting deep trench Schottky diode of existing manufacture method can be below 10 microamperes, that is, the main process time of alloy treatment is that the reverse leakage electric current of 60 minutes prepared deep trench Schottky diodes is significantly less than the reverse leakage electric current that the main process time of alloy treatment is 30 minutes prepared deep trench Schottky diodes.
It should be noted that, in the embodiment of the present invention one, the main process time of original alloy treatment in deep trench Schottky diode manufacturing process was extended to 60 minutes from 30 minutes, the reverse leakage electric current of resulting deep trench Schottky diode can significantly reduce, but the parameters such as its forward voltage drop, reverse breakdown voltage do not have to change substantially.
As shown in Figure 3, in order to utilize the manufacturing process of deep trench Schottky diode described in the embodiment of the present invention one, (take main process time of alloy treatment is 60 minutes, temperature is that 425 ℃ of left and right are example) the deep trench Schottky diode being made and the forward voltage drop comparative bid parameter that adopts the prepared deep trench Schottky diode of prior art (the main process time of alloy treatment is 30 minutes, and temperature is 425 ℃ of left and right); In the deep trench Schottky diode forward voltage drop comparative bid parameter shown in Fig. 3, transverse axis represents the quantity (unit: individual) of test products, and the longitudinal axis represents the size (unit: V) of forward voltage drop; As seen from Figure 3, the main process time of alloy treatment is that the forward voltage drop of 60 minutes prepared deep trench Schottky diodes will be the forward voltage drop of 30 minutes prepared deep trench Schottky diodes slightly higher than the main process time of alloy treatment, but change little, and the main process time of alloy treatment be that the uniformity of forward voltage drop of 60 minutes prepared deep trench Schottky diodes is better.
As shown in Figure 4, in order to utilize the manufacturing process of deep trench Schottky diode described in the embodiment of the present invention one, (take main process time of alloy treatment is 60 minutes, temperature is that 425 ℃ of left and right are example) the deep trench Schottky diode being made and the reverse breakdown voltage comparative bid parameter that adopts the prepared deep trench Schottky diode of prior art (the main process time of alloy treatment is 30 minutes, and temperature is 425 ℃ of left and right).In the deep trench Schottky diode reverse breakdown voltage comparative bid parameter shown in Fig. 4, transverse axis represents the quantity (unit: individual) of test products, and the longitudinal axis represents the size (unit: V) of forward voltage drop; As seen from Figure 4, the main process time of alloy treatment is that the reverse breakdown voltage of 60 minutes prepared deep trench Schottky diodes will be the reverse breakdown voltage of 30 minutes prepared deep trench Schottky diodes slightly higher than the main process time of alloy treatment, but changes also little.
It should be noted that, the manufacturing process of deep trench Schottky diode can repeatedly repeat described in the embodiment of the present invention one, all shows the reverse leakage electric current that can effectively reduce deep trench Schottky diode.
The embodiment of the present invention provides a kind of deep trench Schottky diode and manufacturing process thereof, by the main process time of the alloy treatment operation relating in deep trench Schottky diode manufacturing process in prior art is carried out to corresponding prolongation, thereby stress and movable charge in deep trench Schottky diode wafer have been reduced to a greater degree, improved the stability of device production technique, avoid the unusual fluctuations of deep trench Schottky diode reverse leakage parameter, reached the effect that reduces reverse leakage electric current, improves product yield and quality.
The above is only the preferred embodiments of the invention, and obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (5)
1. a manufacturing process for deep trench Schottky diode, is characterized in that, comprises the following steps:
Semiconductor silicon epitaxial wafer is carried out to formation and the protective layer of silicon groove etching, gate oxidation layer growth, polysilicon deposit and time quarter, dielectric deposit, Schottky Barrier Contact and process, obtain deep trench Schottky diode wafer;
Described deep trench Schottky diode wafer is carried out to alloy treatment, and wherein, the main process time of described alloy treatment is 45 ~ 180 minutes;
Deep trench Schottky diode wafer after alloy is processed carries out back side processing, obtains deep trench Schottky diode.
2. the manufacturing process of deep trench Schottky diode as claimed in claim 1, is characterized in that, the main process time of described alloy treatment is 60 ~ 120 minutes.
3. the manufacturing process of deep trench Schottky diode as claimed in claim 2, is characterized in that, the main process time of described alloy treatment is 60 minutes or 90 minutes.
4. the manufacturing process of deep trench Schottky diode as claimed in claim 1, is characterized in that, the technical process of described alloy treatment is to lead to N in the technique production environment of deep trench Schottky diode
2or N
2with H
2mist.
5. a deep trench Schottky diode, is characterized in that, described deep trench Schottky diode is for to utilize the manufacturing process of the arbitrary deep trench Schottky diode of the claims 1 ~ 4 to be made.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109065637A (en) * | 2018-07-13 | 2018-12-21 | 张家港意发功率半导体有限公司 | A kind of trench schottky barrier diode and its manufacturing method |
| CN109390231A (en) * | 2017-08-08 | 2019-02-26 | 天津环鑫科技发展有限公司 | A kind of manufacturing method of channel schottky front silver surface metal structure |
| CN109390230A (en) * | 2017-08-08 | 2019-02-26 | 天津环鑫科技发展有限公司 | A kind of manufacturing method of channel schottky front silver surface metal structure |
| CN113628972A (en) * | 2021-07-07 | 2021-11-09 | 华虹半导体(无锡)有限公司 | Manufacturing method of groove type MOS device |
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Cited By (7)
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| CN109390231A (en) * | 2017-08-08 | 2019-02-26 | 天津环鑫科技发展有限公司 | A kind of manufacturing method of channel schottky front silver surface metal structure |
| CN109390230A (en) * | 2017-08-08 | 2019-02-26 | 天津环鑫科技发展有限公司 | A kind of manufacturing method of channel schottky front silver surface metal structure |
| CN109390230B (en) * | 2017-08-08 | 2021-07-16 | 天津环鑫科技发展有限公司 | Manufacturing method of groove type Schottky front silver surface metal structure |
| CN109390231B (en) * | 2017-08-08 | 2021-10-08 | 天津环鑫科技发展有限公司 | Manufacturing method of groove type Schottky front silver surface metal structure |
| CN109065637A (en) * | 2018-07-13 | 2018-12-21 | 张家港意发功率半导体有限公司 | A kind of trench schottky barrier diode and its manufacturing method |
| CN109065637B (en) * | 2018-07-13 | 2021-07-16 | 张家港意发功率半导体有限公司 | Groove Schottky barrier diode and manufacturing method thereof |
| CN113628972A (en) * | 2021-07-07 | 2021-11-09 | 华虹半导体(无锡)有限公司 | Manufacturing method of groove type MOS device |
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