CN112786684A - Super junction device for improving EMI (electro-magnetic interference) and reducing characteristic resistance and manufacturing method thereof - Google Patents

Super junction device for improving EMI (electro-magnetic interference) and reducing characteristic resistance and manufacturing method thereof Download PDF

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CN112786684A
CN112786684A CN202110046715.0A CN202110046715A CN112786684A CN 112786684 A CN112786684 A CN 112786684A CN 202110046715 A CN202110046715 A CN 202110046715A CN 112786684 A CN112786684 A CN 112786684A
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epitaxy
layer
upper side
region
doping
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何军
胡兴正
薛璐
刘海波
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Chuzhou Huarui Microelectronics Technology Co ltd
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Chuzhou Huarui Microelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

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Abstract

The invention discloses a super junction device for improving EMI (electro-magnetic interference) and reducing characteristic resistance and a manufacturing method thereof. The device comprises a substrate, a plurality of layers of first epitaxy arranged on the upper side of the substrate and a plurality of layers of second epitaxy arranged on the upper side of the first epitaxy, wherein the upper side of each layer of the first epitaxy is doped with a doping region of a first conductive type, a plurality of doping regions of second conductive types arranged at intervals are manufactured and formed, the doping regions of the second conductive types on the plurality of layers of the first epitaxy are arranged along the vertical direction, a plurality of grooves are formed on the second epitaxy in an etching mode, each groove is arranged on the upper side of a column of doping regions of the second conductive type, impurities of the second conductive type are filled back in each groove, and second conductive type connecting columns are connected between two longitudinally adjacent doping regions of the second conductive type and between each groove and the doping region of the second conductive type on the lower side of the groove. The invention has lower characteristic resistance per unit area, good EMI characteristic and moderate complexity of the manufacturing process.

Description

Super junction device for improving EMI (electro-magnetic interference) and reducing characteristic resistance and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a super junction device for improving EMI (electro magnetic interference) and reducing characteristic resistance and a manufacturing method thereof.
Background
The super-junction power device breaks through silicon limitation, compared with the traditional VDMOS, a product with characteristic resistance of unit area being lower by about 80%, lower on-state power consumption, lower switching loss, higher switching speed and lower energy consumption can be obtained, when the super-junction power device needs to be more than 1200V, the epitaxial thickness needs to be more than 110um, 1) if the super-junction MOS manufactured by using the groove type process is used, compared with the traditional VDMOS process, the super-junction structure can be formed only by adding deep groove photoetching, etching and epitaxial backfilling once, but because of the limitation of EPI backfilling process characteristics, the depth limit of the groove is about 55-60 um, the bottom of the groove only can use high-resistance epitaxy, and compared with the traditional MOS, the super-junction device Rsp manufactured by the method has little advantages and poor EMI characteristics; 2) if a multi-time epitaxial super junction process is used, the EMI characteristic is good, but the super junction structure can be formed only by adding about 15 times of photoetching, the manufacturing process is complex, and the cost is high.
Disclosure of Invention
The invention aims to provide a super junction device for improving EMI (electro-magnetic interference) and reducing characteristic resistance and a manufacturing method thereof, aiming at the defects in the prior art.
In order to achieve the above object, in a first aspect, the present invention provides a super junction device for improving EMI and reducing characteristic resistance, including a substrate of a first conductivity type and an epitaxy disposed on an upper side of the substrate, the epitaxy includes a plurality of first epitaxy layers disposed on the upper side of the substrate and a second epitaxy layer disposed on the upper side of the first epitaxy layer, each layer of the first epitaxy layer is doped with a doped region of the first conductivity type, and a plurality of doped regions of the second conductivity type are formed at intervals, the doped regions of the second conductivity type on the plurality of layers of the first epitaxy layers are arranged in a vertical direction, a plurality of trenches are etched on the second epitaxy layer, each trench is disposed on an upper side of a column of doped regions of the second conductivity type, and is filled with impurities of the second conductivity type, a second conductivity type connection column is connected between two longitudinally adjacent doped regions of the second conductivity type and between a trench and a doped region of the second conductivity type on a lower side of the trench, the epitaxial upside on terminal area is long to have a field oxygen layer, in the active area the epitaxial upside of the second of slot both sides is long to have a gate oxide, gate oxide upside and field oxygen layer's inner upside are equipped with the polycrystal of doping, in the active area the upper end of slot and the second between active area and the terminal area are epitaxial the preparation in the district that has the second conductive type, be equipped with the well region of first conductive type in the district, the upside deposit on polycrystal, district and field oxygen layer has the dielectric layer, be equipped with the connecting hole on the dielectric layer, the upside sputtering of dielectric layer in the connecting hole and in the dielectric layer is formed with the metal layer, the metal layer sculpture forms grid region and source region.
Further, the resistivity of the first epitaxy is 20 to 40 Ω -cm, and the resistivity of the second epitaxy is 3 to 7 Ω -cm.
Further, the thickness of the first epitaxy at the lowest side is 12 to 15 μm, and the thickness of the remaining first epitaxy is 5 to 8 μm.
Further, the first epitaxy comprises 6 to 10 layers.
Further, the second extension has a thickness of 50 to 60 μm.
In a second aspect, the present invention provides a method for manufacturing a superjunction device with improved EMI and reduced characteristic resistance, including:
providing a substrate of a first conductive type, firstly manufacturing a layer of first epitaxy on the substrate, and forming a doped region of the first conductive type and a plurality of doped regions of a second conductive type arranged at intervals on the upper side of the first epitaxy through impurity injection;
growing a layer of first epitaxy on the upper side of the first epitaxy, then forming a first conductive type doping region and a plurality of second conductive type doping regions arranged at intervals on the upper side of the layer of first epitaxy through impurity injection, and repeating the steps for a plurality of times, wherein the second conductive type doping regions on the plurality of layers of first epitaxy are vertically arranged;
growing a layer of second epitaxy on the uppermost layer of the first epitaxy, etching the second epitaxy to form a plurality of grooves, wherein each groove is arranged on the upper side of the row of doping regions of the second conductivity type, and backfilling impurities of the second conductivity type into the plurality of grooves;
connecting columns of the second conductivity type are formed in the multi-layer first epitaxy and the second epitaxy in an implantation mode, and the connecting columns are respectively connected between two longitudinally adjacent doping regions of the second conductivity type and between the groove and the doping region of the second conductivity type on the lower side of the groove;
growing a field oxide layer on the second epitaxy, and etching and removing the field oxide layer in the active region;
and growing a gate oxide layer on the upper side of the second epitaxy in the active region, depositing polycrystal on the upper sides of the gate oxide layer and the field oxide layer, and then doping and etching the polycrystal.
Manufacturing a body region of a second conduction type in the upper end of the groove in the active region and a second extension between the active region and the terminal region, and manufacturing a well region of a first conduction type in the body region;
depositing a dielectric layer on the upper sides of the polycrystal, the body region and the field oxide layer, and etching the dielectric layer to form a connecting hole;
and sputtering a metal layer in the connecting hole and on the upper side of the dielectric layer, and etching the metal layer to form a gate region and a source region.
Further, the resistivity of the first epitaxy is 20 to 40 Ω -cm, and the resistivity of the second epitaxy is 3 to 7 Ω -cm.
Further, the thickness of the first epitaxy at the lowest side is 12 to 15 μm, and the thickness of the remaining first epitaxy is 5 to 8 μm.
Further, the first epitaxy comprises 6 to 10 layers.
Further, the second extension has a thickness of 50 to 60 μm.
Has the advantages that: the invention is characterized in that a plurality of layers of first epitaxy with high resistivity are manufactured on the upper side of a substrate, a plurality of doping regions with second conductivity type are manufactured in the first epitaxy at intervals, a second epitaxy with relatively lower resistivity is manufactured on the upper side of the first epitaxy, the grooves are manufactured on the second epitaxy, the doped regions of the second conduction type and the connecting columns formed by injection and push-in wells are connected into a whole, after the drive well, the doped region of the first conduction type in the first epitaxy can be diffused, so that the resistivity of the first epitaxy is reduced, the parameter stability and consistency of the device are better, and combines the characteristics of the groove type process super junction, the super junction device with a complete super junction structure can be manufactured by using the method, the device has lower characteristic resistance per unit area, good EMI characteristic and moderate complexity of manufacturing process.
Drawings
FIG. 1 is a schematic view of the structure after a first epitaxy is formed on the upper side of the substrate;
FIG. 2 is a schematic view of the structure after fabricating a multi-layer epitaxy on the upper side of the substrate;
FIG. 3 is a schematic diagram of the structure after trenches are formed on the second epitaxy and backfilled;
FIG. 4 is a schematic diagram of the structure after fabrication of the connection post in the first and second epitaxy;
FIG. 5 is a schematic view of a structure for forming a field oxide layer on the second epitaxial upper side of the termination region;
FIG. 6 is a schematic diagram of the structure after gate oxide and poly are formed on the second epitaxy upper side and etched;
fig. 7 is a schematic diagram of the structure after the body region of the second conductivity type is fabricated in the second epitaxy;
fig. 8 is a schematic structural diagram of a well region of a first conductivity type formed in a body region;
fig. 9 is a schematic structural diagram of the device after the gate region and the source region are manufactured.
Detailed Description
The present invention will be further illustrated with reference to the accompanying drawings and specific examples, which are carried out on the premise of the technical solution of the present invention, and it should be understood that these examples are only for illustrating the present invention and are not intended to limit the scope of the present invention.
As shown in fig. 9, an embodiment of the present invention provides a superjunction device for improving EMI and reducing characteristic resistance, including a substrate 1 of a first conductivity type and an epitaxy disposed on an upper side of the substrate 1, where the epitaxy includes a plurality of first epitaxy 2 disposed on the upper side of the substrate 1 and a second epitaxy 3 disposed on the upper side of the first epitaxy 2, the first epitaxy 2 preferably includes 6 to 10 layers, a doped region 4 of the first conductivity type is doped on the upper side of each first epitaxy 2, and a plurality of doped regions 5 of the second conductivity type disposed at intervals are formed on the first epitaxy 2 and fabricated. The second conductive type doping regions 5 on the multilayer first epitaxy 2 are vertically arranged, a plurality of grooves 7 are formed in the second epitaxy 3 in an etching mode, each groove 7 is arranged on the upper side of one row of the second conductive type doping regions 5, second conductive type impurities are back filled in the grooves 7, second conductive type connecting columns 6 are connected between two longitudinally adjacent second conductive type doping regions 5 and between the grooves 7 and the second conductive type doping regions 5 on the lower sides of the grooves 7, and further the impurities in the grooves 7 are connected with the second conductive type doping regions 5 arranged longitudinally into a whole through the connecting columns 6. A field oxide layer 8 is grown on the epitaxial upper side of the termination region, the thickness of the field oxide layer 8 preferably being 8000 to 12000 angstroms. A gate oxide layer 9 is grown on the upper side of the second epitaxy 3 on two sides of the trench 7 in the active region, a doped polycrystal 10 is arranged on the upper side of the gate oxide layer 9 and the upper side of the inner end of the field oxide layer 8, and the thickness of the polycrystal is preferably 6000-8000 angstroms. A body region 11 of the second conductivity type is manufactured in the upper end of the trench 7 in the active region and the second epitaxy 3 between the active region and the terminal region, a well region 12 of the first conductivity type is arranged in the body region 11, a dielectric layer 13 is deposited on the upper sides of the polycrystal 10, the body region 11 and the field oxide layer 8, and the dielectric layer 13 can be a borophosphosilicate glass layer, and the thickness of the dielectric layer is preferably 10000 angstroms. A connecting hole 14 is arranged on the dielectric layer, a metal layer 15 is formed in the connecting hole 14 and on the upper side of the dielectric layer 13 in a sputtering mode, and the metal layer 15 is etched to form a gate region and a source region. The metal layer 15 may be an aluminum layer, preferably 4 μm thick.
The first epitaxy 2 of the embodiment of the invention is a high resistance epitaxy with a resistivity of preferably 20 to 40 Ω · cm and the second epitaxy typically has a resistivity of 3 to 7 Ω · cm. The thickness of the first epitaxy 2 located lowermost is preferably 12 to 15 μm, and the thickness of the remaining first epitaxy 2 is preferably 5 to 8 μm. The thickness of the second epitaxy is preferably 50 to 60 μm.
A passivation layer, which may be a silicon nitride layer, is deposited on the upper side of the metal layer 15, and the thickness of the passivation layer is preferably 7000-12000 angstroms, and then the opening regions of Gate and Source are formed by photolithography and etching.
It is also possible to provide a back gold layer on the underside of the substrate 1, which is first thinned to a residual thickness of 200 to 300 μm from the underside of the substrate 1 before the back gold layer is provided, and then to evaporate Ti-Ni-Ag (titanium-nickel-silver) in sequence on the underside of the substrate 1.
With reference to fig. 1 to 9, based on the above embodiments, it can be understood by those skilled in the art that the present invention also provides a method for manufacturing a superjunction device with improved EMI and reduced characteristic resistance, including:
as shown in fig. 1, a substrate 1 of a first conductivity type is provided, a first epitaxy 2 is first fabricated on the substrate 1, and a doped region 4 of the first conductivity type and a plurality of doped regions 5 of a second conductivity type arranged at intervals are formed on the upper side of the first epitaxy 2 by impurity implantation. The first conductivity type is N-type, and the second conductivity type is P-type. The substrate 1 may be doped with N-type (100) crystal orientation, arsenic or antimony, and typically has a resistivity of 0.001 to 0.005 Ω. The layer of first epitaxy 2 is a high-resistivity epitaxy with a resistivity of preferably 20 to 40 Ω · cm and the layer of first epitaxy 2 has a thickness of preferably 12 to 15 μm. The doped region 4 of the first conductivity type is formed by impurity implantation of the first conductivity type. The second conductive type doped region 5 may be formed by performing conventional steps such as glue coating, photolithography, second conductive type impurity implantation, and photoresist removal, or by etching a trench and backfilling the second conductive type impurity.
As shown in fig. 2, a layer of first epitaxy 2 is grown on the upper side of the first epitaxy 2, and then a first conductive type doping region 4 and a plurality of second conductive type doping regions 5 are formed on the upper side of the layer of first epitaxy 2 by impurity implantation, wherein the implantation energy of the first conductive type doping region 4 is 60Kev, the implantation dose is 1E12-4E12, the implantation energy of the second conductive type doping region 5 is 150Kev, and the implantation dose is 1E12-4E 12. This is repeated a plurality of times to obtain a plurality of layers of first epitaxy 2 having doped regions 4 of the first conductivity type and a plurality of spaced apart doped regions 5 of the second conductivity type. The doped regions 5 of the second conductivity type on the multilayer first epitaxy 2 are arranged in a vertical alignment. The thickness of the first epitaxy 2, except for the lowermost layer, is preferably 5 to 8 μm. This step is preferably repeated 4 to 8 times, and 6 to 10 layers of the first epitaxy 2 may be formed.
As shown in fig. 3, a layer of second epitaxy 3 is grown on the uppermost first epitaxy 2, and a plurality of trenches 7 are etched on the second epitaxy 3, each trench 7 is disposed on the upper side of a column of doping regions 5 of the second conductivity type, and the plurality of trenches 7 are backfilled with impurities of the second conductivity type. The thickness of the second epitaxy 3 is preferably 50 to 60 μm, and the resistivity of the second epitaxy 3 is 3 to 7 Ω · cm.
As shown in fig. 4, a connection post 6 of the second conductivity type is implanted in the multi-layer first epitaxy 2 and the second epitaxy 3, and the connection post 6 is connected between two longitudinally adjacent doped regions 5 of the second conductivity type and between the trench 7 and the doped region 5 of the second conductivity type on the lower side thereof. Specifically, TEOS deposition and SIN deposition are carried out on the upper side of the second epitaxy 3, the TEOS deposition thickness is 1000-3000 angstroms, the SIN deposition thickness is 1000-2000 angstroms, then pilar injection operation is carried out, the trap pushing temperature is 1100 ℃, 100-200 min, and finally SIN etching and TEOS etching are carried out. It should be noted that after passing through the drive well, the doped region 4 of the first conductivity type is diffused so that the resistivity of the first epitaxy 2 is reduced to be substantially the same as the resistivity of the second epitaxy 3.
As shown in fig. 5, the field oxide layer 8 is grown on the upper side of the second epitaxy 2 and the field oxide layer 8 in the active region is etched away. Specifically, a photoresist is coated on the upper side of the field oxide layer 8, then the active region is exposed, the photoresist in the active region is removed, then the field oxide layer 8 in the active region is etched away, and finally the photoresist in the terminal region is removed.
As shown in fig. 6, a gate oxide layer 9 is grown on the upper side of the second epitaxy layer 3 in the active region, a poly 10 is deposited on the upper side of the gate oxide layer 9 and the field oxide layer 8, and then the poly 10 is doped and etched. The thickness of the gate oxide layer 9 is typically 700-1200 angstroms, and the thickness of the deposited poly 10 is preferably 6000-8000 angstroms. After etching the poly 10, the poly 10 is only remained on the upper side of the gate oxide layer 9 and the upper side of the inner end of the field oxide layer 8 at two sides of the trench 7 in the active region.
As shown in fig. 7 and 8, a body region 11 of the second conductivity type is formed in the upper end of the trench 7 in the active region and in the second extension 3 between the active region and the termination region, and a well region 12 of the first conductivity type is formed in the body region 11. The body region 11 is formed by impurity implantation and annealing, and the implantation amount: 4E13-6E13, implant energy: 60Kev-120Kev, implant element: and boron. Then BODY annealing, wherein the annealing temperature is as follows: 1100 ℃, time: 30-180 minutes. Well region 12 impurity implantation and drive-well operation formation, implantation dose: 5E15-1E16, implant energy: 60Kev-120Kev, implant element: arsenic. The temperature of the well: 950 ℃, time: for 30 minutes.
As shown in fig. 9, a dielectric layer 13 is deposited on the upper side of the poly 10, the body region 11 and the field oxide layer 8, and a connection hole 14 is etched on the dielectric layer. Dielectric layer 13 is preferably borophosphosilicate glass, preferably 10000 angstroms thick.
A metal layer 15 is formed in the connecting hole 14 and on the upper side of the dielectric layer 13 in a sputtering mode, and the metal layer 15 is etched to form a gate region and a source region.
A passivation layer, which may be a silicon nitride layer, is deposited on the upper side of the metal layer 15, and the thickness of the passivation layer is preferably 7000-12000 angstroms, and then the opening regions of Gate and Source are formed by photolithography and etching.
It is also possible to provide a back gold layer on the underside of the substrate 1, which is first thinned to a residual thickness of 200 to 300 μm from the underside of the substrate 1 before the back gold layer is provided, and then to evaporate Ti-Ni-Ag (titanium-nickel-silver) in sequence on the underside of the substrate 1.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that other parts not specifically described are within the prior art or common general knowledge to those of ordinary skill in the art. Without departing from the principle of the invention, several improvements and modifications can be made, and these improvements and modifications should also be construed as the scope of the invention.

Claims (10)

1. A super junction device for improving EMI and reducing characteristic resistance is characterized by comprising a substrate of a first conduction type and an epitaxy arranged on the upper side of the substrate, wherein the epitaxy comprises a plurality of layers of first epitaxy arranged on the upper side of the substrate and a plurality of layers of second epitaxy arranged on the upper side of the first epitaxy, the upper side of each layer of the first epitaxy is doped with a doping area of the first conduction type, a plurality of doping areas of the second conduction type are formed at intervals, the doping areas of the second conduction type on the plurality of layers of the first epitaxy are arranged vertically, a plurality of grooves are formed on the second epitaxy in an etching mode, each groove is arranged on the upper side of one column of doping areas of the second conduction type, impurities of the second conduction type are filled back in the grooves, and second conduction type connecting columns are connected between two longitudinally adjacent doping areas of the second conduction type and between the groove and the doping area of the second conduction type on the lower side of the groove, the epitaxial upside on terminal area is long to have a field oxygen layer, in the active area the epitaxial upside of the second of slot both sides is long to have a gate oxide, gate oxide upside and field oxygen layer's inner upside are equipped with the polycrystal of doping, in the active area the upper end of slot and the second between active area and the terminal area are epitaxial the preparation in the district that has the second conductive type, be equipped with the well region of first conductive type in the district, the upside deposit on polycrystal, district and field oxygen layer has the dielectric layer, be equipped with the connecting hole on the dielectric layer, the upside sputtering of dielectric layer in the connecting hole and in the dielectric layer is formed with the metal layer, the metal layer sculpture forms grid region and source region.
2. The superjunction device of claim 1, wherein the first epitaxy has a resistivity of 20 to 40 Ω -cm and the second epitaxy has a resistivity of 3 to 7 Ω -cm.
3. The superjunction device of claim 1, wherein the thickness of the first lowermost epitaxy is 12 to 15 μm, and the thickness of the remaining first epitaxy is 5 to 8 μm.
4. The superjunction device of claim 1, wherein the first epitaxy comprises 6 to 10 layers.
5. The EMI improved and reduced super junction device of claim 1 wherein the thickness of said second extension is 50 to 60 μm.
6. A method of manufacturing a superjunction device with improved EMI and reduced characteristic resistance as claimed in claim 1, comprising:
providing a substrate of a first conductive type, firstly manufacturing a layer of first epitaxy on the substrate, and forming a doped region of the first conductive type and a plurality of doped regions of a second conductive type arranged at intervals on the upper side of the first epitaxy through impurity injection;
growing a layer of first epitaxy on the upper side of the first epitaxy, then forming a first conductive type doping region and a plurality of second conductive type doping regions arranged at intervals on the upper side of the layer of first epitaxy through impurity injection, and repeating the steps for a plurality of times, wherein the second conductive type doping regions on the plurality of layers of first epitaxy are vertically arranged;
growing a layer of second epitaxy on the uppermost layer of the first epitaxy, etching the second epitaxy to form a plurality of grooves, wherein each groove is arranged on the upper side of the row of doping regions of the second conductivity type, and backfilling impurities of the second conductivity type into the plurality of grooves;
connecting columns of the second conductivity type are formed in the multi-layer first epitaxy and the second epitaxy in an implantation mode, and the connecting columns are respectively connected between two longitudinally adjacent doping regions of the second conductivity type and between the groove and the doping region of the second conductivity type on the lower side of the groove;
growing a field oxide layer on the second epitaxy, and etching and removing the field oxide layer in the active region;
and growing a gate oxide layer on the upper side of the second epitaxy in the active region, depositing polycrystal on the upper sides of the gate oxide layer and the field oxide layer, and then doping and etching the polycrystal.
Manufacturing a body region of a second conduction type in the upper end of the groove in the active region and a second extension between the active region and the terminal region, and manufacturing a well region of a first conduction type in the body region;
depositing a dielectric layer on the upper sides of the polycrystal, the body region and the field oxide layer, and etching the dielectric layer to form a connecting hole;
and sputtering a metal layer in the connecting hole and on the upper side of the dielectric layer, and etching the metal layer to form a gate region and a source region.
7. The method of manufacturing a superjunction device with improved EMI and reduced characteristic resistance of claim 6, wherein the resistivity of the first epitaxy is 20 to 40 Ω -cm and the resistivity of the second epitaxy is 3 to 7 Ω -cm.
8. The method of manufacturing a superjunction device with improved EMI and reduced characteristic resistance according to claim 6, wherein the thickness of the first epitaxy at the lowermost side is 12 to 15 μm, and the thickness of the remaining first epitaxy is 5 to 8 μm.
9. The method of manufacturing a superjunction device with improved EMI and reduced characteristic resistance of claim 6, wherein the first epitaxy comprises 6 to 10 layers.
10. The method of manufacturing a superjunction device with improved EMI and reduced characteristic resistance according to claim 6, wherein the thickness of the second epitaxy is 50 to 60 μm.
CN202110046715.0A 2021-01-14 2021-01-14 Super junction device for improving EMI (electro-magnetic interference) and reducing characteristic resistance and manufacturing method thereof Pending CN112786684A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113488389A (en) * 2021-06-07 2021-10-08 西安电子科技大学 Trench gate double-layer super-junction VDMOSFET semiconductor device and preparation method thereof
CN114122115A (en) * 2022-01-28 2022-03-01 绍兴中芯集成电路制造股份有限公司 Super junction semiconductor device and forming method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113488389A (en) * 2021-06-07 2021-10-08 西安电子科技大学 Trench gate double-layer super-junction VDMOSFET semiconductor device and preparation method thereof
CN113488389B (en) * 2021-06-07 2022-11-11 西安电子科技大学 Trench gate double-layer super-junction VDMOSFET semiconductor device and preparation method thereof
CN114122115A (en) * 2022-01-28 2022-03-01 绍兴中芯集成电路制造股份有限公司 Super junction semiconductor device and forming method thereof
CN114122115B (en) * 2022-01-28 2022-04-29 绍兴中芯集成电路制造股份有限公司 Super junction semiconductor device and forming method thereof

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