CN111463281B - High-voltage super-junction DMOS structure integrating starting tube, sampling tube and resistor and preparation method thereof - Google Patents
High-voltage super-junction DMOS structure integrating starting tube, sampling tube and resistor and preparation method thereof Download PDFInfo
- Publication number
- CN111463281B CN111463281B CN202010235409.7A CN202010235409A CN111463281B CN 111463281 B CN111463281 B CN 111463281B CN 202010235409 A CN202010235409 A CN 202010235409A CN 111463281 B CN111463281 B CN 111463281B
- Authority
- CN
- China
- Prior art keywords
- mos tube
- tube
- region
- sampling
- implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000005070 sampling Methods 0.000 title claims abstract description 33
- 238000002360 preparation method Methods 0.000 title claims description 9
- 238000002347 injection Methods 0.000 claims abstract description 37
- 239000007924 injection Substances 0.000 claims abstract description 37
- 238000002955 isolation Methods 0.000 claims abstract description 22
- 238000002513 implantation Methods 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 30
- 238000001259 photo etching Methods 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 15
- 229910052796 boron Inorganic materials 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 9
- 238000005260 corrosion Methods 0.000 claims description 8
- 230000007797 corrosion Effects 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- FAWGZAFXDJGWBB-UHFFFAOYSA-N antimony(3+) Chemical compound [Sb+3] FAWGZAFXDJGWBB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 239000007943 implant Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a high-voltage super-junction DMOS structure integrating a starting tube, a sampling tube and a resistor. The grid electrode of the sampling MOS tube is connected with the grid electrode of the main MOS tube, and the grid electrode of the starting MOS tube is connected with the drain electrode of the starting MOS tube through a polycrystalline resistor; each MOS tube is alternately arranged through an N column and a P column to form a super junction structure; an isolation structure is arranged between two adjacent MOS tubes, and the top ends of the P columns are connected together through Ring injection in each isolation region, so that a pressure-resistant Ring is formed. The invention improves the integration level of the circuit, and reduces the starting loss and the current sampling loss in the circuit, thereby reducing the standby power consumption and improving the energy conversion efficiency.
Description
Technical Field
The invention belongs to the field of semiconductor devices, and particularly relates to a DMOS structure and a preparation method thereof.
Background
Fig. 1 is a plan view of a common DMOS product, in which a start-up transistor, a sampling transistor, and a resistor structure are not provided in the structure of the common DMOS product, and in practical application, a discrete current sampling resistor and a DMOS transistor are required to implement sampling and asynchronous starting, so that the circuit conversion efficiency is low, the whole area of the circuit is large, and the standby loss is high.
Disclosure of Invention
In order to solve the technical problems mentioned in the background art, the invention provides a high-voltage super-junction DMOS structure integrating a starting tube, a sampling tube and a resistor and a preparation method thereof.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
the high-voltage super-junction DMOS structure comprises a main MOS tube, a starting MOS tube, a sampling MOS tube and a polycrystalline resistor, wherein the drain electrodes of the main MOS tube, the starting MOS tube and the sampling MOS tube are connected together; each MOS tube is alternately arranged through an N column and a P column to form a super junction structure; an isolation structure is arranged between two adjacent MOS tubes; the isolation structure is characterized in that two ends of a cell region P column of each MOS tube are respectively connected with the vertex angle of an isosceles triangle injection window, and a distance d exists between the isosceles triangle injection windows connected with the cell region P columns of two adjacent MOS tubes, so that an isolation region is formed between the two adjacent MOS tubes; in each isolation region, the top ends of the P columns are connected together through Ring injection, so that a pressure-resistant Ring is formed.
Further, the vertex angle of the isosceles triangle injection window is less than 30 degrees; the width of each side of the isosceles triangle injection window is smaller than that of the P column; the distance d is equal to the distance between adjacent P pillars.
The preparation method for the high-voltage super junction DMOS structure comprises the following steps:
(1) preparing a substrate: the substrate adopts an N-type <100> crystal orientation, arsenic element or antimony element is doped, a layer of epitaxial material with the thickness of 5-10 um is grown on the substrate in advance, and the resistivity of the epitaxial material is smaller than that of the epitaxial material grown subsequently;
(2) forming a P column: continuously growing a layer of epitaxial material with the thickness of 3-15um on the epitaxial material grown in the step (1), and forming a super junction structure with alternately arranged N columns and P columns through photoetching and N times of injection with different energies to obtain a cell area of the main MOS tube, the starting MOS tube and the sampling MOS tube; wherein n is more than or equal to 1;
(3) forming Ring and isolation region: continuously growing a layer of epitaxial material with the thickness of 2-3um on the epitaxial material grown in the step (2), wherein the resistivity of the epitaxial material is the same as that of the N column; exposing the pressure Ring injection region and the isolation region between the MOS tubes by Ring photoetching, and then Ring injecting with the energy of 110 Kev-180 Kev and the injected element of boron with the injection dose of 5E 12-2E 13;
(4) a P column and a Ring Ring of the drive well are used for growing a field oxide layer;
(5) opening the active region of each MOS tube by photoetching, and removing an oxide layer on the surface of the active region by wet etching;
(6) growing a gate oxide layer on the field oxide layer and the active region of each MOS tube, and depositing polycrystal on the gate oxide layer;
(7) forming a polycrystalline resistor through polycrystalline injection, photoetching and corrosion, wherein a polycrystalline doping process is not adopted in the step;
(8) in the area without polycrystal and field oxygen barrier, Pbody implantation and annealing are carried out;
(9) forming a source region of each MOS tube in the Pbody region through NSD photoetching, injection and well pushing;
(10) depositing a medium on the field oxide layer, the polycrystal and each MOS tube source region, and etching a contact hole on the medium;
(11) forming a gate region and a source region of each MOS tube on the medium and in the contact hole by aluminum sputtering, photoetching and corrosion;
(12) thinning the back of the substrate and evaporating Ti-Ni-Ag alloy on the back of the substrate.
Further, the resistivity of the epitaxial material grown in the step (1) is 0.4-2 omega/cm; and (3) the resistivity of the epitaxial material grown in the step (2) is 0.5-5 omega/cm.
Further, in the step (2), the implanted element is boron element, and the implantation dosage is 4E 12-2E 13; in the step (3), the Ring implantation energy is 110 Kev-180 Kev, the implanted element is boron element, and the implantation dose is 5E 12-2E 13; in the step (7), the energy of polycrystalline implantation is 20Kev-40Kev, the element of polycrystalline implantation is boron element, and the dose of polycrystalline implantation is 1E 14-1E 15; in the step (8), the Pbody implantation energy is 60 KeV-120 KeV, the implanted element is boron element, and the implantation dose is determined according to the threshold voltage; in the step (9), the energy of NSD implantation is 120Kev-160Kev, the implanted element is phosphorus, and the implantation dosage is 5E 15-1E 16.
Further, in the step (4), the temperature of the drive-in trap is 1150 ℃, the time of the drive-in trap is 60-300 minutes, and the thickness of the grown field oxide layer is 12000-18000 angstroms; in the step (6), the thickness of the grown gate oxide layer is 700-1200 angstroms, the growth temperature is 900-1000 ℃, and the thickness of the deposited polycrystal is 6000-8000 angstroms; in step (9), the NSD trap temperature was 950 ℃ and the trap time was 25 minutes.
Furthermore, the strip width of the polycrystalline resistor is 0.8-2.5 um, and the resistance value of the polycrystalline resistor is 8-50M omega; in step (11), the thickness of the sputtered aluminum is 4 um.
Further, in step (10), the dielectric is BPSG, and the thickness of the deposited dielectric is 11000 angstroms.
Further, between the step (11) and the step (12), opening areas of the grid electrode and the source electrode of the main MOS tube and the start MOS tube and opening areas of the source electrode of the sampling MOS tube are formed through passivation layer deposition, photoetching and corrosion.
Further, the passivation layer is silicon nitride, and the thickness of the deposited passivation layer is 7000-12000 angstroms.
Adopt the beneficial effect that above-mentioned technical scheme brought:
(1) the invention integrates the sampling and starting functions with the power DMOS, improves the integration level of the circuit, and can reduce the starting loss and the current sampling loss in the circuit, thereby reducing the standby power consumption and improving the energy conversion efficiency;
(2) according to the invention, by utilizing the excellent conductive characteristic of the high-voltage super-junction DMOS, compared with the common DMOS, the area of a chip is reduced by more than 70%, and the cost of the chip is greatly reduced;
(3) the invention integrates the starting tube, the sampling tube and the resistor, is compatible with the super junction DMOS process, and reduces the cost.
Drawings
Fig. 1 is a plan view of a conventional DMOS product;
fig. 2 is a DMOS circuit connection diagram of the present invention;
FIG. 3 is a schematic view of an isolation structure of the present invention;
FIG. 4 is a schematic diagram of P column injection in the preparation method of the present invention;
FIG. 5 is a schematic diagram of Ring injection in the preparation method of the present invention;
FIG. 6 is a schematic diagram of a field oxide layer grown in the method of the present invention;
FIG. 7 is a schematic view of a deposited polycrystalline form in the production method of the present invention;
FIG. 8 is a schematic view of a Pbody injection well in the fabrication method of the present invention;
FIG. 9 is a schematic diagram of an NSD injection well in the fabrication method of the present invention;
FIG. 10 is a schematic view of deposition of a dielectric and etching of holes in a fabrication method of the present invention;
FIG. 11 is a schematic diagram of aluminum sputter etching in the manufacturing method of the present invention.
Detailed Description
The technical scheme of the invention is explained in detail in the following with the accompanying drawings.
The invention designs a high-voltage super-junction DMOS structure integrating a starting tube, a sampling tube and a resistor, which comprises a main MOS tube, the starting MOS tube, the sampling MOS tube and a polycrystalline resistor, wherein as shown in figure 2, the drain electrodes of the main MOS tube, the starting MOS tube and the sampling MOS tube are connected together, the grid electrode of the sampling MOS tube is connected with the grid electrode of the main MOS tube, and the grid electrode of the starting MOS tube is connected with the drain electrode of the starting MOS tube through the polycrystalline resistor.
The MOS tubes are alternately arranged through N columns and P columns to form a super junction structure. An isolation structure is arranged between two adjacent MOS tubes; the isolation structure is characterized in that two ends of a cell region P column of each MOS tube are respectively connected with the vertex angle of an isosceles triangle injection window, and a distance d exists between the isosceles triangle injection windows connected with the cell region P columns of two adjacent MOS tubes, so that an isolation region is formed between the two adjacent MOS tubes; in each isolation region, the top ends of the P columns are connected together through Ring injection, so that a pressure-resistant Ring is formed.
In this embodiment, preferably, the vertex angle of the isosceles triangle injection window is less than 30 °; the width of each side of the isosceles triangle injection window is smaller than that of the P column; the distance d is equal to the distance between adjacent P pillars.
The invention also provides a preparation method of the high-voltage super-junction DMOS structure for integrating the starting tube, the sampling tube and the resistor, which comprises the following steps:
step 1, preparing a substrate: the substrate adopts an N-type <100> crystal orientation, arsenic element or antimony element is doped, a layer of epitaxial material with the thickness of 5-10 um is grown on the substrate in advance, and the resistivity of the epitaxial material is lower than that of the epitaxial material grown subsequently. Preferably, the resistivity of the epitaxial material grown in this step is 0.4-2 Ω/cm. Through the step, the back diffusion of the doped elements of the substrate at high temperature can be effectively reduced, and the on-resistance is further reduced.
And 3, forming a Ring Ring and an isolation region: continuing to grow a layer of epitaxial material with the thickness of 2-3um on the epitaxial material grown in the step 2, wherein the resistivity of the epitaxial material is the same as that of the N column; exposing the pressure Ring injection region and the isolation region between the MOS tubes by Ring photoetching, and then Ring injecting with the energy of 110 Kev-180 Kev and the injected element of boron and the injection dosage of 5E 12-2E 13. Preferably, the Ring implantation energy is 110 Kev-180 Kev, the implanted element is boron element, and the implantation dose is 5E 12-2E 13. In the step, the tops of the P columns are connected in the terminal area to form a gradual voltage-withstanding structure, so that the voltage-withstanding efficiency of the terminal is improved. The isolation regions of the main MOS tube, the sampling tube and the starting tube are formed, so that the main MOS tube, the sampling tube and the starting tube are isolated from each other and can work independently. The corresponding structure of this step is shown in fig. 5.
And 4, pushing the P column and the Ring of the trap, and growing a field oxide layer. Preferably, the temperature of the drive-in trap is 1150 ℃, the time of the drive-in trap is 60-300 minutes, and the thickness of the grown field oxide layer is 12000-18000 angstroms. The corresponding structure of this step is shown in fig. 6.
And 5, opening the active region of each MOS tube by photoetching, and removing the oxide layer on the surface of the active region by wet etching.
And 6, growing a gate oxide layer on the field oxide layer and the active region of each MOS tube, and depositing polycrystal on the gate oxide layer. Preferably, the thickness of the grown gate oxide layer is 700-1200 angstroms, the growth temperature is 900-1000 ℃, and the thickness of the deposited polycrystal is 6000-8000 angstroms. The corresponding structure of this step is shown in fig. 7.
And 7, forming the polycrystalline resistor through polycrystalline injection, photoetching and corrosion, wherein the polycrystalline doping process is not adopted in the step. Preferably, the energy of the polycrystalline implantation is 20Kev-40Kev, the element of the polycrystalline implantation is boron element, and the dose of the polycrystalline implantation is 1E 14-1E 15; the strip width of the polycrystalline resistor is 0.8-2.5 um, and the resistance value of the polycrystalline resistor is 8-50M omega.
And 8, carrying out Pbody implantation and annealing in the region without polycrystal and field oxygen barrier. Preferably, the Pbody implant has an energy of 60KeV to 120KeV, the implanted element is boron, and the dose of the implant is determined according to the threshold voltage, and is generally 1E13 to 8E 13. The corresponding structure in this step is shown in fig. 8.
And 9, forming a source region of each MOS tube in the Pbody region through NSD photoetching, injection and well pushing. Preferably, the energy of NSD implantation is 120Kev-160Kev, the implanted element is phosphorus, and the implantation dose is 5E 15-1E 16; the NSD trap temperature was 950 ℃ and the trap time was 25 minutes. The structure corresponding to this step is shown in fig. 9.
And step 10, depositing a medium on the field oxide layer, the polycrystal and each MOS tube source region, and etching a contact hole on the medium. Preferably, the dielectric is BPSG (borophosphosilicate glass) and the thickness of the deposited dielectric is 11000 angstroms. The corresponding structure of this step is shown in fig. 10.
And 11, forming a gate region and a source region of each MOS tube on the medium and in the contact hole through aluminum sputtering, photoetching and corrosion. Preferably, the sputtered aluminum is 4um thick. The corresponding structure in this step is shown in fig. 11.
And step 12, forming an opening area of the grid electrode and the source electrode of the main MOS tube and the starting MOS tube and an opening area of the source electrode of the sampling MOS tube through passivation layer deposition, photoetching and corrosion. Preferably, the passivation layer is silicon nitride and the thickness of the deposited passivation layer is 7000-12000 angstroms. The step is an optional operation item, and can be operated or not operated.
And step 13, thinning the back surface of the substrate, and evaporating the Ti-Ni-Ag alloy on the back surface of the substrate.
The embodiments are only for illustrating the technical idea of the present invention, and the technical idea of the present invention is not limited thereto, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the scope of the present invention.
Claims (10)
1. High pressure of integrated start pipe, sampling pipe and resistance surpasses knot DMOS structure, including main MOS pipe, its characterized in that: the sampling MOS tube is characterized by further comprising a starting MOS tube, a sampling MOS tube and a polycrystalline resistor, wherein the drains of the main MOS tube, the starting MOS tube and the sampling MOS tube are connected together, the grid of the sampling MOS tube is connected with the grid of the main MOS tube, and the grid of the starting MOS tube is connected with the drain of the starting MOS tube through the polycrystalline resistor; each MOS tube is alternately arranged through an N column and a P column to form a super junction structure; an isolation structure is arranged between two adjacent MOS tubes; the isolation structure is characterized in that two ends of a cell region P column of each MOS tube are respectively connected with the vertex angle of an isosceles triangle injection window, and a distance d exists between the isosceles triangle injection windows connected with the cell region P columns of two adjacent MOS tubes, so that an isolation region is formed between the two adjacent MOS tubes; in each isolation region, the top ends of the P columns are connected together through Ring injection, so that a pressure-resistant Ring is formed.
2. The integrated starting tube, sampling tube and resistor high-voltage super junction DMOS structure of claim 1 wherein: the vertex angle of the isosceles triangle injection window is less than 30 degrees; the width of each side of the isosceles triangle injection window is smaller than that of the P column; the distance d is equal to the distance between adjacent P pillars.
3. The preparation method of the high-voltage super junction DMOS structure according to claim 1, comprising the steps of:
(1) preparing a substrate: the substrate adopts an N-type <100> crystal orientation, arsenic element or antimony element is doped, a layer of epitaxial material with the thickness of 5-10 um is grown on the substrate in advance, and the resistivity of the epitaxial material is lower than that of the epitaxial material grown subsequently;
(2) forming a P column: continuously growing a layer of epitaxial material with the thickness of 3-15um on the epitaxial material grown in the step (1), and forming a super junction structure with alternately arranged N columns and P columns through photoetching and N times of injection with different energies to obtain a cell area of the main MOS tube, the starting MOS tube and the sampling MOS tube; wherein n is more than or equal to 1;
(3) forming Ring and isolation region: continuously growing a layer of epitaxial material with the thickness of 2-3um on the epitaxial material grown in the step (2), wherein the resistivity of the epitaxial material is the same as that of the N column; exposing the pressure Ring injection region and the isolation region between the MOS tubes by Ring photoetching, and then Ring injecting with the energy of 110 Kev-180 Kev and the injected element of boron with the injection dose of 5E 12-2E 13;
(4) a P column and a Ring Ring of the drive well are used for growing a field oxide layer;
(5) opening the active region of each MOS tube by photoetching, and removing an oxide layer on the surface of the active region by wet etching;
(6) growing a gate oxide layer on the field oxide layer and the active region of each MOS tube, and depositing polycrystal on the gate oxide layer;
(7) forming a polycrystalline resistor through polycrystalline injection, photoetching and corrosion, wherein a polycrystalline doping process is not adopted in the step;
(8) in the area without polycrystal and field oxygen barrier, Pbody implantation and annealing are carried out;
(9) forming a source region of each MOS tube in the Pbody region through NSD photoetching, injection and well pushing;
(10) depositing a medium on the field oxide layer, the polycrystal and each MOS tube source region, and etching a contact hole on the medium;
(11) forming a gate region and a source region of each MOS tube on the medium and in the contact hole by aluminum sputtering, photoetching and corrosion;
(12) thinning the back of the substrate and evaporating Ti-Ni-Ag alloy on the back of the substrate.
4. The method according to claim 3, wherein the epitaxial material grown in the step (1) has a resistivity of 0.4 to 2 Ω/cm; and (3) the resistivity of the epitaxial material grown in the step (2) is 0.5-5 omega/cm.
5. The method according to claim 3, wherein in the step (2), the implanted element is boron, and the implantation dose is 4E 12-2E 13; in the step (3), the Ring implantation energy is 110 Kev-180 Kev, the implanted element is boron element, and the implantation dose is 5E 12-2E 13; in the step (7), the energy of polycrystalline implantation is 20Kev-40Kev, the element of polycrystalline implantation is boron element, and the dose of polycrystalline implantation is 1E 14-1E 15; in the step (8), the Pbody implantation energy is 60 KeV-120 KeV, the implanted element is boron element, and the implantation dose is determined according to the threshold voltage; in the step (9), the energy of NSD implantation is 120Kev-160Kev, the implanted element is phosphorus, and the implantation dosage is 5E 15-1E 16.
6. The method according to claim 3, wherein in the step (4), the temperature of the drive well is 1150 ℃, the time of the drive well is 60-300 minutes, and the thickness of the grown field oxide layer is 12000-18000 angstroms; in the step (6), the thickness of the grown gate oxide layer is 700-1200 angstroms, the growth temperature is 900-1000 ℃, and the thickness of the deposited polycrystal is 6000-8000 angstroms; in step (9), the NSD trap temperature was 950 ℃ and the trap time was 25 minutes.
7. The production method according to claim 3, wherein in the step (7), the strip width of the polycrystalline resistor is 0.8um to 2.5 um; in step (11), the thickness of the sputtered aluminum is 4 um.
8. The method of claim 3, wherein in step (10), the dielectric is BPSG and the thickness of the deposited dielectric is 11000 angstroms.
9. The manufacturing method according to claim 3, wherein between the step (11) and the step (12), an opening region of the gate and the source of the main MOS transistor and the start MOS transistor and an opening region of the source of the sampling MOS transistor are formed by passivation layer deposition, photolithography and etching.
10. The method as claimed in claim 9, wherein the passivation layer is silicon nitride and the thickness of the deposited passivation layer is 7000-12000 angstroms.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010235409.7A CN111463281B (en) | 2020-03-30 | 2020-03-30 | High-voltage super-junction DMOS structure integrating starting tube, sampling tube and resistor and preparation method thereof |
| PCT/CN2020/126045 WO2021196605A1 (en) | 2020-03-30 | 2020-11-03 | High-voltage super-junction dmos structure integrating starting tube, sampling tube and resistor and preparation method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010235409.7A CN111463281B (en) | 2020-03-30 | 2020-03-30 | High-voltage super-junction DMOS structure integrating starting tube, sampling tube and resistor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111463281A CN111463281A (en) | 2020-07-28 |
| CN111463281B true CN111463281B (en) | 2021-08-17 |
Family
ID=71684998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010235409.7A Active CN111463281B (en) | 2020-03-30 | 2020-03-30 | High-voltage super-junction DMOS structure integrating starting tube, sampling tube and resistor and preparation method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN111463281B (en) |
| WO (1) | WO2021196605A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111463281B (en) * | 2020-03-30 | 2021-08-17 | 南京华瑞微集成电路有限公司 | High-voltage super-junction DMOS structure integrating starting tube, sampling tube and resistor and preparation method thereof |
| CN113241371A (en) * | 2021-05-17 | 2021-08-10 | 滁州华瑞微电子科技有限公司 | Intelligent super-junction MOS with ultrahigh isolation voltage and manufacturing method thereof |
| CN113782584B (en) * | 2021-08-05 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | Superjunction device |
| CN114093866B (en) * | 2021-11-19 | 2023-03-14 | 陕西亚成微电子股份有限公司 | MOSFET structure of integrated starting device and manufacturing method |
| CN114023702B (en) * | 2022-01-06 | 2022-03-25 | 南京华瑞微集成电路有限公司 | Manufacturing method of intelligent power MOS (Metal oxide semiconductor) transistor for solving resistance nonlinearity |
| CN114068496B (en) * | 2022-01-17 | 2022-03-18 | 深圳市威兆半导体有限公司 | Integrated SGT-MOSFET device for voltage sampling |
| CN114496994B (en) * | 2022-04-07 | 2022-07-01 | 江苏长晶科技股份有限公司 | Super junction device integrating current sampling function |
| CN118280960B (en) * | 2024-06-03 | 2024-09-13 | 无锡祥瑞微电子科技有限公司 | Multi-module integrated circuit chip and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646708A (en) * | 2011-02-17 | 2012-08-22 | 富士电机株式会社 | Super-junction semiconductor device |
| CN104157689A (en) * | 2014-08-14 | 2014-11-19 | 西安芯派电子科技有限公司 | Semiconductor structure with self-isolation |
| JP2018026450A (en) * | 2016-08-10 | 2018-02-15 | 富士電機株式会社 | Semiconductor device |
| CN109888018A (en) * | 2019-04-03 | 2019-06-14 | 南京华瑞微集成电路有限公司 | The DMOS and its manufacturing method of a kind of integrated starting pipe, sampling pipe and resistance |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4450247B2 (en) * | 2007-07-13 | 2010-04-14 | 株式会社デンソー | Semiconductor device |
| KR101932776B1 (en) * | 2013-09-17 | 2018-12-27 | 매그나칩 반도체 유한회사 | Super-junction semiconductor device |
| JP6228850B2 (en) * | 2014-01-10 | 2017-11-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP6324805B2 (en) * | 2014-05-19 | 2018-05-16 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| CN108598166B (en) * | 2018-04-27 | 2021-07-02 | 电子科技大学 | Depletion type enhanced integrated power device based on super junction self-isolation and manufacturing method |
| CN111463281B (en) * | 2020-03-30 | 2021-08-17 | 南京华瑞微集成电路有限公司 | High-voltage super-junction DMOS structure integrating starting tube, sampling tube and resistor and preparation method thereof |
-
2020
- 2020-03-30 CN CN202010235409.7A patent/CN111463281B/en active Active
- 2020-11-03 WO PCT/CN2020/126045 patent/WO2021196605A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646708A (en) * | 2011-02-17 | 2012-08-22 | 富士电机株式会社 | Super-junction semiconductor device |
| CN104157689A (en) * | 2014-08-14 | 2014-11-19 | 西安芯派电子科技有限公司 | Semiconductor structure with self-isolation |
| JP2018026450A (en) * | 2016-08-10 | 2018-02-15 | 富士電機株式会社 | Semiconductor device |
| CN109888018A (en) * | 2019-04-03 | 2019-06-14 | 南京华瑞微集成电路有限公司 | The DMOS and its manufacturing method of a kind of integrated starting pipe, sampling pipe and resistance |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021196605A1 (en) | 2021-10-07 |
| CN111463281A (en) | 2020-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111463281B (en) | High-voltage super-junction DMOS structure integrating starting tube, sampling tube and resistor and preparation method thereof | |
| CN101452967B (en) | Schottky barrier diode device and manufacturing method thereof | |
| CN111463283B (en) | DMOS structure integrating starting tube, sampling tube and diode and preparation method thereof | |
| CN100590850C (en) | Method for manufacturing fully self-aligned strip-shaped grid power vertical double-diffusion field effect transistor | |
| CN109888018A (en) | The DMOS and its manufacturing method of a kind of integrated starting pipe, sampling pipe and resistance | |
| CN101043053B (en) | Power semiconductor device having improved performance and method | |
| CN111430453B (en) | RC-IGBT chip with good reverse recovery characteristic and manufacturing method thereof | |
| CN111211168B (en) | RC-IGBT chip and manufacturing method thereof | |
| CN211295110U (en) | DMOS with optimized electrical characteristics | |
| CN114975602A (en) | High-reliability IGBT chip and manufacturing method thereof | |
| CN109524472B (en) | Novel power MOSFET device and preparation method thereof | |
| CN113555354B (en) | SBD integrated trench terminal structure and preparation method thereof | |
| CN106876449A (en) | A kind of trench metal-oxide semiconductor and preparation method thereof | |
| CN103915334B (en) | The manufacture method of double level polysilicon bipolar transistor | |
| CN110429134B (en) | IGBT device with asymmetric primitive cells and preparation method | |
| CN107425068A (en) | A kind of carborundum TrenchMOS devices and preparation method thereof | |
| CN103779415A (en) | Planar type power MOS device and manufacturing method thereof | |
| CN112786684A (en) | Super junction device for improving EMI (electro-magnetic interference) and reducing characteristic resistance and manufacturing method thereof | |
| CN103337523B (en) | A kind of valley gutter Superpotential barrier rectification device and manufacture method thereof | |
| CN113314592B (en) | SBR (styrene butadiene rubber) -integrated low-loss high-voltage super junction device and preparation method thereof | |
| CN111223915A (en) | Multi-time epitaxial super junction device structure and manufacturing method thereof | |
| CN111463282B (en) | Low-voltage super-junction DMOS structure integrating starting tube and sampling tube and preparation method | |
| CN206134689U (en) | Low pressure trench gate DMOS device of high integration | |
| CN115332330A (en) | IGBT device with reverse conduction characteristic and preparation method thereof | |
| CN212303676U (en) | Deep trench MOS device for improving EMI |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |