CN100590850C - Method for fabricating full-self-aligned stripe shaped grating power perpendicular double diffusion field effect transistor - Google Patents
Method for fabricating full-self-aligned stripe shaped grating power perpendicular double diffusion field effect transistor Download PDFInfo
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- CN100590850C CN100590850C CN200710122480A CN200710122480A CN100590850C CN 100590850 C CN100590850 C CN 100590850C CN 200710122480 A CN200710122480 A CN 200710122480A CN 200710122480 A CN200710122480 A CN 200710122480A CN 100590850 C CN100590850 C CN 100590850C
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000009792 diffusion process Methods 0.000 title claims description 25
- 230000005669 field effect Effects 0.000 title claims description 21
- 238000005530 etching Methods 0.000 claims abstract description 36
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 33
- 239000010941 cobalt Substances 0.000 claims abstract description 33
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 33
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052796 boron Inorganic materials 0.000 claims abstract description 24
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 24
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 12
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000011521 glass Substances 0.000 claims abstract description 8
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 238000004544 sputter deposition Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 229920005591 polysilicon Polymers 0.000 claims description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 28
- 239000010703 silicon Substances 0.000 claims description 28
- 238000001259 photo etching Methods 0.000 claims description 21
- 230000002146 bilateral effect Effects 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 8
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 210000004483 pasc Anatomy 0.000 claims description 4
- -1 boron ion Chemical class 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 238000010992 reflux Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 13
- 238000001459 lithography Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract 5
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 15
- 230000009286 beneficial effect Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
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Abstract
The invention relates to the technical field of semiconductor device and integrated circuit fabrication technologies and discloses a method for preparing a DMOS power transistor with a fully self aligned strip-type gate. The method comprises: A. epitaxial growth is carried out on a substrate, and a field area is oxidized thereafter, thereby forming a field oxide layer; B. the field oxide layer inactive area is etched, a gate region is oxidized, then, amorphous silicon is deposited, and the deposited amorphous silicon is doped thereafter; C. lithography, etching and boron injection are carriedout on the amorphous silicon after being doped, and the injected boron is pushed forward under high temperature, thereby forming a P-type well region; D. the amorphous silicon is injected with arsenic to form a shallow source region, and then a side wall is formed by deposition and anti-etching; E. boron is injected into the amorphous silicon, a cobalt film is deposited, and then cobalt silicideis formed, and P-type well contact is formed by making use of the cobalt silicide; F. boron-phosphorosilicate glass is deposited, and pulling holes are formed by lithography and etching; G. metal is deposited by sputtering, and lithography and etching are carried out thereafter. The invention simplifies the fabrication process, reduces the fabrication cost and improves the operating frequency of the DMOS power transistor.
Description
Technical field
The present invention relates to semiconductor device and field of IC technique, relate in particular to a kind of making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor (VerticalDouble-diffusion MOSFET, method DMOS).
Background technology
Power DMOS transistor has been widely used in the various electronic equipments.Power DMOS transistor has characteristics such as switching speed is fast, input impedance is high, driving power consumption is little, frequency characteristic is good, mutual conductance highly linear, and has negative temperature coefficient, does not have the second breakdown problem of bipolar power, and the safety operation area is big.Therefore, no matter be switch application, or linear applications, the DMOS transistor all is desirable power device.
In traditional power DMOS transistor fabrication technology, be alignment point, be derived to aim at by P-trap and N+ and inject, realize the unified channel length in the entire chip with the polysilicon border.But contact with P-trap and N+ source in order to form good metal, usually also need two lithography mask versions (P-trap contact injecting mask version, N+ source injecting mask version) in addition, need 7～9 masks altogether, be unfavorable for reducing of chip area, complex technical process, the chip cost height; While, as gate interconnection, series resistance was big, the raising of restraint of labour frequency with polysilicon.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide a kind of method of making the fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor, to simplify manufacture craft, reduces cost of manufacture, improves the transistorized operating frequency of power DMOS.
(2) technical scheme
For achieving the above object, the invention provides a kind of method of making the fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor, this method comprises:
A, on substrate growing epitaxial, carry out the place oxidation then, form field oxide;
B, be etched with the field oxide in source region, carry out gate oxidation, the deposit polysilicon mixes to the polysilicon of deposit;
C, the whole silicon wafer after mixing is carried out photoetching, etching, boron injects, and high temperature advances and forms the P-well region;
D, whole silicon wafer is carried out arsenic inject to form shallow source region, then deposit and anti-carve the formation side wall;
E, whole silicon wafer is carried out boron inject, and deposit cobalt film, form the silicide of cobalt, utilize the silicide of cobalt to form the contact of P-trap;
F, carry out the boron-phosphorosilicate glass deposit, photoetching and etching fairlead;
G, metal sputtering also carry out photoetching and etching.
In the such scheme, described steps A comprises: on n+ type Si substrate, carry out n-type Si outer layer growth, carry out the place oxidation subsequently, form field oxide on n-type Si epitaxial loayer.
In the such scheme, described step B comprises: utilize an oxygen etching mask version to carry out the active area definition on field oxide, after defining active area, etch away the field oxide of active area, carry out gate oxidation then, and the deposit polysilicon, subsequently polysilicon is carried out a high temperature phosphorous diffusion of 1000 ℃, form low-resistivity n+ type polysilicon less than 10 Ω/sq.
In the such scheme, described step C comprises: utilize the etching polysilicon mask, the whole silicon wafer after etching is mixed is carried out the high temperature propelling that boron injects and carries out 1100 ℃ to the whole silicon wafer after the etching then, forms the P-well region.
In the such scheme, described in the step D whole silicon wafer being carried out arsenic and inject, is to be mask with the polysilicon, whole silicon wafer is carried out arsenic inject;
Deposit described in the step D also anti-carves the formation side wall, is deposit one deck tetraethoxysilane TEOS, and the TEOS of deposit is anti-carved the formation side wall.
In the such scheme, described step e comprises: the macro-energy and 2 * 10 of whole silicon wafer being carried out 90keV
15N/cm
2Heavy dose of boron inject, macro-energy makes the boron ion of injection can see through the N+ source region, mainly is distributed under the N+ source region, heavy dose makes the P+ district of P-well region formation high concentration, helps forming ohmic contact; Deposit cobalt film then, 670 ℃ of short annealings 5 seconds make cobalt and pasc reaction form the silicide of cobalt, carve and remove unreacted cobalt on the side wall, and 800 ℃ of short annealings are 10 seconds then, make silicide transfer the low resistance state of 16～18 μ Ω .cm to; Utilizing source region that the silicide of cobalt penetrates shallow source junction structure and following P-trap to form then contacts.
In the such scheme, described step F comprises: carry out the boron-phosphorosilicate glass deposit, and carry out 950 ℃ high temperature reflux, utilize the contact hole etching mask to carry out the fairlead photoetching and etch fairlead.
In the such scheme, described step G comprises: the splash-proofing sputtering metal layer, and utilize the etch masks version that metal level is carried out photoetching and corrosion, form the bar gate power vertical bilateral diffusion field-effect tranisistor of fully self aligned.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, the method for this making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor provided by the invention adopts stripe shape grid structural design, and stripe shape grid DMOS is a kind of DMOS of novel planar structure, and its polysilicon gate is strip and distributes.The strip grate structure can be in the unit active region area integrated bigger channel width, its source region contact hole area increases simultaneously, the grid area reduces, and has that conducting resistance is little, switching speed is high and characteristics such as good operating stability.
2, the method for this making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor provided by the invention, lay photoetching mask plate is few, need 4 lay photoetching mask plates altogether, comprising field oxygen etching mask version, etching polysilicon mask, contact hole etching mask, etch masks version, simplify manufacture craft greatly, reduced cost of manufacture.
3, the method for this making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor provided by the invention adopts the shallow source of N+ knot, contacts with following P-trap so that the silicide of back can penetrate the N+ source region.
4, the method for this making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor provided by the invention, adopt side wall technology, after the whole silicon wafer etching, deposit one deck tetraethoxysilane (TEOS) also anti-carves the formation side wall, injects so that carry out following P-trap contact.
5, the method for this making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor provided by the invention, the contact of P-trap is injected and is adopted macro-energy and heavy dose of boron to inject, the macro-energy purpose makes boron see through the N+ source region, mainly concentrate in the P-well region, heavy dose of purpose can make the silicide of back and P-trap form good Ohmic contact on the one hand, can reduce the reverse depletion widths of P-well region PN junction on the other hand, it is oppositely withstand voltage to improve device.This step has been saved the P-trap contact injecting mask version in traditional DMOS technology, is mask with the side wall, and the contact that forms the P-well region is injected.
6, the method for this making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor provided by the invention, the silicide of employing cobalt.Deposit cobalt film, 670 ℃ of short annealings 5 seconds make cobalt and pasc reaction generate silicide.Remove unreacted cobalt on the side wall quarter, 800 ℃ of short annealings are 10 seconds then, make silicide transfer low resistance state to.Because the N+ source region is a shallow source junction structure, the cobalt silicide in N+ source region penetrates the source region and contacts with following P-trap.In addition, the employing of cobalt makes the silicide form of polysilicon gate formation low-resistivity simultaneously, has reduced the series resistance of device grids, helps improving the switching speed and the operating frequency of device.
Description of drawings
Fig. 1 is the transistorized method flow diagram of making fully self aligned bar gate power DMOS provided by the invention;
Fig. 2 is a schematic diagram of making fully self aligned bar gate power DMOS transistor domain according to the embodiment of the invention;
Fig. 3 makes fully self aligned bar gate power DMOS transistor process flow figure according to the embodiment of the invention; Wherein,
The schematic diagram of Fig. 3-1 for carrying out outer layer growth and place oxidation according to the embodiment of the invention;
Fig. 3-2 is the schematic diagram according to embodiment of the invention definition active area etching field oxide gate oxidation and deposit polysilicon;
Fig. 3-3 is the schematic diagram according to embodiment of the invention etching whole silicon wafer and remanent field oxide layer;
Fig. 3-4 carries out the schematic diagram that boron injects formation P-well region for carving according to the embodiment of the invention;
Fig. 3-5 injects the schematic diagram that forms shallow junction N+ source region for according to the embodiment of the invention silicon chip being carried out arsenic;
Fig. 3-6 is according to embodiment of the invention deposit tetraethoxysilane (TEOS) and anti-carves the schematic diagram that forms side wall;
Fig. 3-7 is for carrying out the schematic diagram of the boron injection of macro-energy and heavy dose to whole silicon wafer according to the embodiment of the invention;
Fig. 3-8 is the schematic diagram that forms silicide according to embodiment of the invention deposit cobalt film;
Fig. 3-9 is the schematic diagram according to the deposit of embodiment of the invention boron-phosphorosilicate glass and photoetching and etching fairlead;
Fig. 3-10 is for according to embodiment of the invention metal sputtering and carry out the schematic diagram of photoetching and etching.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the transistorized method flow diagram of making fully self aligned bar gate power DMOS provided by the invention, and this method may further comprise the steps:
Step 101: growing epitaxial on substrate, carry out the place oxidation then, form field oxide;
Step 102: be etched with the field oxide in source region, carry out gate oxidation, the deposit polysilicon mixes to the polysilicon of deposit;
Step 103: the whole silicon wafer after mixing is carried out photoetching, etching, and boron injects, and high temperature advances and forms the P-well region;
Step 104: whole silicon wafer is carried out arsenic inject to form shallow source region, then deposit and anti-carve the formation side wall;
Step 105: whole silicon wafer is carried out boron inject, and deposit cobalt film, the silicide of formation cobalt utilizes the silicide of cobalt to form the contact of P-trap;
Step 106: carry out the boron-phosphorosilicate glass deposit, photoetching and etching fairlead;
Step 107: metal sputtering also carries out photoetching and etching.
Based on the transistorized method flow diagram of making fully self aligned bar gate power DMOS shown in Figure 1, below in conjunction with specific embodiment the present invention is made the transistorized method of fully self aligned bar gate power DMOS and further describe.
The transistorized method of this making fully self aligned bar gate power DMOS provided by the invention, technology is simple, and lay photoetching mask plate is few, has realized the fully self aligned that the P-trap injects, the N+ source is injected, the contact of P-trap is injected.In the present embodiment, adopt stripe shape grid structure, the domain pattern as shown in Figure 2, Fig. 2 be the schematic diagram according to embodiment of the invention making fully self aligned bar gate power DMOS transistor domain.
Below in conjunction with accompanying drawing 3, the transistorized preparation method of fully self aligned bar gate power DMOS is further specified:
Shown in Fig. 3-1, on n+ type Si substrate, carry out n-type Si outer layer growth, carry out the place oxidation subsequently, on n-type Si epitaxial loayer, form field oxide.
Shown in Fig. 3-2, utilize first mask (an oxygen etching mask version) on field oxide, to carry out the active area definition, after defining active area, etch away the field oxide of active area, carry out gate oxidation then, and the deposit polysilicon, subsequently polysilicon is carried out the phosphorous diffusion of 1000 ℃ of high temperature, form low-resistivity n+ type polysilicon less than 10 Ω/sq.
Shown in Fig. 3-3, utilize second mask (etching polysilicon mask), whole silicon wafer and remaining field oxide after etching is mixed.
As shown in Figure 3-4, the whole silicon wafer after the etching is carried out the high temperature propelling that boron injects and carries out 1100 ℃, form the P-well region.
Shown in Fig. 3-5, silicon chip is carried out arsenic inject.This step is carried out the arsenic injection, rather than the injection of the phosphorus in traditional DMOS technology, and purpose is to form shallow junction N+ source region, and this step has also been removed the N+ source mask in traditional DMOS technology simultaneously, is mask with the polysilicon only, and whole silicon wafer is injected.
Shown in Fig. 3-6, deposit one deck tetraethoxysilane (TEOS) also anti-carves the formation side wall, injects so that carry out following P-trap contact.
Shown in Fig. 3-7, whole silicon wafer is carried out the macro-energy and 2 * 10 of 90keV
15N/cm
2Heavy dose of boron inject, macro-energy makes the boron ion of injection can see through the N+ source region, mainly is distributed under the N+ source, heavy dose makes the P+ district of P-well region formation high concentration, helps forming good ohmic and contacts.
Shown in Fig. 3-8, deposit cobalt film, 670 ℃ of short annealings 5 seconds make cobalt and pasc reaction generate silicide.Remove unreacted cobalt on the side wall quarter, 800 ℃ of short annealings are 10 seconds then, make silicide transfer the low resistance state of 16～18 μ Ω .cm to.Because the N+ source region is a shallow source junction structure, the cobalt silicide in N+ source region penetrates the source region and contacts with following P-trap.
Shown in Fig. 3-9, the boron-phosphorosilicate glass deposit is also carried out 950 ℃ high temperature reflux, utilizes the 3rd mask (contact hole etching mask) to carry out the fairlead photoetching and etch fairlead.
Shown in Fig. 3-10, last splash-proofing sputtering metal layer, and utilize the 4th mask (etch masks version) that metal level is carried out photoetching and corrosion.
In the foregoing description, adopt stripe shape grid structural design, stripe shape grid DMOS is a kind of DMOS of novel planar grid structure, and its polysilicon gate is strip and distributes.P-trap, the contact of P-trap are injected, the N+ source is injected and all adopted self-registered technology, need not to increase lay photoetching mask plate, only need 4 masks, and technology is simple, and the chip manufacture cost reduces.The employing of silicide process simultaneously can effectively reduce the grid series resistance, improves the transistorized operating frequency of power DMOS.Having saved the N+ source mask in traditional DMOS technology, only is mask with the polysilicon; Carry out arsenic and inject, rather than the injection of the phosphorus in traditional DMOS technology, purpose is to form shallow junction N+ source region.Masterplate is injected in the P+ trap contact of having saved in traditional DMOS technology, is mask with the side wall.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1, a kind of method of making the fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor is characterized in that, this method comprises:
A, on substrate growing epitaxial, carry out the place oxidation then, form field oxide;
B, be etched with the field oxide in source region, carry out gate oxidation, the deposit polysilicon mixes to the polysilicon of deposit;
C, the whole silicon wafer after mixing is carried out photoetching, etching, boron injects, and high temperature advances and forms the P-well region;
D, whole silicon wafer is carried out arsenic inject to form shallow source region, then deposit and anti-carve the formation side wall;
E, whole silicon wafer is carried out boron inject, and deposit cobalt film, form the silicide of cobalt, utilize the silicide of cobalt to form the contact of P-trap;
F, carry out the boron-phosphorosilicate glass deposit, photoetching and etching fairlead;
G, metal sputtering also carry out photoetching and etching.
2, the method for making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor according to claim 1 is characterized in that, described steps A comprises:
On n+ type Si substrate, carry out n-type Si outer layer growth, carry out the place oxidation subsequently, on n-type Si epitaxial loayer, form field oxide.
3, the method for making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor according to claim 1 is characterized in that, described step B comprises:
Utilize an oxygen etching mask version on field oxide, to carry out the active area definition, after defining active area, etch away the field oxide of active area, carry out gate oxidation then, and deposit polysilicon, subsequently polysilicon is carried out a high temperature phosphorous diffusion of 1000 ℃, form low-resistivity n+ type polysilicon less than 10 Ω/sq.
4, the method for making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor according to claim 1 is characterized in that, described step C comprises:
Utilize the etching polysilicon mask, the whole silicon wafer after etching is mixed is carried out the high temperature propelling that boron injects and carries out 1100 ℃ to the whole silicon wafer after the etching then, forms the P-well region.
5, the method for making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor according to claim 1 is characterized in that, described in the step D whole silicon wafer is carried out arsenic and inject, and be to be mask with the polysilicon, whole silicon wafer is carried out arsenic inject;
Deposit described in the step D also anti-carves the formation side wall, is deposit one deck tetraethoxysilane TEOS, and the TEOS of deposit is anti-carved the formation side wall.
6, the method for making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor according to claim 1 is characterized in that, described step e comprises:
Whole silicon wafer is carried out the macro-energy and 2 * 10 of 90keV
15N/cm
2Heavy dose of boron inject, macro-energy makes the boron ion of injection can see through the N+ source region, mainly is distributed under the N+ source region, heavy dose makes the P+ district of P-well region formation high concentration, helps forming ohmic contact;
Deposit cobalt film then, 670 ℃ of short annealings 5 seconds make cobalt and pasc reaction form the silicide of cobalt, carve and remove unreacted cobalt on the side wall, and 800 ℃ of short annealings are 10 seconds then, make silicide transfer the low resistance state of 16～18 μ Ω .cm to;
Utilizing source region that the silicide of cobalt penetrates shallow source junction structure and following P-trap to form then contacts.
7, the method for making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor according to claim 1 is characterized in that, described step F comprises:
Carry out the boron-phosphorosilicate glass deposit, and carry out 950 ℃ high temperature reflux, utilize the contact hole etching mask to carry out the fairlead photoetching and etch fairlead.
8, the method for making fully self aligned bar gate power vertical bilateral diffusion field-effect tranisistor according to claim 1 is characterized in that, described step G comprises:
The splash-proofing sputtering metal layer utilizes the etch masks version that metal level is carried out photoetching and corrosion, forms the bar gate power vertical bilateral diffusion field-effect tranisistor of fully self aligned.
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| CN101866841B (en) * | 2009-04-16 | 2012-04-18 | 上海华虹Nec电子有限公司 | Method for forming self-aligned metal silicide at source/drain region of device |
| CN101719472B (en) * | 2009-11-18 | 2011-07-06 | 上海宏力半导体制造有限公司 | Method for preparing vertical double-diffusion MOS transistor |
| CN102074465B (en) * | 2009-11-24 | 2012-04-18 | 上海华虹Nec电子有限公司 | Double-well manufacturing process |
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| CN103050405B (en) * | 2011-10-14 | 2015-06-03 | 北大方正集团有限公司 | DMOS (double-diffused metal oxide semiconductor) device and manufacturing method thereof |
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| CN104810289A (en) * | 2014-01-27 | 2015-07-29 | 北大方正集团有限公司 | VDMOS (vertical double-diffused metal oxide semiconductor) transistor manufacturing method and VDMOS |
| CN105206527A (en) * | 2014-06-05 | 2015-12-30 | 北大方正集团有限公司 | VDMOS device and manufacturing method thereof |
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| US6965146B1 (en) * | 2004-11-29 | 2005-11-15 | Silicon-Based Technology Corp. | Self-aligned planar DMOS transistor structure and its manufacturing methods |
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