CN100590850C - Method for fabricating full-self-aligned stripe shaped grating power perpendicular double diffusion field effect transistor - Google Patents

Method for fabricating full-self-aligned stripe shaped grating power perpendicular double diffusion field effect transistor Download PDF

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CN100590850C
CN100590850C CN 200710122480 CN200710122480A CN100590850C CN 100590850 C CN100590850 C CN 100590850C CN 200710122480 CN200710122480 CN 200710122480 CN 200710122480 A CN200710122480 A CN 200710122480A CN 100590850 C CN100590850 C CN 100590850C
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CN101399227A (en )
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王立新
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中国科学院微电子研究所
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Abstract

The invention relates to the technical field of semiconductor device and integrated circuit fabrication technologies and discloses a method for preparing a DMOS power transistor with a fully self aligned strip-type gate. The method comprises: A. epitaxial growth is carried out on a substrate, and a field area is oxidized thereafter, thereby forming a field oxide layer; B. the field oxide layer inactive area is etched, a gate region is oxidized, then, amorphous silicon is deposited, and the deposited amorphous silicon is doped thereafter; C. lithography, etching and boron injection are carriedout on the amorphous silicon after being doped, and the injected boron is pushed forward under high temperature, thereby forming a P-type well region; D. the amorphous silicon is injected with arsenic to form a shallow source region, and then a side wall is formed by deposition and anti-etching; E. boron is injected into the amorphous silicon, a cobalt film is deposited, and then cobalt silicideis formed, and P-type well contact is formed by making use of the cobalt silicide; F. boron-phosphorosilicate glass is deposited, and pulling holes are formed by lithography and etching; G. metal is deposited by sputtering, and lithography and etching are carried out thereafter. The invention simplifies the fabrication process, reduces the fabrication cost and improves the operating frequency of the DMOS power transistor.

Description

全自对准条型栅功率垂直双扩散场效应晶体管的制作方法技术领域 Full power gate self-aligned vertical bar-type double diffusion method of a field effect transistor Field

本发明涉及半导体器件及集成电路制造工艺技术领域,尤其涉及一种 The present invention relates to semiconductor devices and integrated circuit fabrication technology, and more particularly, to a

制作全自对准条型栅功率垂直双扩散场效应晶体管(Vertical Double-diffiision MOSFET, DMOS)的方法。 The method of making the whole bar-type self-aligned vertical double diffused gate power FET (Vertical Double-diffiision MOSFET, DMOS) a.

背景技术 Background technique

功率DMOS晶体管已广泛应用于各种电子设备中。 Power DMOS transistor has been widely used in various electronic devices. 功率DMOS晶体管具有开关速度快、输入阻抗高、驱动功耗小、频率特性好、跨导高度线性等特点,而且具有负温度系数,没有双极功率管的二次击穿问题,安全工作区大。 DMOS power transistor having a high switching speed, high input impedance, low power consumption driving, frequency characteristics, transconductance highly linear characteristics, and has a negative temperature coefficient, no secondary problem bipolar power tube breakdown, a large safe operating area . 因此,不论是开关应用,还是线性应用,DMOS晶体管都是理想的功率器件。 Thus, whether the application is a switch or linear applications, over the DMOS transistor is a power device.

传统的功率DMOS晶体管制作工艺中,以多晶硅边界为对准点,通过P-阱以及N+源自对准注入,实现整个芯片内的统一沟道长度。 Traditional power DMOS transistor fabrication process, polysilicon boundary alignment points, the P- well and N + implanted from the alignment, the channel length unified throughout the chip. 但是为了形成良好的金属与P-阱及N+源接触,通常还另需两块光刻掩膜版(P-阱接触注入掩模版、N+源注入掩模版),共需要7〜9块掩模版,不利于芯片面积的减小,工艺过程复杂,芯片成本高;同时以多晶硅作为栅极互连, 串联电阻大,限制工作频率的提高。 However, in order to form P- well and good metal contact with the N + source, usually takes another two photolithographic mask (reticle P- well contact implant, N + source implant mask), a total block reticle 7~9 , is not conducive to reducing the chip area, the process is complicated and the cost of the chip; while polysilicon as the gate interconnection, a large series resistor to limit the operating frequency is increased.

发明内容 SUMMARY

(一) 要解决的技术问题 (A) To solve technical problems

有鉴于此,本发明的主要目的在于提供一种制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,以简化制作工艺,降低制作成本,提高功率DMOS晶体管的工作频率。 In view of this, the main object of the present invention is to provide a method for making a full power gate bar vertical double diffused field effect transistor self-aligned to simplify the manufacturing process, reduce manufacturing cost, increase the operating frequency of the power DMOS transistor.

(二) 技术方案 (B) Technical Solution

为达到上述目的,本发明提供了一种制作全自对准条型栅功率垂直双4扩散场效应晶体管的方法,该方法包括: To achieve the above object, the present invention provides a fully automated method of making a field effect transistor diffusion aligned vertical double gate power bar 4, the method comprising:

A、 在衬底上生长外延,然后进行场区氧化,形成场氧化层; A, epitaxially grown on a substrate, and then oxidizing the field region, field oxide is formed;

B、 刻蚀有源区的场氧化层,进行栅氧化,淀积多晶硅,对淀积的多晶硅进行掺杂; B, a field oxide layer is etched in the active region, a gate oxide, polysilicon is deposited on the doped polysilicon is deposited;

C、 对掺杂后的整个硅片进行光刻、刻蚀,硼注入,高温推进形成P- C, the entire silicon wafer after doping lithography, etching, implantation of boron, high temperature promote the formation of P-

阱区; Well region;

D、 对整个硅片进行砷注入形成浅源区,然后淀积并反刻形成侧墙; D, the entire wafer is formed shallow arsenic implantation region, is formed and then deposited and engraved counter-spacers;

E、 对整个硅片进行硼注入,并淀积钴膜,形成钴的硅化物,利用钴的硅化物形成P-阱接触; E, of the boron implantation across the wafer, and depositing a cobalt film is formed of cobalt silicide, cobalt silicide is formed using a P- well contact;

F、 进行硼磷硅玻璃淀积,光刻与刻蚀引线孔; F., Boron phosphosilicate glass deposition, photolithography and etching pin holes;

G、 金属溅射并进行光刻与刻蚀。 G, metal sputtering and photolithography and etching.

上述方案中,所述步骤A包括:在n+型Si衬底上,进行n-型Si外延层生长,随后进行场区氧化,在n-型Si外延层上形成场氧化层。 In the above embodiment, the step A comprises: on the n + -type Si substrate, a Si n- type epitaxial layer is grown, followed by the field oxide region, the field oxide layer is formed on the n- type epitaxial Si layer.

上述方案中,所述步骤B包括:利用场氧刻蚀掩模版在场氧化层上进行有源区定义,定义出有源区后,刻蚀掉有源区的场氧化层,然后进行栅氧化,并淀积多晶硅,随后对多晶硅进行一次100(TC的高温磷扩散,形成小于10Q/sq的低电阻率n+型多晶硅。 In the above embodiment, the step B comprises: using a field oxide etch mask on the field oxide layer to define an active region, the active region is defined, the field oxide layer is etched away in the active region, and then a gate oxide, and polysilicon is deposited, and then the polysilicon 100 (TC of a phosphorus diffusion temperature, to form a low resistivity of less than 10Q / sq n + type polysilicon.

上述方案中,所述步骤C包括:利用多晶硅刻蚀掩模版,刻蚀掺杂后 In the above scheme, the step C comprises: a polysilicon etching mask, etching the doped

的整个硅片,然后对刻蚀后的整个硅片进行硼注入并进行110(TC的高温推进,形成P-阱区。 Across the wafer, and then the entire wafer after etching and boron implantation for 110 (TC to promote a high temperature to form P- well region.

上述方案中,步骤D中所述对整个硅片进行砷注入,是以多晶硅为掩模,对整个硅片进行砷注入; In the above embodiment, Step D, arsenic implantation across the wafer, the polysilicon is used as a mask, arsenic implantation on the whole wafer;

步骤D中所述淀积并反刻形成侧墙,是淀积一层正硅酸乙酯TEOS, 并对淀积的TEOS进行反刻形成侧墙。 Step D deposited and engraved counter-formed spacers, is deposited a layer of tetraethyl orthosilicate TEOS, TEOS deposited and engraved anti spacer formed.

上述方案中,所述步骤E包括:对整个硅片进行90keV的大能量与2 X10"n/cmS的大剂量硼注入,大能量使注入的硼离子能透过N+源区,主要分布于N+源区之下,大剂量使P-阱区形成高浓度的P+区,有利于形成欧姆接触;然后淀积钴膜,670。C快速退火5秒,使钴与硅反应形成钴的硅化物,刻去侧墙上未反应的钴,然后80(TC快速退火10秒,使硅化物转为16〜18u Qxm的低阻态;然后利用钴的硅化物穿透浅源结结构的源区 In the above embodiment, the step E comprises: a large energy of 90keV for the entire wafer with 2 X10 "n / cmS high dose boron implantation, high energy implantation of boron ions through the N + source regions can, mainly the N + under the source region, the P- well region so that large doses of a high concentration of the P + region, is conducive to formation of an ohmic contact; cobalt film is then deposited, 670.C 5 seconds rapid thermal annealing, the cobalt to react with silicon form cobalt silicide, unreacted cobalt engraved to the sidewall, and 80 (TC flash annealing for 10 seconds 16~18u Qxm silicide into the low resistance state; then using a cobalt silicide shallow junction structures penetrating the source region

5与下面的P-阱形成接触。 5 is formed in contact with the underlying P- well.

上述方案中,所述步骤F包括:进行硼磷硅玻璃淀积,并进行95(TC 的高温回流,利用接触孔刻蚀掩模版进行引线孔光刻并刻蚀出引线孔。 In the above embodiment, the step F comprises: depositing boron phosphosilicate glass, and 95 (TC the reflux temperature, using a contact hole etching mask for photolithography pin holes and pin holes etched.

上述方案中,所述步骤G包括:溅射金属层,利用金属刻蚀掩模版对金属层进行光刻与腐蚀,形成全自对准的条型栅功率垂直双扩散场效应晶体管。 In the above embodiment, G comprises the step of: sputtering a metal layer, using a metal etch mask on the metal layer, photolithography and etching to form a stripe-shaped gate power all self-aligned vertical double diffused field effect transistor.

(三)有益效果从上述技术方案可以看出,本发明具有以下有益效果: (C) Advantageous Effects As can be seen from the above technical solutions, the present invention has the following advantages:

1、 本发明提供的这种制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,采用条型栅结构设计,条型栅DMOS是一种新型平面结构 1, the production of the present invention provides fully automated method of aligning gate power bar vertical double diffused field effect transistor using the gate bar design, a bar-type DMOS the gate is a new planar structure

的DMOS,它的多晶硅栅呈条状分布。 The DMOS, its polysilicon gate stripe shape distribution. 条形栅结构可以在单位有源区面积 Stripe-shaped gate structure may be in the unit area of ​​the active region

内集成更大的沟道宽度,同时其源区接触孔面积增大,栅面积降低,具有导通电阻小、开关速度高及工作稳定性好等特点。 Integrated within a larger channel width, while the source contact hole area is increased, gate area is decreased, having a small ON resistance, high switching speed and good working stability.

2、 本发明提供的这种制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,光刻掩模版少,共需4块光刻掩模版,其中包括场氧刻蚀掩模版、多晶硅刻蚀掩模版、接触孔刻蚀掩模版、金属刻蚀掩模版,大大简化了制作工艺,降低了制作成本。 2, the present invention provides the production of full self-alignment method bar gate power vertical double diffused field effect transistor, less photolithographic reticle, totaling four photolithographic reticle, wherein the reticle comprises a field oxide etching, polysilicon etch mask, etch a contact hole mask, a metal etch mask, greatly simplifies the manufacturing process, reducing the manufacturing cost.

3、 本发明提供的这种制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,采用N+浅源结,以便后面的硅化物可以穿透N+源区与下面的P-阱接触。 3, the production of the present invention provides fully automated method of aligning gate power bar vertical double diffused field effect transistor, using the N + shallow junction, so that the latter can penetrate silicide N + source region in contact with the underlying P- well .

4、 本发明提供的这种制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,采用侧墙工艺,在整个硅片刻蚀后,淀积一层正硅酸乙酯 4, the present invention provides the production of full self-alignment method bar gate power vertical double diffused field effect transistor, using the sidewall spacer process, after the entire wafer etching, depositing a layer of TEOS

(TEOS)并反刻形成侧墙,以便于进行下面的P-阱接触注入。 (TEOS) and back sidewall engraved formed so as to be in contact with the P- well following injection.

5、 本发明提供的这种制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,P-阱接触注入采用大能量与大剂量硼注入,大能量目的使硼透过N+源区,主要集中在P-阱区内,大剂量的目的一方面可以使后面的硅化物与P-阱形成良好的欧姆接触,另一方面可以减小P-阱区PN结反向耗尽宽度,提高器件反向耐压。 5, the production of the present invention provides fully automated method of aligning gate power bar vertical double diffused field effect transistor, P- well contact implantation using high energy implantation with a high dose of boron, boron large energy object through N + source region , mainly in the P- well region, a large dose of the latter object on the one hand allows the silicide to form a good ohmic contact with the P- well, on the other hand can reduce the P- well region reverse PN junction depletion width, improve device reverse voltage. 此步省去了传统DMOS工艺中的P-阱接触注入掩模版,以侧墙为掩模,形成P-阱区的接触注入。 This step eliminates the conventional DMOS P- well injection process, a contact mask, spacers as a mask to form a P- well region contact implantation.

66、本发明提供的这种制作全自对准条型栅功率垂直双扩散场效应晶 66, the present invention provides the production of full-power self-aligned gate bar vertical double diffused field effect transistor

体管的方法,采用钴的硅化物。 The method of the transistor, cobalt silicide. 淀积钴膜,67(TC快速退火5秒,使钴与硅反应生成硅化物。刻去侧墙上未反应的钴,然后80(TC快速退火10秒, 使硅化物转为低阻态。因为N+源区为浅源结结构,N+源区的钴硅化物穿透源区与下面的P-阱接触。另外,钴的采用同时使多晶硅栅形成低电阻率的硅化物形态,降低了器件栅极的串联电阻,有利于提高器件的开关速度与工作频率。 Depositing a cobalt film, 67 (TC flash annealing five seconds, the cobalt silicide reacts with the silicon. Engraved unreacted cobalt to the sidewall, and 80 (TC 10 seconds flash annealing the silicide into a low resistance state. because the N + source region is shallow junction structure, a cobalt silicide N + source region penetrating the source region and the underlying P- well contact. Further, cobalt in the same time the polysilicon gate to form a low resistivity silicide morphology, reducing device gate series resistance, help to improve the switching speed of the device operating frequency.

附图说明 BRIEF DESCRIPTION

图1为本发明提供的制作全自对准条型栅功率DMOS晶体管的方法流程图; FIG method of making the present invention provides a full self-aligned gate power bar flowchart DMOS transistor;

图2为依照本发明实施例制作全自对准条型栅功率DMOS晶体管版图的示意图; Figure 2 is a schematic diagram of the whole production of the bar-type self-aligned gate power DMOS transistor layout embodiment according to the present invention;

图3为依照本发明实施例制作全自对准条型栅功率DMOS晶体管工艺流程图;其中, Example 3 is produced using the entire bar-type self-aligned gate process flow diagram of a power DMOS transistor in accordance with embodiments of the present invention; wherein,

图3-1为依照本发明实施例进行外延层生长及场区氧化的示意图; FIG. 3-1, and a schematic view of an epitaxial layer grown oxide for the field region according to an embodiment of the present invention;

图3-2为依照本发明实施例定义有源区刻蚀场氧化层栅氧化与淀积多晶硅的示意图; Figure 3-2 is a schematic view of an embodiment of the active region is etched field oxide layer and the gate oxide deposited polysilicon is defined in accordance with the present invention;

图3-3为依照本发明实施例刻蚀整个硅片及剩余场氧化层的示意图; 图3-4为依照本发明实施例刻进行硼注入形成P-阱区的示意图; 图3-5为依照本发明实施例对硅片进行砷注入形成浅结N+源区的示意图; Figure 3-3 is a schematic diagram of the entire wafer is etched and the remaining field oxide layer in accordance with the embodiment of the present invention; FIG. 3-4 is a schematic view of implanted boron engraved P- well region formed in accordance with an embodiment of the present invention; FIG 3-5 in accordance with embodiments of the present invention, silicon wafers schematic shallow junction implantation of arsenic N + source region is formed;

图3-6为依照本发明实施例淀积正硅酸乙酯(TEOS)并反刻形成侧墙的示意图; FIG 3-6 is a schematic view of an embodiment according to the present invention is tetraethyl orthosilicate (TEOS) and back sidewall deposition engraved formed;

图3-7为依照本发明实施例对整个硅片进行大能量与大剂量的硼注入的示意图; FIG. 3-7 for a schematic view of the high energy boron implantation with large doses of the entire silicon wafer according to an embodiment of the present invention;

图3-S为依照本发明实施例淀积钴膜形成硅化物的示意图; 图3-9为依照本发明实施例硼磷硅玻璃淀积并光刻与刻蚀引线孔的示意图; FIG 3-S according to an embodiment of the present invention is a schematic view of the film deposition of cobalt silicide is formed; FIG. 3-9 depositing borophosphosilicate glass as an example embodiment according to the present invention is a schematic diagram of photolithography and etching pin holes;

图3-10为依照本发明实施例金属溅射并进行光刻与刻蚀的示意图。 Figure 3-10 is a schematic view and embodiment examples of the metal sputtering and photolithographic etching performed in accordance with the present invention. 具体实施方式 Detailed ways

为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明进一步详细说明。 To make the objectives, technical solutions, and advantages of the present invention will become more apparent hereinafter in conjunction with specific embodiments, and with reference to the accompanying drawings, the present invention is further described in detail.

如图1所示,图1为本发明提供的制作全自对准条型栅功率DMOS 晶体管的方法流程图,该方法包括以下步骤- As shown in FIG method, the present invention provides the production of 1 bar full self-aligned gate power DMOS transistor 1 is a flowchart, the method comprising the steps of -

步骤101:在衬底上生长外延,然后进行场区氧化,形成场氧化层; Step 101: epitaxial growth on a substrate and then oxidizing the field region, field oxide is formed;

步骤102:刻蚀有源区的场氧化层,进行栅氧化,淀积多晶硅,对淀积的多晶硅进行掺杂; Step 102: etching the field oxide layer of the active region, a gate oxide, polysilicon is deposited on the doped polysilicon is deposited;

步骤103:对掺杂后的整个硅片进行光刻、刻蚀,硼注入,高温推进形成P-阱区; Step 103: the entire wafer after doping lithography, etching, implantation of boron, high temperature promote the formation of the P- well region;

步骤104:对整个硅片进行砷注入形成浅源区,然后淀积并反刻形成侧墙; Step 104: the entire wafer shallow arsenic implantation region is formed, then deposited and engraved counter-formed spacers;

步骤105:对整个硅片进行硼注入,并淀积钴膜,形成钴的硅化物, 利用钴的硅化物形成P-阱接触; Step 105: The boron implantation across the wafer, and depositing a cobalt film is formed of cobalt silicide, cobalt silicide is formed using a P- well contact;

步骤106:进行硼磷硅玻璃淀积,光刻与刻蚀引线孔; 步骤107:金属溅射并进行光刻与刻蚀。 Step 106: boron phosphosilicate glass deposition, photolithography and etching pin holes; Step 107: metal sputtering and photolithography and etching.

基于图i所示的制作全自对准条型栅功率DMOS晶体管的方法流程图,以下结合具体的实施例对本发明制作全自对准条型栅功率DMOS晶体管的方法进一步详细说明。 Based on method of making a self-aligned as shown in full stripe type gate power DMOS transistor flowchart, the following embodiments with reference to specific embodiments of the present invention is produced using the entire bar-type self-aligned gate power DMOS transistor further detail in FIG. I.

本发明提供的这种制作全自对准条型栅功率DMOS晶体管的方法, 工艺简单,光刻掩模版少,实现了P-阱注入、N+源注入、P-阱接触注入的全自对准。 This invention provides a method of making self-aligned full stripe type gate power DMOS transistor, the process is simple, less photolithographic reticle, to achieve the P- well implants, N + source implant, the whole P- well contact self-aligned implantation . 在本实施例中,采用条型栅结构,版图样式如图2所示,图2 为依照本发明实施例制作全自对准条型栅功率DMOS晶体管版图的示意图。 In the present embodiment, using the bar-gate structure, the layout pattern shown in FIG. 2, FIG. 2 in accordance with an embodiment of the present invention produced a schematic view of the alignment stripe type gate power DMOS transistor layout fully automated.

以下结合附图3,对全自对准条型栅功率DMOS晶体管的制备方法进一步说明: 3 in conjunction with the following drawings, the whole self aligning further illustrate the preparation bar gate power DMOS transistor:

如图3-l所示,在n+型Si衬底上,进行n-型Si外延层生长,随后进行场区氧化,在n-型Si外延层上形成场氧化层。 As shown in FIG. 3-l, on the n + -type Si substrate, a Si n- type epitaxial layer is grown, followed by the field oxide region, the field oxide layer is formed on the n- type epitaxial Si layer.

如图3-2所示,利用第一块掩模版(场氧刻蚀掩模版)在场氧化层上进行有源区定义,定义出有源区后,刻蚀掉有源区的场氧化层,然后进行栅氧化,并淀积多晶硅,随后对多晶硅进行一次100(TC高温的磷扩散,形 Figure 3-2 shows the use of a reticle (reticle field oxide etch) defines an active region on the field oxide layer defining the active region, the field oxide layer is etched away in the active region, then the gate oxide, and polysilicon is deposited, and then the polysilicon 100 a phosphorus diffusion (TC high temperature, shape

成小于10Q/sq的低电阻率n+型多晶硅。 To less than 10Q / sq low resistivity n + type polysilicon.

如图3-3所示,利用第二块掩模版(多晶硅刻蚀掩模版),刻蚀掺杂后的整个硅片及剩余的场氧化层。 As shown in Figure 3-3, the second block using a reticle (reticle polysilicon etch), the entire wafer and the field oxide layer remaining after etching doped.

如图3-4所示,对刻蚀后的整个硅片进行硼注入并进行UO(TC的高温推进,形成P-阱区。 As shown, the entire wafer after etching and boron implantation UO (TC promote high temperature, forming the P- well region 3-4.

如图3-5所示,对硅片进行砷注入。 3-5, the silicon wafers implanted arsenic. 此步进行砷注入,而不是传统DMOS工艺中的磷注入,目的是形成浅结N十源区,同时此歩还去除了传统DMOS工艺中的N+源掩模版,仅以多晶硅为掩模,对整个硅片进行注入。 This arsenic implantation step, instead of the phosphorus implant in the conventional DMOS technology, the purpose of forming a shallow junction N + source region, but this also removes ho conventional DMOS processes the N + source mask, only polysilicon as a mask implanting the entire wafer.

如图3-6所示,淀积一层正硅酸乙酯(TEOS)并反刻形成侧墙,以便于进行下面的P-阱接触注入。 3-6, depositing a layer of tetraethylorthosilicate (TEOS) and back sidewall engraved formed so as to be in contact with the P- well following injection.

如图3-7所示,对整个硅片进行90keV的大能量与2X 1055n/cm2的大剂量硼注入,大能量使注入的硼离子能透过N+源区,主要分布于N+源下,大剂量使P-阱区形成高浓度的P+区,有利于形成良好欧姆接触。 As shown, the entire silicon wafers 3-7 large energy 90keV with large dose of 2X 1055n / cm2 boron implantation, high energy implantation of boron ions through the N + source regions can be, mainly in the N + source, a large dose so that P- well region forming the high concentration P + region, it is conducive to formation of a good ohmic contact.

如图3-8所示,淀积钴膜,67(TC快速退火5秒,使钴与硅反应生成硅化物。刻去恻墙上未反应的钴,然后8WTC快速退火10秒,使硅化物转为i6〜18ii Qxm的低阻态。因为N+源区为浅源结结构,N+源区的钴硅化物穿透源区与下面的P-阱接触。 Shown in Figure 3-8, a cobalt film is deposited, 67 (TC flash annealing five seconds, the cobalt silicide reacts with the silicon. Engraved to sad wall unreacted cobalt and 8WTC rapid thermal annealing for 10 seconds, so that a silicide i6~18ii Qxm into the low resistance state. because the N + source region is shallow junction structure, N + source regions penetrate cobalt silicide source contact with the underlying P- well.

如图3-9所示,硼磷硅玻璃淀积并进行95(TC的高温回流,利用第三块掩模版(接触孔刻蚀掩模版)进行引线孔光刻并刻蚀出引线孔。 As shown in Figure 3-9, borophosphosilicate glass is deposited and 95 (TC the reflux temperature, using a third block reticle (reticle etching a contact hole) for pin holes etched photolithography and pin holes.

如图3-10所示,最后溅射金属层,并利用第四块掩模版(金属刻蚀掩模版)对金属层进行光刻与腐蚀。 As shown, the last 3-10 sputtered metal layer, and using a fourth block reticle (reticle metal etch) the metal layer lithography and etching.

上述实施例中,采用条型栅结构设计,条型栅DMOS是一种新型平面栅结构的DMOS,它的多晶硅栅呈条状分布。 The above-described embodiment using stripe type gate structure design, a bar-type DMOS the gate DMOS is a novel planar gate structure, its polysilicon gate stripe shape distribution. P-阱、P-阱接触注入、N+源注入均采用自对准工艺,无需增加光刻掩模版,仅需4块掩模版,工艺简单,芯片加工成本降低。 P- well, injection well contact P-, N + source implantation are self-aligned process without increasing the photolithographic reticle, only four reticle, simple process, reducing chip processing cost. 同时硅化物工艺的采用可以有效降低栅串联电阻,提高功率DMOS晶体管的工作频率。 While using silicide process can effectively reduce the series resistance of the gate, to improve the working frequency of the power DMOS transistor. 省去了传统DMOS工艺中的N+源掩模版,仅以多晶硅为掩模;进行砷注入,而不是传统DMOS工艺中 Eliminating the N + source mask in conventional DMOS technology, only polysilicon as a mask; arsenic implantation, rather than the traditional process DMOS

9的磷注入,目的是形成浅结N+源区。 Phosphorus implant 9, the purpose of forming a shallow junction N + source region. 省去了传统DMOS工艺中的P+阱接触注入模版,以侧墙为掩模。 Eliminating the traditional processes DMOS P + well contact implant templates to spacer as a mask.

以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。 The above-described specific embodiments of the object, technical solutions, and advantages of the invention will be further described in detail, should be understood that the above descriptions are merely embodiments of the present invention, but not intended to limit the invention, within the spirit and principle of the present invention, any modifications, equivalent replacements, improvements, etc., should be included within the scope of the present invention.

Claims (8)

  1. 1、一种制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,其特征在于,该方法包括: A、在衬底上生长外延,然后进行场区氧化,形成场氧化层; B、刻蚀有源区的场氧化层,进行栅氧化,淀积多晶硅,对淀积的多晶硅进行掺杂; C、对掺杂后的整个硅片进行光刻、刻蚀,硼注入,高温推进形成P-阱区; D、对整个硅片进行砷注入形成浅源区,然后淀积并反刻形成侧墙; E、对整个硅片进行硼注入,并淀积钴膜,形成钴的硅化物,利用钴的硅化物形成P-阱接触; F、进行硼磷硅玻璃淀积,光刻与刻蚀引线孔; G、金属溅射并进行光刻与刻蚀。 1. A method of making fully automatic gate power bar vertical double diffused field effect transistor are aligned, characterized in that the method comprises: A, epitaxial growth on a substrate and then oxidizing the field region, field oxide is formed; B, a field oxide layer is etched in the active region, a gate oxide, polysilicon is deposited on the doped polysilicon is deposited; C, the entire silicon wafer after doping lithography, etching, implantation of boron, high temperature promote the formation of the P- well region; D, the entire wafer is formed shallow arsenic implantation region, is formed and then deposited and engraved counter-spacers; E, of the boron implantation across the wafer, and depositing a cobalt film is formed of cobalt silicide, cobalt silicide is formed using a P- well contact; F, boron phosphosilicate glass deposition, lithography and etching the lead hole; G, metal sputtering and photolithography and etching.
  2. 2、 根据权利要求1所述的制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,其特征在于,所述步骤A包括:在n+型Si衬底上,进行n-型Si外延层生长,随后进行场区氧化,在n-型Si外延层上形成场氧化层。 2, according to claim 1 prepared according to methods fully automatic aligning bar gate power vertical double diffused field effect transistor, wherein said step A comprises: on the n + -type Si substrate, a n- type Si epitaxial layer growth, followed by the field oxide region, the field oxide layer is formed on the n- type epitaxial Si layer.
  3. 3、 根据权利要求1所述的制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,其特征在于,所述步骤B包括:利用场氧刻蚀掩模版在场氧化层上进行有源区定义,定义出有源区后,刻蚀掉有源区的场氧化层,然后进行栅氧化,并淀积多晶硅,随后对多晶硅进行一次100(TC的高温磷扩散,形成小于10Q/sq的低电阻率n+型多晶硅。 3, prepared according to claim 1 bar fully automated method of aligning gate power vertical double diffused field effect transistor, wherein said step B comprises: using a field oxide etch mask on the field oxide layer for after the source region is defined, the definition of an active region, the field oxide layer is etched away in the active region, and then the gate oxide, and polysilicon is deposited, and then the polysilicon 100 (TC of a high temperature phosphorus diffusion, is formed smaller than 10Q / sq low resistivity n + type polysilicon.
  4. 4、 根据权利要求1所述的制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,其特征在于,所述步骤C包括:利用多晶硅刻蚀掩模版,刻蚀掺杂后的整个硅片,然后对刻蚀后的整个硅片进行硼注入并进行110(TC的高温推进,形成P-阱区。 4, according to claim 1, wherein fabricating the self-aligned method of full power gate bar vertical double diffused field effect transistor, wherein the step C comprises: etching polysilicon using the mask, etching the doped across the wafer, and then the entire wafer after etching and boron implantation for 110 (TC to promote a high temperature to form P- well region.
  5. 5、 根据权利要求1所述的制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,其特征在于,步骤D中所述对整个硅片进行砷注入,是以多晶硅为掩模,对整个硅片进行砷注入;步骤D中所述淀积并反刻形成侧墙,是淀积一层正硅酸乙酯TEOS,并对淀积的TEOS进行反刻形成侧墙。 5, according to claim 1, wherein fabricating the self-aligned method of full power gate bar vertical double diffused field effect transistor, wherein said Step D arsenic implantation across the wafer, the polysilicon is used as a mask , the entire wafer arsenic implantation; step D deposited and engraved counter-formed spacers, is deposited a layer of tetraethyl orthosilicate TEOS, TEOS deposited and engraved anti spacer formed.
  6. 6、 根据权利要求1所述的制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,其特征在于,所述步骤E包括-对整个硅片进行90keV的大能量与2X 1015n/cm2的大剂量硼注入,大能量使注入的硼离子能透过N+源区,主要分布于N+源区之下,大剂量使P-阱区形成高浓度的P+区,有利于形成欧姆接触;然后淀积钴膜,67(TC快速退火5秒,使钴与硅反应形成钴的硅化物,刻去侧墙上未反应的钴,然后80CTC快速退火10秒,使硅化物转为16〜18y Q.cm的低阻态;然后利用钴的硅化物穿透浅源结结构的源区与下面的P-阱形成接触。 6, the whole process according to a bar-type self-aligned vertical double diffused gate power field effect transistor produced according to claim 1, wherein said step E comprises - 90keV with large energy to the entire wafer 2X 1015n / cm2 high-dose boron implantation, high energy boron ion implantation energy through the N + source region, mainly the N + under the source region, large doses so that P- well region forming high-concentration P + region, is conducive to formation of an ohmic contact; cobalt film is then deposited, 67 (TC flash annealing five seconds, the cobalt to react with silicon form cobalt silicide, to cut the spacer unreacted cobalt and 80CTC rapid thermal annealing for 10 seconds into silicide 16~18y Q.cm the low resistance state; then using a cobalt silicide penetrate below the source region and the shallow junction structure is formed in contact with the P- well.
  7. 7、 根据权利要求1所述的制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,其特征在于,所述步骤F包括:进行硼磷硅玻璃淀积,并进行950。 7, prepared according to the method of claim 1, the gate bar vertical double diffused field effect power transistor full self-alignment, characterized in that said step F comprises: performing borophosphosilicate glass is deposited, and 950. C的高温回流,利用接触孔刻蚀掩模版进行弓i线孔光刻并刻蚀出引线孔。 C to reflux temperature, the contact hole etching mask for the bow and the i-line lithography etched hole pin holes.
  8. 8、 根据权利要求1所述的制作全自对准条型栅功率垂直双扩散场效应晶体管的方法,其特征在于,所述步骤G包括:溅射金属层,利用金属刻蚀掩模版对金属层进行光刻与腐蚀,形成全自对准的条型栅功率垂直双扩散场效应晶体管。 8, according to claim 1, wherein fabricating the self-aligned method of full power gate bar vertical double diffused field effect transistor, wherein said step G comprises: sputtering a metal layer, using a metal etch mask on the metal plate layer photolithography and etching to form a stripe-shaped gate power all self-aligned vertical double diffused field effect transistor.
CN 200710122480 2007-09-26 2007-09-26 Method for fabricating full-self-aligned stripe shaped grating power perpendicular double diffusion field effect transistor CN100590850C (en)

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CN101719472B (en) 2009-11-18 2011-07-06 上海宏力半导体制造有限公司 Method for preparing vertical double-diffusion MOS transistor
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