CN104810289A - VDMOS (vertical double-diffused metal oxide semiconductor) transistor manufacturing method and VDMOS - Google Patents

VDMOS (vertical double-diffused metal oxide semiconductor) transistor manufacturing method and VDMOS Download PDF

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Publication number
CN104810289A
CN104810289A CN201410040108.3A CN201410040108A CN104810289A CN 104810289 A CN104810289 A CN 104810289A CN 201410040108 A CN201410040108 A CN 201410040108A CN 104810289 A CN104810289 A CN 104810289A
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China
Prior art keywords
layer
source region
titanium
silicide
type source
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CN201410040108.3A
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马万里
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Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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Priority to CN201410040108.3A priority Critical patent/CN104810289A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

Abstract

The invention provides a VDMOS (vertical double-diffused metal oxide semiconductor) transistor manufacturing method and a VDMOS. The method includes the steps: sequentially forming a gate oxide layer, a polycrystalline silicon layer, a P- body area, an N-type source area, a silicon nitride layer and a P+ body area on a silicon slice; etching the silicon nitride layer and the gate oxide layer to form a side wall on the side of the polycrystalline silicon layer; forming a titanium silicide layer on the upper surface of each of the polycrystalline silicon layer and the N-type source area, and reducing the resistance of titanium silicide; sequentially forming a dielectric layer, a contact hole and a metal layer and respectively connecting the metal layer with the side face of the N-type source area and the side face of the titanium silicide on the upper surface of the N-type source area.

Description

A kind of manufacture method of VDMOS pipe and VDMOS
Technical field
The present invention relates to semiconductor chip formation process technology, particularly relate to a kind of vertical DMOS transistor (Vertical Double-diffused MOSFET; Be called for short: manufacture method VDMOS) and VDMOS.
Background technology
Fig. 1 is the structure principle chart of prior art planar-type VDMOS pipe, as shown in fig. 1, in order to ensure pulse avalanche breakdown (Single Pulse Avalanche Energy; Be called for short: EAS) ability, in the structure of plane VDMOS pipe, source region and tagma need short circuit.At present, the way of in prior art, source region and tagma being carried out short circuit is: fill metal etching in silicon hole out, thus by metal by source region and tagma short circuit, wherein, the contact-making surface in metal and source region can as shown in the dashed circle in Fig. 1.
But as shown in Figure 1, the contact area in metal and source region is very little, be namely mainly connected with metal by the side in source region, then metal Zai Yu P+ district short circuit gets up, thus makes the effect of short circuit relatively poor, and then the problem causing EAS ability poor.
Summary of the invention
The invention provides a kind of manufacture method and VDMOS of VDMOS pipe, for improving the short circuit effect in source region and P+ tagma, and then improving EAS ability.
First aspect of the present invention is to provide improving one's methods of a kind of EAS ability, comprising:
Silicon chip is formed gate oxide, polysilicon layer, P-tagma, N-type source region, silicon nitride layer and P+ tagma successively;
Etching processing is carried out to described silicon nitride layer and described gate oxide, forms side wall with the sidewall at described polysilicon layer;
Form the silicide of one deck titanium at the upper surface in described polysilicon layer and N-type source region, and reduce the resistance of the silicide of described titanium;
Form dielectric layer, contact hole and metal level successively, be connected with the side of the silicide of the titanium of the side in described N-type source region and the upper surface in described N-type source region respectively to make described metal level.
Another aspect of the present invention is to provide a kind of VDMOS, comprise: N-type substrate, in the N-type epitaxy layer that described N-type substrate upper surface is formed, at the gate oxide that described N-type epitaxy layer upper surface is formed, at the polysilicon layer that described gate oxide upper surface is formed, the P-tagma that described N-type substrate is formed, N-type source region and P+ tagma, the side wall of the described polysilicon layer formed by the etching to the silicon nitride layer that described polysilicon layer is formed and described gate oxide, the silicide layer of the titanium that the upper surface in described polysilicon layer and N-type source region is formed, at described polysilicon layer, the medium that the side wall of described polysilicon layer and the surface of described silicide layer are formed, the contact hole formed above described P+ tagma, and at the upper surface of described dielectric layer, in described contact hole and described N-type substrate lower surface formed metal level,
Wherein, described metal level is connected with the side of the silicide of the titanium on the side in described N-type source region and the surface in described N-type source region respectively.
Technique effect of the present invention is: on silicon chip, form gate oxide, polysilicon layer, P-tagma, N-type source region, silicon nitride layer and P+ tagma successively, etching processing is carried out to this silicon nitride layer and this gate oxide, forms side wall with the sidewall at this polysilicon layer, form the silicide of one deck titanium at the upper surface in this polysilicon layer and N-type source region, and reduce the resistance of the silicide of this titanium, form dielectric layer successively again, contact hole and metal level, be connected with the side of the silicide of the titanium of the side in this N-type source region and the upper surface in this N-type source region respectively to make this metal level, while metal level is connected with the side in this N-type source region, be connected with the side of the silicide of the titanium of the upper surface in this N-type source region, and the resistivity of the Titanium silicide on surface on source region is minimum, and cover the upper surface in whole source region, this has extended to the surface in whole source region by being equivalent to metal level, therefore the contact area of source region and metal level is made to become large, thus improve the short circuit effect in source region and P+ tagma, and then improve EAS ability.
Accompanying drawing explanation
Fig. 1 is the structure principle chart of prior art planar-type VDMOS pipe;
Fig. 2 is the flow chart of an embodiment of the manufacture method of VDMOS pipe of the present invention;
Fig. 3 a is the schematic diagram of the formation method of gate oxide and polysilicon layer in the present embodiment;
Fig. 3 b is the schematic diagram of the formation method in P-tagma in the present embodiment;
Fig. 3 c is the schematic diagram of the formation method in N-type source region in the present embodiment;
Fig. 3 d is the schematic diagram of the formation method in silicon nitride layer and P+ tagma in the present embodiment;
Fig. 3 e is the schematic diagram of the generation type of the sidewall formation side wall of polysilicon layer in the present embodiment;
Fig. 3 f is the schematic diagram of the silicide of titanium in the present embodiment;
Fig. 3 g is the schematic diagram of the generation type of the present embodiment dielectric layer and contact hole;
Fig. 3 h is the schematic diagram of the generation type of metal level in the present embodiment;
Fig. 4 is the flow chart of another embodiment of the manufacture method of VDMOS pipe of the present invention.
Embodiment
Fig. 2 is the flow chart of an embodiment of the manufacture method of VDMOS pipe of the present invention, and as shown in Figure 2, the method for the present embodiment comprises:
Step 101, on silicon chip, form gate oxide, polysilicon layer, P-tagma, N-type source region, silicon nitride layer and P+ tagma successively.
In the present embodiment, Fig. 3 a is the schematic diagram of the formation method of gate oxide and polysilicon layer in the present embodiment, as shown in Figure 3 a, this gate oxide is formed in the upper surface of N-type epitaxy layer, and forms polysilicon layer at the upper surface of this gate oxide.Wherein, N-type epitaxy layer is formed in the upper surface of N-type substrate.This growth of gate oxide layer temperature is more than or equal to 900 DEG C, and is less than or equal to 1100 DEG C; Its thickness is more than or equal to 0.05um, and is less than or equal to 0.20um.
In addition, Fig. 3 b is the schematic diagram of the formation method in P-tagma in the present embodiment, as shown in Figure 3 b, the generation type in P-tagma is specially: inject boron ion to form P-tagma, wherein, the dosage of boron ion is more than or equal to 1.0E14/cm, and is less than or equal to 1.0E15/cm; Its energy is more than or equal to 100KEV, and is less than or equal to 150KEV.Then adopt to preset to drive in temperature and preset and drive in the time and drive in this P-tagma, wherein, this is preset and drives in temperature and be more than or equal to 1100 DEG C, and is less than or equal to 1200 DEG C; Preset and drive in the time and be more than or equal to 50 minutes, and be less than or equal to 200 minutes.
Fig. 3 c is the schematic diagram of the formation method in N-type source region in the present embodiment, as shown in Figure 3 c, the generation type in N-type source region is specially: injection arsenic ion or phosphonium ion are to form N-type source region, wherein, the dosage of this arsenic ion or phosphonium ion is more than or equal to 1.0E15/cm, and is less than or equal to 1.0E16/cm; Its energy for being more than or equal to 100KEV, and is less than or equal to 150KEV.
Fig. 3 d is the schematic diagram of the formation method in silicon nitride layer and P+ tagma in the present embodiment, as shown in Figure 3 d, the generation type in this silicon nitride layer and P+ tagma is specially: form silicon nitride layer at the upper surface of polysilicon layer and gate oxide, wherein, the growth temperature of this silicon nitride layer is more than or equal to 700 DEG C, and is less than or equal to 900 DEG C; Its thickness is more than or equal to 0.1um, and is less than or equal to 0.3um.Then inject boron ion (the P type ion namely shown in Fig. 3 d) to form this P+ tagma, wherein, this boron ion dose is more than or equal to 1.0E15/cm, and is less than or equal to 1.0E16/cm; Its energy for being more than or equal to 100KEV, and is less than or equal to 150KEV.
Step 102, etching processing is carried out to this silicon nitride layer and this gate oxide, form side wall with the sidewall at this polysilicon layer.
In the present embodiment, concrete, Fig. 3 e is the schematic diagram of the generation type of the sidewall formation side wall of polysilicon layer in the present embodiment, as shown in Figure 3 e, carries out etching processing to this silicon nitride layer and this gate oxide, thus forms side wall at the sidewall of this polysilicon layer.
Step 103, form the silicide of one deck titanium at the upper surface in this polysilicon layer and N-type source region, and reduce the resistance of the silicide of this titanium.
In the present embodiment, concrete, Fig. 3 f is the schematic diagram of the silicide of titanium in the present embodiment, and as illustrated in figure 3f, the Formation of silicide of this titanium is on the surface in polysilicon layer and N-type source region.
Step 104, form dielectric layer, contact hole and metal level successively, be connected with the side of the silicide of the titanium of the side in this N-type source region and the upper surface in this N-type source region respectively to make this metal level.
In the present embodiment, concrete, Fig. 3 g is the schematic diagram of the generation type of the present embodiment dielectric layer and contact hole, and as shown in figure 3g, dielectric layer is made up of undope silicon dioxide and phosphorosilicate glass, and wherein, the thickness of plain silicon dioxide is 0.2um; The thickness of phosphorosilicate glass is 0.8um.
In addition, Fig. 3 h is the schematic diagram of the generation type of metal level in the present embodiment, and as illustrated in figure 3h, the metal level in dielectric layer side can be referred to as front metal layer, and it needs to carry out photoetching and etching processing.Metal layer on back (or titanium nickeline composite bed) is referred to as at the metal level of N-type substrate side.From Fig. 3 h, when front metal layer is connected with the side in source region, also be connected with the side of the Titanium silicide on the surface in source region simultaneously, because the resistivity of the Titanium silicide on the surface in source region is minimum, and cover the upper surface in whole source region, this has extended to the surface in whole source region by being equivalent to metal level, thus the contact area of source region and metal level is become greatly, and then improves the short circuit effect in source region and P+ tagma.
In the present embodiment, gate oxide, polysilicon layer, P-tagma, N-type source region, silicon nitride layer and P+ tagma is formed successively, etching processing is carried out to this silicon nitride layer and this gate oxide, forms side wall with the sidewall at this polysilicon layer, form the silicide of one deck titanium at the upper surface in this polysilicon layer and N-type source region, and reduce the resistance of the silicide of this titanium, form dielectric layer successively again, contact hole and metal level, be connected with the side of the silicide of the titanium of the side in this N-type source region and the upper surface in this N-type source region respectively to make this metal level, while metal level is connected with the side in this N-type source region, be connected with the side of the silicide of the titanium of the upper surface in this N-type source region, and the resistivity of the Titanium silicide of the upper surface in source region is minimum, and cover the upper surface in whole source region, this has extended to the surface in whole source region by being equivalent to metal level, therefore the contact area of source region and metal level is made to become large, thus improve the short circuit effect in source region and P+ tagma, and then improve EAS ability.
Fig. 4 is the flow chart of another embodiment of the manufacture method of VDMOS pipe of the present invention, on above-mentioned basis embodiment illustrated in fig. 2, as shown in Figure 4, a kind of specific implementation forming the silicide of one deck titanium in step 103 on the surface in this polysilicon layer and N-type source region is:
Step 201, on the upper surface in this polysilicon layer and N-type source region, form titanium layer.
Step 202, silicon chip is carried out to the high temperature anneal of the first preset temperature, with the silicide making the upper surface in this polysilicon layer and the N-type source region contacted with this titanium layer form one deck titanium.
Step 203, mixed liquor by sulfuric acid and hydrogen peroxide, remove unnecessary unreacted titanium layer.
In this enforcement, the upper surface in this polysilicon layer and N-type source region forms titanium layer, the thickness of this titanium layer is more than or equal to 0.02 millimeter, and is less than or equal to 0.06 millimeter.And silicon chip is carried out to the high temperature anneal of the first preset temperature, thus make the upper surface in polysilicon layer and the N-type source region contacted with titanium layer all can form the silicide of one deck titanium, and it should be noted that, titanium and silicon nitride, the side wall surface namely formed at the sidewall of polysilicon layer can not form the silicide of titanium.Then by the mixed liquor of sulfuric acid and hydrogen peroxide, unnecessary unreacted titanium layer is removed.Wherein, this first preset temperature is more than or equal to 600 DEG C, and is less than or equal to 800 DEG C.
Preferably, a kind of specific implementation reducing the resistance of the silicide of this titanium in step 103 is:
Step 204, this silicon chip is carried out to the high temperature anneal of the second preset temperature, to reduce the resistance of the silicide of this titanium.
In the present embodiment, this second preset temperature is more than or equal to 800 DEG C, and is less than or equal to 1000 DEG C.
Present invention also offers a kind of VDMOS, comprise: N-type substrate, in the N-type epitaxy layer that this N-type substrate upper surface is formed, at the gate oxide that this N-type epitaxy layer upper surface is formed, at the polysilicon layer that this gate oxide upper surface is formed, the P-tagma that this N-type substrate is formed, N-type source region and P+ tagma, the side wall of this polysilicon layer formed by the etching to the silicon nitride layer that this polysilicon layer is formed and this gate oxide, the silicide layer of the titanium that the upper surface in this polysilicon layer and N-type source region is formed, at this polysilicon layer, the medium that the side wall of this polysilicon layer is formed with the surface of this silicide layer, the contact hole formed above this P+ tagma, and at the upper surface of this dielectric layer, in this contact hole and this N-type substrate lower surface formed metal level, wherein, this metal level is connected with the side of the silicide of the titanium on the side in this N-type source region and the surface in this N-type source region respectively.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims (7)

1. a manufacture method for vertical DMOS crystal VDMOS pipe, is characterized in that, comprising:
Silicon chip is formed gate oxide, polysilicon layer, P-tagma, N-type source region, silicon nitride layer and P+ tagma successively;
Etching processing is carried out to described silicon nitride layer and described gate oxide, forms side wall with the sidewall at described polysilicon layer;
Form the silicide of one deck titanium at the upper surface in described polysilicon layer and N-type source region, and reduce the resistance of the silicide of described titanium;
Form dielectric layer, contact hole and metal level successively, be connected with the side of the silicide of the titanium of the side in described N-type source region and the upper surface in described N-type source region respectively to make described metal level.
2. method according to claim 1, is characterized in that, the described surface in described polysilicon layer and N-type source region forms the silicide of one deck titanium, comprising:
The upper surface in described polysilicon layer and N-type source region forms titanium layer;
Described silicon chip is carried out to the high temperature anneal of the first preset temperature, with the silicide making the upper surface in described polysilicon layer and the N-type source region contacted with described titanium layer form one deck titanium;
By the mixed liquor of sulfuric acid and hydrogen peroxide, remove unnecessary unreacted titanium layer.
3. method according to claim 2, is characterized in that, the resistance of the silicide of the described titanium of described reduction, comprising:
Described silicon chip is carried out to the high temperature anneal of the second preset temperature, to reduce the resistance of the silicide of described titanium.
4. method according to claim 2, is characterized in that, the thickness of described titanium layer is more than or equal to 0.02 millimeter, and is less than or equal to 0.06 millimeter.
5. method according to claim 2, is characterized in that, described first preset temperature is more than or equal to 600 DEG C, and is less than or equal to 800 DEG C.
6. method according to claim 3, is characterized in that, described second preset temperature is more than or equal to 800 DEG C, and is less than or equal to 1000 DEG C.
7. a VDMOS, it is characterized in that, comprise: N-type substrate, in the N-type epitaxy layer that described N-type substrate upper surface is formed, at the gate oxide that described N-type epitaxy layer upper surface is formed, at the polysilicon layer that described gate oxide upper surface is formed, the P-tagma that described N-type substrate is formed, N-type source region and P+ tagma, the side wall of the described polysilicon layer formed by the etching to the silicon nitride layer that described polysilicon layer is formed and described gate oxide, the silicide layer of the titanium that the upper surface in described polysilicon layer and N-type source region is formed, at described polysilicon layer, the medium that the side wall of described polysilicon layer and the surface of described silicide layer are formed, the contact hole formed above described P+ tagma, and at the upper surface of described dielectric layer, in described contact hole and described N-type substrate lower surface formed metal level,
Wherein, described metal level is connected with the side of the silicide of the titanium on the side in described N-type source region and the surface in described N-type source region respectively.
CN201410040108.3A 2014-01-27 2014-01-27 VDMOS (vertical double-diffused metal oxide semiconductor) transistor manufacturing method and VDMOS Pending CN104810289A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108155239A (en) * 2017-12-21 2018-06-12 深圳市晶特智造科技有限公司 Vertical bilateral diffusion metallic oxide transistor and preparation method thereof
CN111933700A (en) * 2020-09-29 2020-11-13 中芯集成电路制造(绍兴)有限公司 Power semiconductor device and method for manufacturing the same

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CN1937176A (en) * 2005-09-23 2007-03-28 半导体元件工业有限责任公司 Method of forming a low resistance semiconductor contact and structure therefor
CN101399227A (en) * 2007-09-26 2009-04-01 中国科学院微电子研究所 Method for making fully self-aligning bar gate power vertical bilateral diffusion field-effect tranisistor
CN102738229A (en) * 2011-03-31 2012-10-17 无锡维赛半导体有限公司 Structure of power transistor and method for manufacturing power transistor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1937176A (en) * 2005-09-23 2007-03-28 半导体元件工业有限责任公司 Method of forming a low resistance semiconductor contact and structure therefor
CN101399227A (en) * 2007-09-26 2009-04-01 中国科学院微电子研究所 Method for making fully self-aligning bar gate power vertical bilateral diffusion field-effect tranisistor
CN102738229A (en) * 2011-03-31 2012-10-17 无锡维赛半导体有限公司 Structure of power transistor and method for manufacturing power transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108155239A (en) * 2017-12-21 2018-06-12 深圳市晶特智造科技有限公司 Vertical bilateral diffusion metallic oxide transistor and preparation method thereof
CN108155239B (en) * 2017-12-21 2020-08-28 南京溧水高新创业投资管理有限公司 Vertical double-diffused metal oxide transistor and manufacturing method thereof
CN111933700A (en) * 2020-09-29 2020-11-13 中芯集成电路制造(绍兴)有限公司 Power semiconductor device and method for manufacturing the same

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Application publication date: 20150729