CN103367413B - A kind of insulated gate bipolar transistor and manufacture method thereof - Google Patents
A kind of insulated gate bipolar transistor and manufacture method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
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- 238000009792 diffusion process Methods 0.000 claims abstract description 46
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 144
- 239000012212 insulator Substances 0.000 claims description 56
- 229920005591 polysilicon Polymers 0.000 claims description 52
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 42
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 39
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 38
- 230000004888 barrier function Effects 0.000 claims description 35
- 239000012535 impurity Substances 0.000 claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 238000001259 photo etching Methods 0.000 claims description 26
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- 235000012239 silicon dioxide Nutrition 0.000 claims description 21
- 239000000377 silicon dioxide Substances 0.000 claims description 21
- 238000000137 annealing Methods 0.000 claims description 18
- 238000005516 engineering process Methods 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 14
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 229910004205 SiNX Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 10
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
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Abstract
The semiconductor device relating to electric and electronic technical field of the present invention, be specially a kind of insulated gate bipolar transistor and manufacture method thereof, comprise the first conductivity type substrate, the second conduction type base region is provided with in first interarea of the first conductivity type substrate, the second conductive-type moldeed depth diffusion region is provided with in second conduction type base region, be provided with transverse electric path unit first conduction type emitter region in second conduction type base region, under the design reducing device window, due to the precision reason of mask aligner during electrode hole etching, sometimes electrode can not with emitter while contact, device half is caused to lose efficacy, the setting of second unit 142 emitter region of transverse direction of the present invention then can realize under any circumstance electrode and can contact with both sides emitter, which increase the reliability of device.
Description
Technical field
The semiconductor device relating to electric and electronic technical field of the present invention, is specially a kind of insulated gate bipolar transistor and manufacture method thereof.
Background technology
Existing insulated gate bipolar transistor IGBT (comprises SiO2 floor primarily of N-drift region, P tagma, dark P+ district, N+ emitter region, P+ collector region, SiO2 grid oxide layer, polycrystalline silicon gate layer, SiO2 oxide layer, PSG phosphorosilicate glass layer, SiO2 layer) and front metal layer, metal layer on back composition.Front metal layer contacts P tagma and N+ emitter region simultaneously, forms the emitter of device.Back metal contacts P+ collector region, forms the collector electrode of device.Polysilicon gate forms device grids together with the metal connected.
As shown in Figure 2, the PIN diode district (width is L) defined by polysilicon gate and the PNP bipolar transistor district (width is W) defined by polysilicon gate interval can be divided in IGBT device.When device forward conduction, the Channeling implantation that electronics is formed from N+ emitter through polysilicon gate is to N-drift region.Hole is injected into N-drift region from P+ collector electrode simultaneously.For PIN diode district, because the electron hole stored is more, due to the conductivity modulation effect of semiconductor excess carrier, make the resistance in this region lower.Contrary to PNP bipolar transistor district, because the electron hole stored is less, the resistance in this region is higher.Electric current flows through these two regions of PNP and PIN simultaneously, forms conduction voltage drop Vce(sat).The ratio W:L reducing high resistant PNP region and low-resistance PIN peak width can reduce the Vce(sat of device).
IGBT manufacturing process traditional is at present as follows:
(1) gate oxide is grown in the side of N-drift region by the mode of thermal oxidation, and by LPCVD deposit spathic silicon on gate oxide, and use POCl3 to adulterate to polysilicon.
(2) by photoetching, dry etching, the polysilicon gate forming separation has not had polysilicon to cover window between grid, injects boron in the window, anneals, pushes away trap process, forms P tagma.
(3) form emitter pattern in the both sides of window region by photoetching, and inject phosphorus in emitter pattern; Remove photoresist, inject phosphorus in the window; Anneal, push away trap process, form He Shen P+ district, N+ emitter region.
(4) on window region and polysilicon gate, SiO2, rear regrowth one deck PSG or BPSG is deposited by LPCVD or PECVD; By photoetching, dry etching between the N+ district, middle part that window goes and in the middle part of P+ district, form contact motor hole.
(5) inject boron overleaf, annealing pushes away trap process and forms P+ collector electrode; Metal electrode formation IGBT device is made by evaporating or sputtering again at front and back.
By IGBT manufacturing process above, we can see, technological process have employed repeatedly photoetching and etching processing, because mask aligner itself exists the problem of alignment precision, within the width that the precision making the width W of the Window layer between polysilicon gate can only be limited to mask aligner can reach, as the width W of further reduction of device Window layer, much hidden danger will be brought to device.Particularly in step (3) to the photoetching of N+ emitter region, very possible appearance causes Graphic transitions deviation because of overlapping partially, and the N+ emitter as side in window does not have and Metal Contact, causes device active region half to lose efficacy.Meanwhile, to the short circuit that the photoetching of electrode hole can occur between emitter and grid because cover is inclined in step (4), device is caused all to lose efficacy.So, utilize the IGBT device that existing technology is produced, ubiquity, because the restriction of alignment accuracy of lithography machine, causes device architecture to owe reasonable and affects running parameter and the reliability of device, because the dependence to mask aligner equipment in needing a kind of new device layout to reduce to produce.
If the patent No. is CN201110165393.8, patent name is the patent of invention of " igbt and manufacture method ", its technical scheme is: a kind of igbt, comprise: collector region, be made up of the P-type layer be formed at bottom silicon substrate, draw collector electrode from the back side of described silicon substrate; Drift region, is made up of the N+ layer be formed at successively on described collector region and a N-layer, and the N-type impurity concentration of a described N+ layer is greater than the N-type impurity concentration of a described N-layer; P trap, is formed in a described N-layer; Emitter region, be made up of the 2nd N+ layer being formed at described P trap top, described emitter region and described drift region separate by described P trap; Grid, P trap described in cover part, the described P trap covered by described grid is channel region, and described channel region connects the described drift region of described P trap both sides and described emitter region; It is characterized in that: in described P trap, be formed with groove or hole, in the described P trap of the bottom in described groove or hole, be formed with P+ articulamentum, described P+ articulamentum is positioned at the bottom of described emitter region; Be formed with emitter terminal hole at described groove or top, hole, the width in described emitter terminal hole is greater than the width in described groove or hole, is filled with metal and draws emitter in described groove or hole and described emitter terminal hole.
In configuration aspects, the polysilicon window opening of the bipolar transistor that above-mentioned patent describes is comparatively large, and the distance of electrode hole and polysilicon only has 1.5 ~ 3.5um, and at more than 2um, such electrode hole has generally added that the width of polysilicon window is minimum altogether can only to 5 ~ 9um; In production technology, prior art have employed repeatedly photoetching and etching processing, because mask aligner itself exists the problem of alignment precision, within the width that the precision making the width W of the Window layer between polysilicon gate can only be limited to mask aligner can reach, as the width W of further reduction of device Window layer, much hidden danger will be brought to device, and cause device architecture to owe reasonable and affect running parameter and the reliability of device.
In production technology, above-mentioned patent have employed repeatedly photoetching and etching processing, because mask aligner itself exists the problem of alignment precision, within the width that the precision making the width W of the Window layer between polysilicon gate can only be limited to mask aligner can reach, as the width W of further reduction of device Window layer, much hidden danger will be brought to device, and cause device architecture to owe reasonable and affect running parameter and the reliability of device.
Summary of the invention
In order to overcome the problems referred to above of existing insulated gate bipolar transistor and manufacture method existence thereof, a kind of insulated gate bipolar transistor of existing special proposition and manufacture method thereof.
Concrete scheme of the present invention is as follows:
A kind of insulated gate bipolar transistor, comprise the first conductivity type substrate, the second conduction type base region is provided with in first interarea of the first conductivity type substrate, the second conductive-type moldeed depth diffusion region is provided with in second conduction type base region, be provided with transverse electric path unit first conduction type emitter region in second conduction type base region, described first conduction type emitter region comprises two first modules and two second units, two first modules are laterally connected with a second unit separately, and the second unit of two horizontally sets forms transverse electric path unit;
The first module of the first conduction type emitter region is separately positioned on the two ends of the second conductive-type moldeed depth diffusion region, first interarea of each first conduction type emitter region is provided with gate insulator, gate insulator is provided with polycrystalline silicon gate layer, polycrystalline silicon gate layer is provided with the second insulating barrier, the inner side of two groups of polycrystalline silicon gate layer and the second insulating barrier is provided with insulative sidewall, insulative sidewall lower end is arranged on gate insulator, be provided with the second conduction type collector region in second interarea of the first conductivity type substrate, the region between described two polycrystalline silicon gate layer is window region.
Further, also include front metal and back metal, front metal contacts the second conduction type base region and the first conduction type emitter region simultaneously, form the emitter of device, back metal contacts second conduction type collector region, form the collector electrode of device, polycrystalline silicon gate layer forms device grids together with the metal connecting it.
Further, described each first module is connected with two second units, and each second unit is connected with two first modules;
The same side of two first modules of described first conduction type emitter region forms region, two emitter regions, and between two first modules of same emitter region, the distance at edge is D1; Region, an each emitter region part is covered by gate insulator and described polycrystalline silicon gate layer;
Two second units of described first conduction type emitter region form region, two emitter regions, lay respectively at the both sides of window region, be horizontally installed between two first modules, between two emitter regions of described two second units, the distance at edge is D2, described region, an each emitter region part is covered by gate insulator and described polysilicon, another part region is not covered by gate insulator and described polycrystalline silicon gate layer, and D2 is less than D1.
Further, when described D2 is 0, the emitter region that two second units 142 of described first conduction type emitter region are respective is communicated with, whole window region is run through in described region, emitter region, both sides, region, described emitter region are covered by gate insulator and described polysilicon, and zone line is not covered by gate insulator and described polysilicon;
Further, described first conduction type is N-type, second conduction type is P type, described first conductivity type substrate is silicon substrate, first conductivity type substrate first interarea is front, second interarea is the back side, and the diffusion depth of described first conduction type emitter region is 0.2-0.5um, and each emitter region width is between 0.4-1um.
Further, described gate insulator is the silicon dioxide layer that thermal oxidation technology is formed, and the width of described insulative sidewall is less than the width of the first conduction type emitter region, and the width of described insulative sidewall is 0.1-1um, is highly between 0.7-2um.
Further, between described polycrystalline silicon gate layer, the width of window region is between 2-20um, and preferably condition is, between polycrystalline silicon gate layer, the width of window region is between 3-5um.
A manufacture method for insulated gate bipolar transistor, concrete manufacturing process is:
A. on the first interarea of the first conductivity type substrate, with the method growth gate insulator of thermal oxidation, LPCVD or PECVD;
B. on gate insulator by the method for LPCVD or PECVD, deposit polycrystalline polysilicon gate layer;
C. POCl3 is used to adulterate to polycrystalline silicon gate layer;
D. on polycrystalline silicon gate layer, the second insulating barrier is deposited by LPCVD or PECVD;
E. by photoetching, dry etching, the second insulating barrier and polycrystalline silicon gate layer are etched, form window region and polycrystalline silicon gate layer district;
F. in window region, inject the second conductive type impurity, carry out annealing, pushing away trap process, form the second conduction type base region;
G. form emitter pattern in the both sides of window region by photoetching, and in emitter pattern, inject the first conductive type impurity; Remove photoresist, inject the second conductive type impurity in the window, anneal, push away trap process, formed with transverse electric path first conduction type emitter region and the second conductive-type moldeed depth diffusion region.
H. on window region and polysilicon gate polar region, the 3rd insulating medium layer is deposited by LPCVD or PECVD, pass through dry etching, etch into the first conductivity type substrate surface, 3rd insulating barrier forms insulative sidewall by polycrystalline silicon gate layer place in window region, and the space formed described in self aligned electrode hole between insulative sidewall by sidewall is electrode hole;
I. inject the second conductive type impurity overleaf, annealing pushes away trap process and forms the second conduction type collector region, then makes metal electrode formation resulting devices at front and back by evaporating or sputtering.
Further, described second conduction type base region doping content is higher than the doping content of the first conductivity type substrate, described second conductive-type moldeed depth diffusion region doping content is greater than the doping content of the second conduction type base region, and is less than the concentration of the first conduction type emitter region; The degree of depth of described second conductive-type moldeed depth diffusion region is greater than the first conduction type emitter region; And spread the region be diffused into less than the second conduction type base region below polysilicon gate, the doping content of described second conduction type collector region is greater than the second conduction type base region, and be less than the first conduction type emitter region, first conduction type emitter region concentration is higher than the second conduction type base region, and diffusion depth is less than the second conduction type base region.
Further, described second insulating barrier is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any; Described insulative sidewall is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any.
The invention has the advantages that:
1, under the design reducing device window, due to the precision reason of mask aligner during electrode hole etching, sometimes electrode can not with emitter while contact, device half is caused to lose efficacy, the setting of second unit 142 emitter region of transverse direction of the present invention then can realize under any circumstance electrode and can contact with both sides emitter, which increases the reliability of device.
2, bipolar transistor of the present invention adopts insulative sidewall to be the self aligned technology of a kind of electrode hole, does not need photoetching, therefore, it is possible to the width of the window of polysilicon is reduced to 4um; So just can realize the figure more become more meticulous.
3, bipolar transistor of the present invention structurally adds insulative sidewall, electrode hole is aimed at completely, processing step can be reduced, because the existence of insulative sidewall, the width of window can be reduced, another effect that the width reducing window brings is the increase in the area ratio of polysilicon gate and polycrystalline window, and the effect brought like this is the conduction voltage drop Vce(sat of IGBT) can reduce.Due to the reduction of window region, but N+ emitter region needs photoetching to there is deviation of the alignment, so introduce a N+ emitter region unit gone across window, makes device be unlikely to have half to lose efficacy.
4, in operation, decrease the photoetching of electrode hole, add the deposition step of insulative sidewall, add the step that insulative sidewall is reduced in corrosion.Decreasing photo-mask process can make the width W of the Window layer between polysilicon gate reduce under the prerequisite ensureing device reliability as far as possible.Because the existence of insulative sidewall, electrode hole does not need photoetching, so can save the step of electrode hole photoetching needs.
5, D step for deposit the second insulating barrier by LPCVD or PECVD on polycrystalline silicon gate layer, is used for isolating polysilicon gate and emitter electrode.
6, H step defines insulative sidewall, forms electrode hole self-registered technology by insulative sidewall.
7, in I step due to the self-aligned mask effect of insulative sidewall, the width of the second conductive-type moldeed depth diffusion region is less than the width of existing device, reduces cut-in voltage Vth.
Accompanying drawing explanation
Fig. 1 is the three-dimension integrally design drawing of this patent device.
Fig. 2 is the two-dimensional cross sectional design drawing of existing technique.
Fig. 3 is sectional view of the present invention.
Fig. 4 is two second units 142 of the present invention first conduction type emitter region structural representations when separating.
Structural representation when Fig. 5 is two second unit 142 cross connection of the present invention first conduction type emitter region.
The manufacture craft of Fig. 6 ~ 16 respective devices:
Fig. 6 is silicon substrate.
The corresponding technique A of Fig. 7, B, C, D.
The corresponding technique E of Fig. 8.
The corresponding technique F of Fig. 9.
The device with the first emitter unit that the corresponding technique G of Figure 10 is formed.
The device with the second emitter unit that Figure 11,12 corresponding technique G are formed.
The corresponding technique H of Figure 13.
The dark diffusion region that Figure 14,15 corresponding technique G are formed.
The corresponding technique I of Figure 16.
110: the first conductivity type substrate in accompanying drawing; 120: the second conduction type base region; 130: the second conductive-type moldeed depth diffusion regions; 140: the first conduction type emitter regions; 141: first module; 142: second unit 142; 150: the second conduction type collector regions; 160: gate insulator; 170: polysilicon gate; 180: the second insulating barriers; 190: insulative sidewall.
The width of polysilicon gate is L, and the window region width between polysilicon gate is W; Two emitter regions of the first conduction type emitter region first module be spaced apart D1; Spacing distance between two emitter regions that two second units 142 are formed is D2.
Embodiment
Embodiment 1
As shown in Figure 1, a kind of insulated gate bipolar transistor, comprise the first conductivity type substrate 110, the second conduction type base region 120 is provided with in first interarea of the first conductivity type substrate 110, the second conductive-type moldeed depth diffusion region 130 is provided with in second conduction type base region 120, be provided with in second conduction type base region 120 with transverse electric path unit first conduction type emitter region 140, described first conduction type emitter region 140 comprises two first modules 141 and two second units 142, two first modules 141 are longitudinally arranged side by side, two second units 142 are laterally connected with a second unit 142 separately, the second unit 142 of two horizontally sets forms transverse electric path unit,
The first module 141 of the first conduction type emitter region 140 is separately positioned on the two ends of the second conductive-type moldeed depth diffusion region 130, first interarea of each first conduction type emitter region 140 is provided with gate insulator 160, gate insulator 160 is provided with polycrystalline silicon gate layer 170, polycrystalline silicon gate layer 170 is provided with the second insulating barrier 180, the inner side of two groups of polycrystalline silicon gate layer 170 and the second insulating barrier 180 is provided with insulative sidewall 190, insulative sidewall 190 lower end is arranged on gate insulator 160, the second conduction type collector region 150 is provided with in second interarea of the first conductivity type substrate 110, region between described two polycrystalline silicon gate layer 170 is window region.
Embodiment 2
As shown in Figure 1, a kind of insulated gate bipolar transistor, comprise the first conductivity type substrate 110, the second conduction type base region 120 is provided with in first interarea of the first conductivity type substrate 110, the second conductive-type moldeed depth diffusion region 130 is provided with in second conduction type base region 120, be provided with in second conduction type base region 120 with transverse electric path unit first conduction type emitter region 140, described first conduction type emitter region 140 comprises two first modules 141 and two second units 142, two first modules 141 are longitudinally arranged side by side, two second units 142 are laterally connected with a second unit 142 separately, the second unit 142 of two horizontally sets forms transverse electric path unit, also include front metal and back metal, front metal contacts the second conduction type base region 120 and the first conduction type emitter region 140 simultaneously, form the emitter of device, back metal contacts second conduction type collector region 150, form the collector electrode of device, polycrystalline silicon gate layer 170 forms device grids together with the metal connecting it.
The first module 141 of the first conduction type emitter region 140 is separately positioned on the two ends of the second conductive-type moldeed depth diffusion region 130, first interarea of each first conduction type emitter region 140 is provided with gate insulator 160, gate insulator 160 is provided with polycrystalline silicon gate layer 170, polycrystalline silicon gate layer 170 is provided with the second insulating barrier 180, the inner side of two groups of polycrystalline silicon gate layer 170 and the second insulating barrier 180 is provided with insulative sidewall 190, insulative sidewall 190 lower end is arranged on gate insulator 160, the second conduction type collector region 150 is provided with in second interarea of the first conductivity type substrate 110, region between described two polycrystalline silicon gate layer 170 is window region.
Described each first module 141 is connected with two second units 142, and each second unit 142 is connected with two first modules 141; The same side of two first modules 141 of described first conduction type emitter region 140 forms region, two emitter regions, and between two first modules 141 of same emitter region, the distance at edge is D1; Region, an each emitter region part is covered by gate insulator 160 and described polycrystalline silicon gate layer 170.Two second units 142 of the first conduction type emitter region 140 form region, two emitter regions, lay respectively at the both sides of window region, be horizontally installed between two first modules 141, between two emitter regions of described two second units 142, the distance at edge is D2, described region, an each emitter region part is covered by gate insulator and described polysilicon, another part region is not covered by gate insulator 160 and described polycrystalline silicon gate layer 170, and D2 is less than D1.
If reduce window region, so likely make two emitter regions one of them can not cause device to have half to lose efficacy with electrode contact when photoetching is carried out in N+ emitter region, so the present invention is by the first conduction type emitter region 140 shown in Fig. 1, namely in Fig. 1, the structure of the part of black is improved, its shape approximation is H type, the lateral part of its centre is exactly our transverse electric path unit, i.e. second unit 142.
First conduction type is N-type, second conduction type is P type, described first conductivity type substrate 110 is silicon substrate, first conductivity type substrate 110 first interarea is front, second interarea is the back side, the diffusion depth of described first conduction type emitter region 140 is 0.5um, and each emitter region width is between 1um.The silicon dioxide layer that described gate insulator 160 is formed for thermal oxidation technology, the width of described insulative sidewall 190 is less than the width of the first conduction type emitter region 140, and the width of described insulative sidewall 190 is 1um, is highly between 2um.Between described polycrystalline silicon gate layer, the width of window region is between 20um.Between polycrystalline silicon gate layer, the width of window region is between 5um.
Embodiment 3
As shown in Figure 1, a kind of insulated gate bipolar transistor, comprise the first conductivity type substrate 110, the second conduction type base region 120 is provided with in first interarea of the first conductivity type substrate 110, the second conductive-type moldeed depth diffusion region 130 is provided with in second conduction type base region 120, be provided with in second conduction type base region 120 with transverse electric path unit first conduction type emitter region 140, described first conduction type emitter region 140 comprises two first modules 141 and two second units 142, two first modules 141 are longitudinally arranged side by side, two second units 142 are laterally connected with a second unit 142 separately, the second unit 142 of two horizontally sets forms transverse electric path unit, also include front metal and back metal, front metal contacts the second conduction type base region 120 and the first conduction type emitter region 140 simultaneously, form the emitter of device, back metal contacts second conduction type collector region 150, form the collector electrode of device, polycrystalline silicon gate layer 170 forms device grids together with the metal connecting it.
The first module 141 of the first conduction type emitter region 140 is separately positioned on the two ends of the second conductive-type moldeed depth diffusion region 130, first interarea of each first conduction type emitter region 140 is provided with gate insulator 160, gate insulator 160 is provided with polycrystalline silicon gate layer 170, polycrystalline silicon gate layer 170 is provided with the second insulating barrier 180, the inner side of two groups of polycrystalline silicon gate layer 170 and the second insulating barrier 180 is provided with insulative sidewall 190, insulative sidewall 190 lower end is arranged on gate insulator 160, the second conduction type collector region 150 is provided with in second interarea of the first conductivity type substrate 110, region between described two polycrystalline silicon gate layer 170 is window region.
Described each first module 141 is connected with two second units 142, and each second unit 142 is connected with two first modules 141; The same side of two first modules 141 of described first conduction type emitter region 140 forms region, two emitter regions, and between two first modules 141 of same emitter region, the distance at edge is D1; Region, an each emitter region part is covered by gate insulator 160 and described polycrystalline silicon gate layer 170.Two second units 142 of the first conduction type emitter region 140 form region, two emitter regions, lay respectively at the both sides of window region, be horizontally installed between two first modules 141, between two emitter regions of described two second units 142, the distance at edge is D2, described region, an each emitter region part is covered by gate insulator and described polysilicon, another part region is not covered by gate insulator 160 and described polycrystalline silicon gate layer 170, and D2 is less than D1.When described D2 is 0, the emitter region that two second units 142 of described first conduction type emitter region 140 are respective is communicated with, whole window region is run through in described region, emitter region, both sides, region, described emitter region are covered by gate insulator and described polysilicon, and zone line is not covered by gate insulator and described polysilicon.
The first module 141 of the present invention first emitter region can be identical with traditional devices, suppose that the distance of the unit of two emitter regions is D1, the distance D2 of two emitter region unit of second unit 142 is less than first module 141 two emitter region cell distance D1, when two emitter region spacing D2 of second unit 142 little to 0 time, two emitter regions of second unit 142 are just linked to be an emitter region, run through whole window region.
First conduction type is N-type, second conduction type is P type, described first conductivity type substrate 110 is silicon substrate, first conductivity type substrate 110 first interarea is front, second interarea is the back side, the diffusion depth of described first conduction type emitter region 140 is 0.2um, and each emitter region width is between 0.4um.The silicon dioxide layer that described gate insulator 160 is formed for thermal oxidation technology, the width of described insulative sidewall 190 is less than the width of the first conduction type emitter region 140, and the width of described insulative sidewall 190 is 0.1um, is highly between 0.7um.Between described polycrystalline silicon gate layer, the width of window region is between 2um.Between polycrystalline silicon gate layer, the width of window region is between 3um.
Embodiment 4
A manufacture method for insulated gate bipolar transistor, concrete manufacturing process is:
A. on the first interarea of the first conductivity type substrate 110, with the method growth gate insulator 160 of thermal oxidation, LPCVD or PECVD;
B. on gate insulator 160 by the method for LPCVD or PECVD, deposit polycrystalline polysilicon gate layer 170;
C. POCl3 is used to adulterate to polycrystalline silicon gate layer 170;
D. on polycrystalline silicon gate layer 170, the second insulating barrier 180 is deposited by LPCVD or PECVD;
E. by photoetching, dry etching, the second insulating barrier 180 and polycrystalline silicon gate layer 170 are etched, form window region and polycrystalline silicon gate layer 170 district;
F. in window region, inject the second conductive type impurity, carry out annealing, pushing away trap process, form the second conduction type base region 120;
G. form emitter pattern in the both sides of window region by photoetching, and in emitter pattern, inject the first conductive type impurity; Remove photoresist, inject the second conductive type impurity in the window, anneal, push away trap process, formed with transverse electric path first conduction type emitter region 140 and the second conductive-type moldeed depth diffusion region 130.
H. on window region and polysilicon gate polar region, the 3rd insulating medium layer is deposited by LPCVD or PECVD, pass through dry etching, etch into the first conductivity type substrate 110 surface, 3rd insulating barrier forms insulative sidewall 190 by polycrystalline silicon gate layer 170 place in window region, and the space formed described in self aligned electrode hole between insulative sidewall by sidewall is electrode hole;
I. inject the second conductive type impurity overleaf, annealing pushes away trap process and forms the second conduction type collector region 150, then makes metal electrode formation resulting devices at front and back by evaporating or sputtering.
Embodiment 5
A manufacture method for insulated gate bipolar transistor, concrete manufacturing process is:
A. on the first interarea of the first conductivity type substrate 110, with the method growth gate insulator 160 of thermal oxidation, LPCVD or PECVD;
B. on gate insulator 160 by the method for LPCVD or PECVD, deposit polycrystalline polysilicon gate layer 170;
C. POCl3 is used to adulterate to polycrystalline silicon gate layer 170;
D. on polycrystalline silicon gate layer 170, the second insulating barrier 180 is deposited by LPCVD or PECVD;
E. by photoetching, dry etching, the second insulating barrier 180 and polycrystalline silicon gate layer 170 are etched, form window region and polycrystalline silicon gate layer 170 district;
F. in window region, inject the second conductive type impurity, carry out annealing, pushing away trap process, form the second conduction type base region 120;
G. form emitter pattern in the both sides of window region by photoetching, and in emitter pattern, inject the first conductive type impurity; Remove photoresist, inject the second conductive type impurity in the window, anneal, push away trap process, formed with transverse electric path first conduction type emitter region 140 and the second conductive-type moldeed depth diffusion region 130.
H. on window region and polysilicon gate polar region, the 3rd insulating medium layer is deposited by LPCVD or PECVD, pass through dry etching, etch into the first conductivity type substrate 110 surface, 3rd insulating barrier forms insulative sidewall 190 by polycrystalline silicon gate layer 170 place in window region, and the space formed described in self aligned electrode hole between insulative sidewall by sidewall is electrode hole;
I. inject the second conductive type impurity overleaf, annealing pushes away trap process and forms the second conduction type collector region 150, then makes metal electrode formation resulting devices at front and back by evaporating or sputtering.
Described second conduction type base region 120 doping content is higher than the doping content of the first conductivity type substrate 110, described second conductive-type moldeed depth diffusion region 130 doping content is greater than the doping content of the second conduction type base region 120, and is less than the concentration of the first conduction type emitter region 140; The degree of depth of described second conductive-type moldeed depth diffusion region 130 is greater than the first conduction type emitter region 140; And spread the region be diffused into less than the second conduction type base region 120 below polysilicon gate, the doping content of described second conduction type collector region 150 is greater than the second conduction type base region 120, and be less than the first conduction type emitter region 140, first conduction type emitter region 140 concentration is higher than the second conduction type base region 120, and diffusion depth is less than the second conduction type base region 120.
Described second insulating barrier 180 is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any; Described insulative sidewall 190 is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any.
Embodiment 6
As shown in Figure 1, it is a kind of igbt device with lateral-emitter unit, comprise the first conductivity type substrate 110, the second conduction type base region 120 is provided with in first interarea of the first conductivity type substrate 110, the second conductive-type moldeed depth diffusion region 130 is provided with in second conduction type base region 120, first conduction type emitter region 140, be arranged in the second conductive-type moldeed depth diffusion region 130, first interarea of the first conductivity type substrate 110 is provided with gate insulator 160, gate insulator 160 is provided with polycrystalline silicon grid layer 170, polycrystalline silicon grid layer 170 is provided with the second insulating barrier 180, polycrystalline silicon grid layer 170 both sides are provided with insulative sidewall 190, the second conduction type collector region 150 is provided with in second interarea of the first conductivity type substrate.
Region between described polysilicon is window region.
Described first conduction type emitter region first module 141 comprises two discrete emitter regions, and its doping content is higher than the second conduction type base region 120; A part for each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region, and the spacing of two emitter regions is D1.
Described first conduction type emitter region second unit 142 comprises a connected emitter region, and its doping content is higher than the second conduction type base region 120; A part for each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region.
Described first conduction type emitter region second unit 142,142 comprises two discrete emitter regions, and its doping content is higher than the second conduction type base region 120; A part for each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region, and the spacing of two emitter regions is D2, D2<D1.
First conduction type is N-type, and the second conduction type is P type.First conductivity type substrate is silicon substrate 110, and the first conductivity type substrate first interarea is front, and the second interarea is the back side.
Second conduction type base region 120 doping content is higher than the doping content of the first conductivity type substrate 110;
Second conductive-type moldeed depth diffusion region 130 doping content is greater than the doping content of the second conduction type base region 110, and is less than the concentration of the first conduction type emitter region 140; The degree of depth of the second conductive-type moldeed depth diffusion region 130 is greater than the first conduction type emitter region 140; And spread the region be diffused into less than the second conduction type base region 120 below polysilicon gate 160;
The diffusion depth of the first conduction type emitter region 140 is 0.2 ~ 0.5um; Each emitter region width is between 0.2 ~ 1um, and left and right each one is all the same width.
The doping content of the second conduction type collector region 150 is greater than the second conduction type base region 110.
Concrete, the first conductivity type substrate 110 doping content is 2e13 ~ 2e14 ㎝-3, the second conduction type base region 120 doping content 1e17 ~ 5e17 ㎝-3, the second conductive-type moldeed depth diffusion region 130 doping content is 1e19 ~ 3e19 ㎝-3; First conduction type emitter region 140 doping content is 1.5e20 ~ 2.5e20 ㎝-3; Second conduction type collector electrode 150 doping content is 1e17 ~ 1e19 ㎝-3.
The silicon dioxide layer that described gate insulator 160 is formed for thermal oxidation technology, its thickness is 0.03 ~ 0.2um.
Described polycrystalline silicon grid layer 170 is the polysilicon layer of LPCVD or PECVD deposition, and the width of polysilicon layer is at 8 ~ 20um, and thickness is at 0.4 ~ 1um; Part between polycrystalline silicon grid layer forms window region, and the width of window region is at 2 ~ 8um;
Described second insulating barrier 180 is the TEOS silicon dioxide by LPCVD or PECVD deposit, phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG) or silicon nitride (SiNx), and their combination in any, and its thickness is 0.5 ~ 2um;
Described insulative sidewall 190 is the TEOS silicon dioxide by LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG, silicon nitride SiNx, the width of insulative sidewall 190 is less than the width of the first conduction type emitter region 140, the width of described insulative sidewall is between 0.1-1um, and height is between 0.7-2um.The shape of insulative sidewall is the shape in Fig. 1, also can be other shapes such as triangle.
A kind of manufacturing process of igbt device of fully self aligned is as shown in figs. 6 to 16:
A. on the first interarea of the first conductivity type substrate, with the method growth gate insulator of thermal oxidation, LPCVD or PECVD;
B. on gate insulator by the method for LPCVD or PECVD, deposit polycrystalline silicon gate layer.
C. use POCl3 to adulterate to polycrystalline silicon grid layer, or just polysilicon is adulterated when step B.
D. on polycrystalline silicon grid layer, the second insulating barrier is deposited by LPCVD or PECVD.
E. by photoetching, dry etching, the second insulating barrier and polycrystalline silicon grid layer are etched, form window region (width is W) and polycrystalline silicon grid layer district (width is L).
F. inject the second conductive type impurity in the window, anneal, push away trap process, the second conduction type base region.The impurity injected in step F is boron, and inject metering 1e13 ~ 2e14 cm-2, desirable is chosen as 6e13 ~ 1.5e14cm-2, and Implantation Energy is 10 ~ 200KeV, and annealing temperature is 900 DEG C ~ 1300 DEG C, and the time is 10 ~ 200min.
G. emitter pattern is formed in the both sides of window region by photoetching, and at emitter pattern, middle injection first conductive type impurity; Remove photoresist, anneal, push away trap process, formed with transverse electric path first conduction type emitter region (140) and the second conductive-type moldeed depth diffusion region (130).The impurity injected in step G is phosphorus or arsenic, and inject metering 2e15 ~ 2e16 cm-2, desirable is chosen as 1e16 ~ 2e16cm-2, and Implantation Energy is 10 ~ 200KeV, and annealing temperature is 900 DEG C ~ 1100 DEG C, and the time is 5 ~ 200min.
H. on window region and polycrystalline silicon grid layer district, deposit the 3rd insulating medium layer by LPCVD or PECVD, by dry etching, etch into the first conductivity type substrate surface, in window region, form insulative sidewall by polycrystalline silicon grid layer place.
I. be mask with insulative sidewall, inject the second conductive type impurity, anneal, push away trap and form the second conductive-type moldeed depth diffusion region.The impurity injected in step I is boron, and inject metering 1e15 ~ 2e15 cm-2, desirable is chosen as 3e15 ~ 1e16cm-2, and Implantation Energy is 10 ~ 200KeV, and annealing temperature is 900 DEG C ~ 1000 DEG C, and the time is 10 ~ 200min.Form structure as shown in the figure.
J. inject the second conductive type impurity overleaf, annealing pushes away trap process and forms collector electrode; Metal electrode formation IGBT device is made by evaporating or sputtering again at front and back.The impurity injected in step L is boron, and inject metering 1e13 ~ 1e16 cm-2, desirable is chosen as 1e13 ~ 1e15cm-2, and Implantation Energy is 10 ~ 200KeV, and annealing temperature is 300 DEG C ~ 900 DEG C, and the time is 100 ~ 1000min.
This patent only relates to the front technique of igbt, the back side technology for different: field cut-off type igbt, inverse conductivity type igbt and other back side technology, applicable equally.
Embodiment 7
As shown in Figure 1, it is a kind of igbt device with lateral-emitter unit, comprise the first conductivity type substrate 110, the second conduction type base region 120 is provided with in first interarea of the first conductivity type substrate 110, the second conductive-type moldeed depth diffusion region 130 is provided with in second conduction type base region 120, first conduction type emitter region 140, be arranged in the second conductive-type moldeed depth diffusion region 130, first interarea of the first conductivity type substrate 110 is provided with gate insulator 160, gate insulator 160 is provided with polycrystalline silicon grid layer 170, polycrystalline silicon grid layer 170 is provided with the second insulating barrier 180, polycrystalline silicon grid layer 170 both sides are provided with insulative sidewall 190, the second conduction type collector region 150 is provided with in second interarea of the first conductivity type substrate.
Region between described polysilicon is window region.
Described first conduction type emitter region first module 141 comprises two discrete emitter regions, and its doping content is higher than the second conduction type base region 120; A part for each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region, and the spacing of two emitter regions is D1.
Described first conduction type emitter region second unit 142142 comprises a connected emitter region, and its doping content is higher than the second conduction type base region 120; A part for each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region.
Described first conduction type emitter region second unit 142142 comprises two discrete emitter regions, and its doping content is higher than the second conduction type base region 120; A part for each emitter region is covered by polycrystalline silicon grid layer 170, and another part is positioned at window region, and the spacing of two emitter regions is D2, D2<D1.
First conduction type is N-type, and the second conduction type is P type.First conductivity type substrate is silicon substrate 110, and the first conductivity type substrate first interarea is front, and the second interarea is the back side.
Second conduction type base region 120 doping content is higher than the doping content of the first conductivity type substrate 110;
Second conductive-type moldeed depth diffusion region 130 doping content is greater than the doping content of the second conduction type base region 110, and is less than the concentration of the first conduction type emitter region 140; The degree of depth of the second conductive-type moldeed depth diffusion region 130 is greater than the first conduction type emitter region 140; And spread the region be diffused into less than the second conduction type base region 120 below polysilicon gate 160;
The diffusion depth of the first conduction type emitter region 140 is 0.2 ~ 0.5um; Each emitter region width is between 0.2 ~ 1um, and left and right each one is all the same width.
The doping content of the second conduction type collector region 150 is greater than the second conduction type base region 110.
Concrete, the first conductivity type substrate 110 doping content is 2e13 ~ 2e14 ㎝-3, the second conduction type base region 120 doping content 1e17 ~ 5e17 ㎝-3, the second conductive-type moldeed depth diffusion region 130 doping content is 1e19-3e19 ㎝-3; First conduction type emitter region 140 doping content is 1.5e20 ~ 2.5e20 ㎝-3; Second conduction type collector electrode 150 doping content is 1e17 ~ 1e19 ㎝-3.
The silicon dioxide layer that described gate insulator 160 is formed for thermal oxidation technology, its thickness is 0.03 ~ 0.2um.
Described polycrystalline silicon grid layer 170 is the polysilicon layer of LPCVD or PECVD deposition, and the width of polysilicon layer is at 8 ~ 20um, and thickness is at 0.4 ~ 1um; Part between polycrystalline silicon grid layer forms window region, and the width of window region is at 2 ~ 8um;
Described second insulating barrier 180 is the TEOS silicon dioxide by LPCVD or PECVD deposit, phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG) or silicon nitride (SiNx), and their combination in any, and its thickness is 0.5 ~ 2um;
Described insulative sidewall 190 is the TEOS silicon dioxide by LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG, silicon nitride SiNx, the width of insulative sidewall 190 is less than the width of the first conduction type emitter region 140, the width of described insulative sidewall is between 0.1-1um, and height is between 0.7-2um.The shape of insulative sidewall is the shape in Fig. 1, also can be other shapes such as triangle.
A kind of manufacturing process of igbt device of fully self aligned is as shown in figs. 6 to 16:
A. on the first interarea of the first conductivity type substrate, with the method growth gate insulator of thermal oxidation, LPCVD or PECVD;
B. on gate insulator by the method for LPCVD or PECVD, deposit polycrystalline silicon gate layer.
C. use POCl3 to adulterate to polycrystalline silicon grid layer, or just polysilicon is adulterated when step B.
D. on polycrystalline silicon grid layer, the second insulating barrier is deposited by LPCVD or PECVD.
E. by photoetching, dry etching, the second insulating barrier and polycrystalline silicon grid layer are etched, form window region (width is W) and polycrystalline silicon grid layer district (width is L).
F. inject the second conductive type impurity in the window, anneal, push away trap process, the second conduction type base region.The impurity injected in step F is boron, and inject metering 1e13 ~ 2e14 cm-2, desirable is chosen as 6e13 ~ 1.5e14cm-2, and Implantation Energy is 10 ~ 200KeV, and annealing temperature is 900 DEG C ~ 1300 DEG C, and the time is 10 ~ 200min.
G. emitter pattern is formed in the both sides of window region by photoetching, and at emitter pattern, middle injection first conductive type impurity, the impurity injected is phosphorus or arsenic, and inject metering 2e15 ~ 2e16 cm-2, desirable is chosen as 1e16 ~ 2e16cm-2, Implantation Energy is 10 ~ 200KeV; Remove photoresist, inject the second conductive type impurity, the impurity of injection is boron, and inject metering 1e15 ~ 2e15 cm-2, desirable is chosen as 3e15 ~ 1e16cm-2, and Implantation Energy is 10 ~ 200KeV.Formed with transverse electric path first conduction type emitter region (140,141,142) and the second conductive-type moldeed depth diffusion region (130).Annealing temperature is 900 DEG C ~ 1100 DEG C, and the time is 5 ~ 200min.
H. on window region and polycrystalline silicon grid layer district, deposit the 3rd insulating medium layer by LPCVD or PECVD, by dry etching, etch into the first conductivity type substrate surface, in window region, form insulative sidewall by polycrystalline silicon grid layer place.Form device architecture as shown in the figure.
I. inject the second conductive type impurity overleaf, annealing pushes away trap process and forms collector electrode; Metal electrode formation IGBT device is made by evaporating or sputtering again at front and back.The impurity injected in step L is boron, and inject metering 1e13 ~ 1e16 cm-2, desirable is chosen as 1e13 ~ 1e15cm-2, and Implantation Energy is 10 ~ 200KeV, and annealing temperature is 300 DEG C ~ 900 DEG C, and the time is 100 ~ 1000min.
This patent only relates to the front technique of igbt, the back side technology for different: field cut-off type igbt, inverse conductivity type igbt and other back side technology, applicable equally.
Claims (11)
1. an insulated gate bipolar transistor, it is characterized in that: comprise the first conductivity type substrate (110), the second conduction type base region (120) is provided with in first interarea of the first conductivity type substrate (110), the second conductive-type moldeed depth diffusion region (130) is provided with in second conduction type base region (120), be provided with in second conduction type base region (120) with transverse electric path unit first conduction type emitter region (140), described first conduction type emitter region (140) comprises two first modules (141) and two second units (142), two first modules (141) are laterally connected with a second unit (142) separately, the second unit (142) of two horizontally sets forms transverse electric path unit,
The first module (141) of the first conduction type emitter region (140) is separately positioned on the two ends of the second conductive-type moldeed depth diffusion region (130), first interarea of each first conduction type emitter region (140) is provided with gate insulator (160), gate insulator (160) is provided with polycrystalline silicon gate layer (170), polycrystalline silicon gate layer (170) is provided with the second insulating barrier (180), the inner side of two groups of polycrystalline silicon gate layer (170) and the second insulating barrier (180) is provided with insulative sidewall (190), insulative sidewall (190) lower end is arranged on gate insulator (160), the second conduction type collector region (150) is provided with in second interarea of the first conductivity type substrate (110), region between described two polycrystalline silicon gate layer (170) is window region.
2. a kind of insulated gate bipolar transistor according to claim 1, it is characterized in that: also include front metal and back metal, front metal contacts the second conduction type base region (120) and the first conduction type emitter region (140) simultaneously, form the emitter of device, back metal contacts second conduction type collector region (150), form the collector electrode of device, polycrystalline silicon gate layer (170) forms device grids together with the metal connecting it.
3. a kind of insulated gate bipolar transistor according to claim 1, is characterized in that: described each first module (141) is connected with two second units (142), and each second unit (142) is connected with two first modules (141);
The same side of two first modules (141) of described first conduction type emitter region (140) forms region, two emitter regions, and between two first modules (141) of same emitter region, the distance at edge is D1; Region, an each emitter region part is covered by gate insulator (160) and described polycrystalline silicon gate layer (170);
Two second units (142) of described first conduction type emitter region (140) form region, two emitter regions, lay respectively at the both sides of window region, be horizontally installed between two first modules (141), between two emitter regions of described two second units (142), the distance at edge is D2, described region, an each emitter region part is covered by gate insulator and described polysilicon, another part region is not covered by gate insulator (160) and described polycrystalline silicon gate layer (170), and D2 is less than D1.
4. a kind of insulated gate bipolar transistor according to claim 3, it is characterized in that: when described D2 is 0, two second unit 142(142 of described first conduction type emitter region (140)) respective emitter region is communicated with, whole window region is run through in described region, emitter region, both sides, region, described emitter region are covered by gate insulator and described polysilicon, and zone line is not covered by gate insulator and described polysilicon.
5. a kind of insulated gate bipolar transistor according to claim 3 or 4, it is characterized in that: described first conduction type is N-type, second conduction type is P type, described first conductivity type substrate (110) is silicon substrate, first conductivity type substrate (110) first interarea is front, second interarea is the back side, and the diffusion depth of described first conduction type emitter region (140) is 0.2-0.5um, and each emitter region width is between 0.4-1um.
6. a kind of insulated gate bipolar transistor according to claim 5, it is characterized in that: the silicon dioxide layer that described gate insulator (160) is formed for thermal oxidation technology, the width of described insulative sidewall (190) is less than the width of the first conduction type emitter region (140), the width of described insulative sidewall (190) is 0.1-1um, is highly between 0.7-2um.
7. a kind of insulated gate bipolar transistor according to claim 6, is characterized in that: between described polycrystalline silicon gate layer, the width of window region is between 2-20um.
8. a kind of insulated gate bipolar transistor according to claim 7, is characterized in that: between polycrystalline silicon gate layer, the width of window region is between 3-5um.
9. a manufacture method for insulated gate bipolar transistor, is characterized in that: concrete manufacturing process is:
A. on the first interarea of the first conductivity type substrate (110), by method growth gate insulator (160) of thermal oxidation, LPCVD or PECVD;
B. on gate insulator (160) by the method for LPCVD or PECVD, deposit polycrystalline polysilicon gate layer (170);
C. POCl3 is used to adulterate to polycrystalline silicon gate layer (170);
D. on polycrystalline silicon gate layer (170), the second insulating barrier (180) is deposited by LPCVD or PECVD;
E. by photoetching, dry etching, the second insulating barrier (180) and polycrystalline silicon gate layer (170) are etched, form window region and polycrystalline silicon gate layer (170) district;
F. in window region, inject the second conductive type impurity, carry out annealing, pushing away trap process, form the second conduction type base region (120);
G. form emitter pattern in the both sides of window region by photoetching, and in emitter pattern, inject the first conductive type impurity; Remove photoresist, inject the second conductive type impurity in the window, anneal, push away trap process, formed with transverse electric path first conduction type emitter region (140) and the second conductive-type moldeed depth diffusion region (130);
H. on window region and polysilicon gate polar region, the 3rd insulating medium layer is deposited by LPCVD or PECVD, pass through dry etching, etch into the first conductivity type substrate (110) surface, 3rd insulating barrier forms insulative sidewall (190) by polycrystalline silicon gate layer (170) place in window region, and the space formed described in self aligned electrode hole between insulative sidewall by sidewall is electrode hole;
I. inject the second conductive type impurity overleaf, annealing pushes away trap process and forms the second conduction type collector region (150), then makes metal electrode formation resulting devices at front and back by evaporating or sputtering.
10. the manufacture method of a kind of insulated gate bipolar transistor according to claim 9, it is characterized in that: described second conduction type base region (120) doping content is higher than the doping content of the first conductivity type substrate (110), described second conductive-type moldeed depth diffusion region (130) doping content is greater than the doping content of the second conduction type base region (120), and is less than the concentration of the first conduction type emitter region (140); The degree of depth of described second conductive-type moldeed depth diffusion region (130) is greater than the first conduction type emitter region (140); And spread the region be diffused into less than the second conduction type base region (120) below polysilicon gate, the doping content of described second conduction type collector region (150) is greater than the second conduction type base region (120), and be less than the first conduction type emitter region (140), first conduction type emitter region (140) concentration is higher than the second conduction type base region (120), and diffusion depth is less than the second conduction type base region (120).
The manufacture method of 11. a kind of insulated gate bipolar transistors according to claim 9, it is characterized in that: described second insulating barrier (180) is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any; Described insulative sidewall (190) is by the TEOS silicon dioxide of LPCVD or PECVD deposit, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG or silicon nitride SiNx, and their combination in any.
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