CN104253045A - VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor) device and manufacturing method thereof - Google Patents
VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor) device and manufacturing method thereof Download PDFInfo
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- CN104253045A CN104253045A CN201310256294.XA CN201310256294A CN104253045A CN 104253045 A CN104253045 A CN 104253045A CN 201310256294 A CN201310256294 A CN 201310256294A CN 104253045 A CN104253045 A CN 104253045A
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- well region
- gate polysilicon
- polysilicon layer
- epitaxial loayer
- oxic horizon
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 title abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 23
- 238000001259 photo etching Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- -1 phosphonium ion Chemical class 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910000906 Bronze Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000010974 bronze Substances 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- DXBNFOZPQUKUHW-UHFFFAOYSA-N [Si](=O)=O.[P] Chemical compound [Si](=O)=O.[P] DXBNFOZPQUKUHW-UHFFFAOYSA-N 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention provides a VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor) device and a manufacturing method thereof. Polycrystalline silicon between two channel regions in an existing VDMOS device is removed by means of twice polycrystalline silicon etching, so that the aim of reducing gate-drain capacitance is fulfilled. Moreover, the injection amount of N<+> is increased, and the junction depth of a P<+> trap is pushed, so that P<+> trap regions and N<+> trap regions are of the same ionized impurity concentration, and the aim of fully consuming the N<+> trap regions in case of reversal of biasing is fulfilled. Since the injection amount of the N<+> is increased, RJ and RD are reduced, and the starting speed of the VDMOS device is increased.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly relate to a kind of VDMOS device and manufacture method thereof.
Background technology
At present, the application of power device widely, because the operating frequency specific power bipolar transistor of power MOS transistor is high, and it is voltage control device, its drive current is smaller, its drive circuit specific power bipolar transistor is simple, and thus make power MOS transistor, particularly VDMOS is widely used more.The transistor of Metal-oxide-semicondutor (Metal-Oxide-Semiconductor) structure is called for short MOS transistor.Form raceway groove by twice diffusion junction depth difference, bilateral diffusion MOS is called for short DMOS.The DMOS that drain electrode (Drain) is drawn from the back side is exactly VDMOS.
Along with complete machine is to miniaturization, require that the power output of VDMOS device is larger, but the power consumption of himself is less, this just requires that the conducting resistance of VDMOS device is less.Therefore, the conducting resistance how reducing VDMOS device has become industry emphasis research topic.
Summary of the invention
The invention provides a kind of VDMOS device and manufacture method thereof, realize the opening speed of raising VDMOS device and reduce its conducting resistance.
VDMOS device provided by the invention, comprising:
Substrate, and the epitaxial loayer being positioned at described substrate face;
Be positioned at the grid structure of described epi-layer surface, described grid structure comprises grid oxic horizon and is positioned at the gate polysilicon layer on described grid oxic horizon surface, and described gate polysilicon layer only covers described grid oxic horizon two ends; The surface do not covered by described gate polysilicon layer in the middle part of described gate polysilicon layer and described grid oxic horizon is provided with middle dielectric layer;
Be positioned at the P+ well region of epitaxial loayer described in described grid structure both sides, and be positioned at the N+ well region of described epitaxial loayer below described grid structure, mixing in described N+ well region has ionized impurity;
Be positioned at the drain metal layer of described substrate back.
The manufacture method of VDMOS device provided by the invention, comprising:
There is provided a substrate, described substrate comprises front and back, and is positioned at the epitaxial loayer of described substrate face;
Grid oxic horizon is formed in described epi-layer surface, and be positioned at the gate polysilicon layer on described grid oxic horizon surface, first time photoetching and etching are carried out to described gate polysilicon layer, and carry out N+ injection, in described epitaxial loayer, do not formed N+ district by the position that described gate polysilicon layer covers;
Second time photoetching and etching are carried out to described gate polysilicon layer, exposes the epitaxial loayer covered by described gate polysilicon layer between adjacent N+ district, and carry out P+ injection, in described epitaxial loayer, form P+ district between adjacent N+ district;
Knot depths reason is carried out to described N+ district and described P+ district simultaneously, forms N+ well region and P+ well region; Photoetching and etching are carried out to described P+ well region, and carries out ion implantation; Deposit middle dielectric layer, forms the grid structure being positioned at described epi-layer surface; Described grid structure comprises grid oxic horizon and is positioned at the gate polysilicon layer on described grid oxic horizon surface, and described gate polysilicon layer only covers described grid oxic horizon two ends; The surface do not covered by described gate polysilicon layer in the middle part of described gate polysilicon layer and described grid oxic horizon is provided with described middle dielectric layer;
Carry out photoetching and the etching of fairlead, and form the drain metal layer being positioned at described substrate back.
VDMOS device provided by the invention and manufacture method thereof, removed the polysilicon in the middle of two channel regions in existing VDMOS device by twice etching polysilicon, reach the object reducing gate leakage capacitance; Inject by increasing N+ again, knot is dark simultaneously with P+ trap, reaches P+ well region identical with N+ well region ionized impurity concentration, the object that when reaching reverse-biased, N+ well region exhausts completely, inject owing to adding N+, so RJ and RD can reduce, improve the opening speed of VDMOS device.
Accompanying drawing explanation
Fig. 1 is existing VDMOS device conducting resistance composition schematic diagram;
Fig. 2 is the structural representation of VDMOS device of the present invention;
Fig. 3 is the structural representation of existing VDMOS device;
Fig. 4 to Figure 17 is the manufacturing process schematic diagram of VDMOS device of the present invention;
Embodiment
Fig. 1 is existing VDMOS device conducting resistance composition schematic diagram, and as shown in Figure 1, the conducting resistance of traditional VDMOS device, except the Metal Contact resistance at source and drain two ends, also comprises tetrameric resistance: channel resistance R
ch, just to the epitaxial region resistance R of grid near grid
j, just to the epitaxial region resistance R of grid near substrate
dand resistance substrate R
sUB.Due to R
chand R
sUBdrop to very little, and R
jand R
dratio shared by source and drain conducting resistance is comparatively large, therefore the invention provides a kind of VDMOS device and its manufacture method, reduces R
jand R
d, to realize the conducting resistance reducing VDMOS device, improve its opening speed.
Fig. 2 is the structural representation of VDMOS device of the present invention, and Fig. 3 is the structural representation of existing VDMOS device, and as shown in Figure 2, VDMOS device provided by the present invention comprises substrate 2, and is positioned at the epitaxial loayer 3 in substrate 2 front; Be positioned at the grid structure on epitaxial loayer 3 surface, this grid structure comprises grid oxic horizon 4 and is positioned at the gate polysilicon layer 5 on grid oxic horizon 4 surface, and gate polysilicon layer 5 only cover gate oxide layer 4 two ends; The surface do not covered by gate polysilicon layer 5 in the middle part of gate polysilicon layer 5 and grid oxic horizon 4 is provided with middle dielectric layer; Be positioned at the P+ well region of grid structure both sides epitaxial loayer 3, and be positioned at the N+ well region of epitaxial loayer 3 below grid structure, mixing in described N+ well region has ionized impurity; Be positioned at the drain metal layer 1 at substrate 2 back side.
Comparison diagram 2 and Fig. 3 known, VDMOS device provided by the present invention is removed the polysilicon in the middle of two channel regions in existing VDMOS device by twice etching polysilicon, reaches the object reducing gate leakage capacitance; Inject by increasing N+ again, knot is dark simultaneously with P+ trap, reaches P+ well region identical with N+ well region ionized impurity concentration, the object that when reaching reverse-biased, N+ well region exhausts completely, injects, so RJ and RD can reduce owing to adding N+.Further, in VDMOS device provided by the present invention, P+ well region and the N+ well region degree of depth in epitaxial loayer 3 can be identical.
Below introduce the manufacture method of VDMOS device provided by the present invention, comprising:
Step 1, provide a substrate 2, this substrate 2 comprises front and back, and is positioned at the epitaxial loayer 3 in substrate 2 front, and carries out field oxidation, forms field oxide 3a;
Specifically as shown in Figure 4, specifically N-type epitaxy layer 3 can be gone out at N+ grown above silicon.Field oxidation 3a layer can be the silicon dioxide of 12000 dusts.
Step 2, through active area photoetching and etching, be formed with source region figure;
Specifically as shown in Figure 5, pass through the photoetching to field oxide and etching, the end on epitaxial loayer 3 generates ring district, and epitaxial loayer 3 remainder is active area figure.
Step 3, epitaxial loayer 3 surface formed grid oxic horizon 4;
Concrete as shown in Figure 6 gate oxidation is carried out to epitaxial loayer 3 surface, form grid oxic horizon 4, can the silicon dioxide of 800 dusts.
Step 4, deposit grid polycrystalline silicon adulterate simultaneously, form gate polysilicon layer 5;
Specifically as shown in Figure 7, gate polysilicon layer 5 can be the polysilicon of 6000 dusts.
Step 5, first time photoetching and etching are carried out to gate polysilicon layer 5, and carry out N+ injection, in epitaxial loayer 3, do not formed N+ district 6 by the position that gate polysilicon layer 5 covers;
Specifically as shown in Figure 8, through photoetching and the etching of primary gate polysilicon layer 5, and carry out N+ injection in the position of the gate polysilicon layer 5 be etched away, phosphonium ion of specifically can coming in and going out, energy is 130 kilo electron volts, and dosage is 5.9E13 every square centimeter.After N+ has injected, in epitaxial loayer 3, form N+ district 6.
Step 6, second time photoetching and etching are carried out to gate polysilicon layer 5, expose between adjacent N+ district 6 by epitaxial loayer 3 that gate polysilicon layer 5 covers;
Concrete as shown in Figure 9 second time photoetching and etching are carried out to gate polysilicon layer 5, formation gate patterns, expose between adjacent N+ district 6 by epitaxial loayer 3 that gate polysilicon layer 5 covers.
Step 7, P+ injection is carried out to P+ district, in epitaxial loayer 3, form P+ district 7 between adjacent N+ district 6;
Specifically as shown in Figure 10; grid oxic horizon 4 above Jiang Ge N+ district 6; and be positioned at gate polysilicon layer 5(and the grid at grid oxic horizon 4 two ends) coat photoresist 8 and protect; (described P+ district is through the region to the epitaxial loayer 3 come out after gate polysilicon layer 5 two photoetching and etching to carry out the photoetching in P+ district and injection; and in ring district corresponding epitaxial loayer 3 region); such as inject boron ion, energy is 120 kilo electron volts, and dosage is 6E13 every square centimeter.The N+ district 6 formed in the figure of active area and P+ district 7 adjoin one another.
Step 8, knot depths reason is carried out to N+ district 6 and P+ district 7 simultaneously, form N+ well region 6a and P+ well region 7a;
Specifically as shown in figure 11, dark through P knot, complete N+ well region 6a and P+ well region 7a.Preferably, N+ well region 6a is identical with the degree of depth of P+ well region 7a in epitaxial loayer 3; N+ well region 6a is identical with the ionized impurity concentration of P+ well region 7a.
Step 9, photoetching and etching are carried out to P+ well region 7a;
Specifically as shown in figure 12, source region photoetching and etching is carried out.Retain the grid oxic horizon 4 above N+ well region 6a, to etch away above P+ well region 7a and near the grid oxic horizon 4 of grid.
Step 10, ion implantation is carried out to P+ well region 7a, and deposit middle dielectric layer 9, form the grid structure being positioned at described epi-layer surface;
Specifically as shown in figure 13, inject phosphonium ion to P+ well region 7a, energy is 120 kilo electron volts, and dosage is 5E15 every square centimeter.Middle dielectric layer 9 can be the silicon nitride of 1200 dusts and the boron-doping phosphorus silicon dioxide of 10000 dusts.Middle dielectric layer backflow again, makes chip surface planarization, is conducive to metal filled.
To which form grid structure of the present invention, comprise grid oxic horizon 4 and the gate polysilicon layer 5 being positioned at grid oxic horizon 4 surface, and gate polysilicon layer 5 only cover gate oxide layer 4 two ends; The surface do not covered by gate polysilicon layer 5 in the middle part of gate polysilicon layer 5 and grid oxic horizon 4 is provided with middle dielectric layer 9.
Step 11, carry out fairlead photoetching and etching, form fairlead figure; Carry out aluminum bronze metal level 10 again to sputter, such as aluminum bronze 40000 dust, specifically as shown in figure 14.
Step 12, the photoetching carrying out metal level 10 and etching, specifically as shown in figure 15.
Step 13, passivation layer 11 deposit, passivation layer 11 photoetching and etching;
Specifically as shown in figure 16, passivation layer 11 can be the silicon nitride of 2000 dusts.
Step 14, formation are positioned at the drain metal layer 1 of described substrate back, complete the manufacture of VDMOS pipe.
Specifically as shown in figure 17, alloy technique is carried out; (450C, 30 minutes), thinning v process (260 microns), the back side is injected and is such as injected phosphonium ion, and energy is 50 kilo electron volts, and dosage is 3E15 every square centimeter; Back side alloy (450C, 60 minutes), evaporation back metal, parameter testing.
The manufacture method of the VDMOS device that the embodiment of the present invention provides, is removed the polysilicon in the middle of two channel regions in existing VDMOS device by twice etching polysilicon, reaches the object reducing gate leakage capacitance; Inject by increasing N+ again, knot is dark simultaneously with P+ trap, reaches P+ well region identical with N+ well region ionized impurity concentration, the object that when reaching reverse-biased, N+ well region exhausts completely, inject owing to adding N+, so RJ and RD can reduce, improve the opening speed of VDMOS device.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (6)
1. a VDMOS device, is characterized in that, comprising:
Substrate, and the epitaxial loayer being positioned at described substrate face;
Be positioned at the grid structure of described epi-layer surface, described grid structure comprises grid oxic horizon and is positioned at the gate polysilicon layer on described grid oxic horizon surface, and described gate polysilicon layer only covers described grid oxic horizon two ends; The surface do not covered by described gate polysilicon layer in the middle part of described gate polysilicon layer and described grid oxic horizon is provided with middle dielectric layer;
Be positioned at the P+ well region of epitaxial loayer described in described grid structure both sides, and be positioned at the N+ well region of described epitaxial loayer below described grid structure, mixing in described N+ well region has ionized impurity;
Be positioned at the drain metal layer of described substrate back.
2. VDMOS device according to claim 1, is characterized in that, described P+ well region is identical with the ionized impurity concentration of described N+ well region.
3. VDMOS device according to claim 1 and 2, is characterized in that, described P+ well region is identical with the degree of depth of described N+ well region in described epitaxial loayer.
4. a manufacture method for VDMOS device, is characterized in that, comprising:
There is provided a substrate, described substrate comprises front and back, and is positioned at the epitaxial loayer of described substrate face;
Grid oxic horizon is formed in described epi-layer surface, and be positioned at the gate polysilicon layer on described grid oxic horizon surface, first time photoetching and etching are carried out to described gate polysilicon layer, and carry out N+ injection, in described epitaxial loayer, do not formed N+ district by the position that described gate polysilicon layer covers;
Second time photoetching and etching are carried out to described gate polysilicon layer, exposes the epitaxial loayer covered by described gate polysilicon layer between adjacent N+ district, and carry out P+ injection, in described epitaxial loayer, form P+ district between adjacent N+ district;
Knot depths reason is carried out to described N+ district and described P+ district simultaneously, forms N+ well region and P+ well region; Photoetching and etching are carried out to described P+ well region, and carries out ion implantation; Deposit middle dielectric layer, forms the grid structure being positioned at described epi-layer surface; Described grid structure comprises grid oxic horizon and is positioned at the gate polysilicon layer on described grid oxic horizon surface, and described gate polysilicon layer only covers described grid oxic horizon two ends; The surface do not covered by described gate polysilicon layer in the middle part of described gate polysilicon layer and described grid oxic horizon is provided with described middle dielectric layer;
Carry out photoetching and the etching of fairlead, and form the drain metal layer being positioned at described substrate back.
5. method according to claim 4, is characterized in that, described P+ well region is identical with the ionized impurity concentration of described N+ well region.
6. the method according to claim 4 or 5, is characterized in that, described P+ well region is identical with the degree of depth of described N+ well region in described epitaxial loayer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310256294.XA CN104253045A (en) | 2013-06-25 | 2013-06-25 | VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor) device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310256294.XA CN104253045A (en) | 2013-06-25 | 2013-06-25 | VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor) device and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN104253045A true CN104253045A (en) | 2014-12-31 |
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|---|---|---|---|
| CN201310256294.XA Pending CN104253045A (en) | 2013-06-25 | 2013-06-25 | VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor) device and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870184A (en) * | 2015-01-21 | 2016-08-17 | 北大方正集团有限公司 | Power device manufacturing method and power device |
| CN110648921A (en) * | 2019-10-08 | 2020-01-03 | 北京锐达芯集成电路设计有限责任公司 | N-channel depletion type VDMOS device and manufacturing method thereof |
-
2013
- 2013-06-25 CN CN201310256294.XA patent/CN104253045A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870184A (en) * | 2015-01-21 | 2016-08-17 | 北大方正集团有限公司 | Power device manufacturing method and power device |
| CN110648921A (en) * | 2019-10-08 | 2020-01-03 | 北京锐达芯集成电路设计有限责任公司 | N-channel depletion type VDMOS device and manufacturing method thereof |
| CN110648921B (en) * | 2019-10-08 | 2023-01-24 | 北京锐达芯集成电路设计有限责任公司 | N-channel depletion type VDMOS device and manufacturing method thereof |
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