JP2009277755A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that allows a MOSFET to stably operate and also prevents the breakdown voltage of an SBD region from decreasing. <P>SOLUTION: The semiconductor device includes an n+ type semiconductor substrate 1 where an MOSFET region 10 and an SBD region 20 are arranged, and an n type epitaxial layer 2 provided on the n+ type semiconductor substrate 1. The MOSFET region 10 includes a p+ type diffusion region 5 provided in a p type base region 3 and having a first impurity concentration. The SBD region 20 includes a p type diffusion region 21 provided on an upper surface of the n type epitaxial layer 2 and having a second impurity concentration. The second impurity concentration that the p type diffusion area 21 has is lower than the first impurity concentration that the p+ type diffusion region 5 has. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a transistor and a Schottky barrier diode are mixedly mounted.

  A semiconductor device in which a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a Schottky Barrier Diode (SBD) are mixedly mounted is widely used for power conversion and control in various communication devices and household electrical devices. Yes. In order to achieve miniaturization, high efficiency, and low power consumption of a power supply system using this semiconductor device, the semiconductor device in which the MOSFET and SBD constituting the system are mixedly mounted is turned on while maintaining a high breakdown voltage. There is a need to reduce the resistance of the state.

  In order to reduce the on-resistance during the on-operation of the vertical MOSFET, a configuration is known in which a p-type diffusion region is provided below a source electrode that is electrically connected to an n + type source region and a p-type base region. The source electrode and the p-type base region are connected via the p-type diffusion region (see Patent Document 1).

  On the other hand, in SBD, a p-type diffusion region is formed so as to be in contact with the end portion of the anode electrode in order to suppress a decrease in breakdown voltage at the Schottky junction portion due to the anode electrode and the n-type epitaxial layer (see Patent Document 2). When the semiconductor device is turned off, a depletion layer spreads between the p-type diffusion region and the n-type epitaxial layer, and the breakdown voltage of the SBD is maintained.

In a semiconductor device in which a MOSFET and an SBD are mixedly mounted, in order to improve the performance of the MOSFET, the on-resistance is reduced by increasing the n-type impurity concentration of the n-type epitaxial layer on the semiconductor substrate. In order to stably operate such a MOSFET, a high impurity concentration is also required for the p-type diffusion region provided under the source electrode. Here, in the case where the p-type diffusion region provided at the end of the Schottky junction of the SBD has an impurity concentration as high as that of the p-type diffusion region of the MOSFET, between the n-type epitaxial layer having a high n-type impurity concentration The depletion layer is difficult to spread during the off operation, and the breakdown voltage of the SBD is lowered.
JP 2006-210392A JP 2003-142698 A

  An object of the present invention is to provide a semiconductor device capable of stably operating a MOSFET and preventing a decrease in breakdown voltage in an SBD region.

  A semiconductor device according to one aspect of the present invention includes a semiconductor substrate of a first conductivity type in which a transistor region in which a transistor is formed and a Schottky barrier diode region in which a Schottky barrier diode is formed, and the semiconductor A first conductivity type epitaxial layer provided on the substrate, and the transistor region includes a second conductivity type base region provided on an upper surface of the epitaxial layer, and a first conductivity type provided on the base region. A first conductivity type first high-concentration diffusion region having an impurity concentration, a first conductivity type diffusion region selectively provided on an upper surface of the base region, and the diffusion region from the base region through the base region And a control electrode provided through an insulating film in a region extending through the epitaxial layer, and the Schottky barrier diode region includes the epitaxial layer. A second conductivity type second high-concentration diffusion region provided on the upper surface of the Shall layer and having a second impurity concentration lower than the first impurity concentration is formed, and the first high-concentration diffusion in the transistor region Electrically connected to the region and the diffusion region, and electrically connected to the epitaxial layer and the second high-concentration diffusion region in the Schottky barrier diode region, and the epitaxial layer in the Schottky barrier diode region And a first main electrode forming a Schottky junction, and a second main electrode electrically connected to the lower surface of the semiconductor substrate.

  According to the present invention, it is possible to provide a semiconductor device capable of stably operating a MOSFET and preventing a decrease in breakdown voltage in the SBD region.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type. In addition, “n + type” described below indicates a semiconductor having a high n-type impurity concentration, and “n− type” indicates a semiconductor having a low n-type impurity concentration. Similarly, “p + type” and “p− type” indicate a semiconductor having a high p-type impurity concentration and a semiconductor having a low p-type impurity concentration, respectively. In the following embodiments, a semiconductor device will be described by taking a semiconductor device in which an n-channel trench gate type MOSFET and SBD are mixedly mounted as an example.

(First embodiment)
FIG. 1 is a cross-sectional view of a chip on which a semiconductor device according to the first embodiment is formed. In the semiconductor device, a MOSFET region 10 where a MOSFET is formed and an SBD region 20 where an SBD is formed are arranged. FIG. 1A is a cross-sectional view showing the structure of the MOSFET region 10 of the semiconductor device, and FIG. 1B is a cross-sectional view showing the structure of the SBD region 20 of the semiconductor device.

  As shown in FIG. 1A, an n + type semiconductor substrate 1 having an upper surface and a lower surface facing each other is provided in the MOSFET region 10, and an n type epitaxial layer 2 is provided on the upper surface of the n + type semiconductor substrate 1. It has been. A p-type base region 3 is provided on the upper surface of the n-type epitaxial layer 2. Further, an n + type source region 4 connected to the p type base region 3 is selectively provided on the upper surface of the p type base region 3. In the present embodiment, a contact trench t1 is formed in the n + type source region 4 on the p type base region 3 so as to reach the surface of the p type base region 3, and the p type base in contact with the bottom of the contact trench t1. A p + type diffusion region 5 is provided in the region 3.

In the p + -type diffusion region 5, for example, boron difluoride (BF ₂ ) is implanted as a p-type impurity, and 1E19 cm ⁻³ or more and 1E21 cm ⁻³ or less in the surface portion in contact with the bottom of the contact trench t1. For example, it has an impurity concentration of about 1E20 cm ⁻³ . Further, the value obtained by linearly integrating the impurity concentration from the upper surface of the p + type diffusion region 5 to the depth of 0.5 μm in the depth direction perpendicular to the n + type semiconductor substrate 1 (y direction shown in FIG. 1) is 5E14 cm ^−2. The value is 1E16 cm ⁻² or less.

  The n + -type source region 4 is provided with a gate trench T that reaches the inside of the n-type epitaxial layer 2 from the surface of the n + -type source region 4 through the p-type base region 3. A gate insulating film 6 is provided on the side and bottom surfaces of the gate trench T, and a gate electrode G is embedded inside the gate trench T via the gate insulating film 6. An interlayer insulating film 7 is provided on the gate electrode G. The gate electrode G is for applying a gate voltage equal to or higher than a threshold voltage to form a channel in the p-type base region 3 to make the MOSFET conductive. Further, a source electrode S is provided on the n + type source region 4 so as to be electrically connected to the n + type source region 4 and the p + type diffusion region 5. The source electrode S is also buried in the contact trench t1. The source electrode S in the contact trench t1 is connected to the n + type source region 4 on the side surface. Further, the source electrode S and the p + -type diffusion region 5 are electrically connected below the contact trench t1. A drain electrode D is provided so as to be electrically connected to the lower surface of the n + type semiconductor substrate 1. As a result, a plurality of MOSFETs are formed in a direction parallel to the n + type semiconductor substrate 1 (x direction shown in FIG. 1).

  As shown in FIG. 1B, an n-type epitaxial layer 2 is also provided on the upper surface of the n + -type semiconductor substrate 1 having an upper surface and a lower surface that face each other also in the SBD region 20. A plurality of Schottky junction trenches t2 having substantially the same depth as the contact trench t1 of the MOSFET region 10 are formed on the surface of the n-type epitaxial layer 2. A p-type diffusion region 21 is provided in the n-type epitaxial layer 2 in contact with the bottom of the Schottky junction trench t2.

In the p-type diffusion region 21, for example, boron (B) is implanted as a p-type impurity, and the surface portion in contact with the bottom of the Schottky junction trench t 2 is 1E16 cm ⁻³ or more and 1E18 cm ⁻³ or less. For example, it has an impurity concentration of about 1E17 cm ⁻³ . The value obtained by line integration of the impurity concentration from the upper surface of the p-type diffusion region 21 to the depth of 0.5 μm in the depth direction perpendicular to the n + -type semiconductor substrate 1 (y direction shown in FIG. 1) is 1E13 cm ⁻² or more and 1E14 cm. ^-2 or less.

  An anode electrode 22 is provided on the surface of the n-type epitaxial layer 2 including the inside of the Schottky junction trench t2. A Schottky junction A is formed at the junction interface between the anode electrode 22 and the n-type epitaxial layer 2. A cathode electrode 23 is provided so as to be electrically connected to the lower surface of the n + type semiconductor substrate 1. In the semiconductor device according to the present embodiment, the source electrode S in the MOSFET region 10 and the anode electrode 22 in the SBD region 20 are connected to each other. The drain electrode D in the MOSFET region 10 and the cathode electrode 23 in the SBD region 20 are also connected to each other.

  Next, the operation of the semiconductor device thus formed will be described. In the operation of the semiconductor device, it is assumed that the n + -type source region 4 and the p-type base region 3 of each MOSFET formed in the MOSFET region 10 are grounded via the source electrode S. Further, it is assumed that a predetermined positive voltage is applied to the n + type semiconductor substrate 1 which is the drain region via the drain electrode D.

  When the semiconductor device is turned on, a predetermined positive voltage (a gate voltage equal to or higher than the threshold voltage) is applied to the gate electrode G of each MOSFET in the MOSFET region 10. As a result, an n-type inversion layer is formed in the channel region of the p-type base region 3. Electrons from the n + type source region 4 pass through this inversion layer, are injected into the n type epitaxial layer 2 that is the drift region, and reach the n + type semiconductor substrate 1 that is the drain region. Therefore, a current flows from the n + type semiconductor substrate 1 to the n + type source region 4.

  During the on-operation of the semiconductor device, the anode electrode 22 in the SBD region 20 is grounded together with the source electrode S, and a predetermined positive potential is applied to the cathode electrode 23 together with the drain electrode D. Due to the Schottky barrier due to the Schottky junction A, free electrons of the anode electrode 22 cannot move to the n-type epitaxial layer 2. Therefore, no current flows from the cathode electrode 23 to the anode electrode 22.

  When the semiconductor device is turned off, the voltage applied to the gate electrode G is controlled so that the gate voltage applied to the gate electrode G of each MOSFET is equal to or lower than the threshold voltage in the MOSFET region 10. Thereby, the inversion layer of the channel region of the p-type base region 3 disappears, and the injection of electrons from the n + -type source region 4 to the n-type epitaxial layer 2 is stopped. Therefore, no current flows from the n + type semiconductor substrate 1 which is the drain region to the n + type source region 4. During the off operation, the breakdown voltage of the semiconductor device is maintained by the depletion layer extending in the vertical direction (y direction shown in FIG. 1) from the pn junction interface formed by the n-type epitaxial layer 2 and the p-type base region 3. .

  When the semiconductor device is turned off, the potentials of the source electrode S and the drain electrode D of the MOSFET may be instantaneously reversed. That is, a high voltage is applied to the source electrode S and a low voltage is applied to the drain electrode D. As a result, current may flow from the p + type diffusion region 5 to the n + type semiconductor substrate 1 through the p type base region 3 and the n type epitaxial layer 2.

  In the semiconductor device according to the present embodiment, the anode electrode 22 and the source electrode S, the cathode electrode 23 and the drain electrode D are connected, and the MOSFET and the SBD are connected in parallel. When a high voltage is applied to the anode electrode 22 and a low voltage is applied to the cathode electrode 23, free electrons in the n-type epitaxial layer 2 move to the anode electrode 22 side having a low energy level, and the anode electrode 22 moves to the cathode electrode. A current flows to 23. Here, when a high voltage is applied to the source electrode S and a low voltage is applied to the drain electrode D, the SBD is turned on at a lower voltage than the MOSFET, so that the current flows to the SBD side and the current flows to the MOSFET. There is no. Further, when the potential returns to normal, the current flowing through the SBD is instantaneously turned off.

  When the semiconductor device according to the present embodiment is turned off, a depletion layer extends from the pn junction interface between the p-type diffusion region 21 and the n-type epitaxial layer 2 in the SBD region, and a voltage is held in the depletion layer. At this time, if the impurity concentration of the p-type diffusion region 21 and the n-type epitaxial layer 2 is high, the depletion layer is difficult to spread from the pn junction interface. If the depletion layer does not spread sufficiently, the breakdown voltage of the SBD region 20 of the semiconductor device will decrease.

Here, in the semiconductor device of the present embodiment, the p-type impurity concentration is lower in the p-type diffusion region 21 formed in the SBD region 20 than in the p + -type diffusion region 5 formed in the MOSFET region 10. Is provided. The p-type diffusion region 21 of the SBD region 20 has an impurity concentration of about 1E17 cm ⁻³ . With this impurity concentration, the depletion layer normally spreads sufficiently in the p-type diffusion region 21, and the breakdown voltage can be maintained in the SBD region 20. On the other hand, since the impurity concentration of the p + -type diffusion region 5 in the MOSFET region 10 is about 1E20 cm ⁻³ , the connection between the source electrode S of the MOSFET and the p-type base region 3 is kept good, and the MOSFET is operated stably. be able to.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described. 2 to 6 are process diagrams showing the manufacturing process of the semiconductor device according to the present embodiment. 2A to 6A are cross-sectional views showing the MOSFET region 10 of the semiconductor device, and FIGS. 2B to 6B are cross-sectional views showing the SBD region 20 of the semiconductor device. is there.

  The processes up to forming the n-type epitaxial layer 2, the p-type base region 3, the n + -type source region 4 and the gate electrode G on the n + -type semiconductor substrate 1 are manufactured by a known MOSFET manufacturing process. That is, after ion-implanting p-type impurities such as boron (B) into the MOSFET region 10 on the upper surface of the n-type epitaxial layer 2 provided on the n + -type semiconductor substrate 1, the p-type base region is diffused by heat, for example. 3 is formed. Then, after n-type impurities such as phosphorus (P) are ion-implanted into the upper surface of the p-type base region 3, the n + -type source region 4 is formed by, for example, heat diffusion. Next, after forming a gate trench T extending from the surface of the n + type source region 4 formed in the MOSFET region 10 to the inside of the n type epitaxial layer 2, the gate insulating film 6 is thermally oxidized on the bottom and side walls of the gate trench T. To form. For example, polysilicon or the like is buried in the gate trench T through the gate insulating film 6 to form the gate electrode G. In the steps so far, a mask is provided on the upper surface of the SBD region 20 and no processing is performed.

  Next, as shown in FIG. 2, an interlayer insulating film 7 covering the upper surface of the gate electrode G is deposited. The interlayer insulating film 7 is uniformly deposited on the MOSFET region 10 and the SBD region 20. Then, after depositing a resist on the interlayer insulating film 7, the resist is patterned and etched to form a contact trench t 1 in the MOSFET region 10 and a Schottky junction trench t 2 in the SBD region 20.

Next, as shown in FIG. 3, a resist R <b> 1 is uniformly deposited on the MOSFET region 10 and the SBD region 20, and then patterned to form the resist R <b> 1 only on the MOSFET region 10. Using this resist R1 as a mask, a p-type impurity such as boron ( ¹¹ B) is ion-implanted into the entire surface of the n + -type semiconductor substrate 1 at an acceleration voltage of 70 keV and a dose of 3E13 cm ⁻² . As a result, boron ions are implanted only into the bottom of the Schottky junction trench t2 in the SBD region 20.

Next, as shown in FIG. 4, after removing the resist R <b> 1, the resist R <b> 2 is uniformly deposited on the MOSFET region 10 and the SBD region 20, and patterned to form the resist R <b> 2 only on the SBD region 20. Using this resist R2 as a mask, a p-type impurity, for example, boron difluoride ( ⁴⁹ BF ₂ ) is ion-implanted into the entire surface of the n + -type semiconductor substrate 1 at an acceleration voltage of 30 keV and a dose of 5E15 cm ⁻² . As a result, boron difluoride ions are implanted only into the bottom of the contact trench t1 in the MOSFET region 10. After removing the resist R2, activation annealing is performed in a nitrogen (N ₂ ) atmosphere at 900 ° C. for 20 minutes. As a result, p-type impurities are diffused to form p + -type diffusion region 5 in p-type base region 3 of MOSFET region 10, and p-type diffusion region 21 is formed in n-type epitaxial layer 2 of SBD region 20. .

  Next, as shown in FIG. 5, wet etching is performed to remove the interlayer insulating film 7 in the SBD region 20. At this time, a part of the interlayer insulating film 7 on the gate electrode G in the MOSFET region 10 is also removed, and a part of the upper surface of the n + -type source region 4 is exposed.

  Next, as shown in FIG. 6, a metal is sputtered on the MOSFET region 10 and the SBD region 20 and then etched, and the source electrically connected to the p + type diffusion region 5 and the n + type source region 4 is connected to the MOSFET region 10. An electrode S is formed. At the same time, an anode electrode 22 that is electrically joined to the n-type epitaxial layer 2 is formed in the SBD region 20. Thereafter, after the lower surface of the n + type semiconductor substrate 1 is polished, the drain electrode D and the cathode electrode 23 are provided. As described above, the semiconductor device shown in FIG. 1 can be manufactured.

  According to the method of manufacturing a semiconductor device according to the present embodiment, p + type diffusion region 5 formed in MOSFET region 10 and p type diffusion region 21 formed in SBD region 20 can be formed with different impurity concentrations. . Since the impurity concentration of the p-type diffusion region 21 in the SBD region 20 can be formed to be lower than the impurity concentration of the p + -type diffusion region 5 in the MOSFET region 10, a depletion layer is usually sufficient in the p-type diffusion region 21. And the breakdown voltage can be maintained in the SBD region 20. On the other hand, the impurity concentration of p + -type diffusion region 5 in MOSFET region 10 can be made higher than the impurity concentration of p-type diffusion region 21 in SBD region 20. Therefore, the connection between the source electrode S of the MOSFET and the p-type base region 3 is kept good, and the MOSFET can be operated stably.

(Second Embodiment)
FIG. 7 is a cross-sectional view of a chip on which a semiconductor device according to the second embodiment is formed. In the semiconductor device, a MOSFET region 10 where a MOSFET is formed and an SBD region 20 where an SBD is formed are arranged. FIG. 7A is a cross-sectional view showing the MOSFET region 10 of the semiconductor device, and FIG. 7B is a cross-sectional view showing the SBD region 20 of the semiconductor device. In the semiconductor device according to the second embodiment shown in FIG. 7, portions having the same configuration as those of the semiconductor device according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 7A, in the MOSFET region 10 of the semiconductor device according to the second embodiment, a p-type diffusion region 5 ′ is formed below the p + -type diffusion region 5 in the p-type base region 3. This is different from the semiconductor device according to the first embodiment. In the p-type diffusion region 5 ′, for example, boron (B) is implanted as a p-type impurity, and has an impurity concentration of about 1E17 cm ^{−3 in the} surface portion in contact with the p + -type diffusion region 5.

Also in the semiconductor device according to the present embodiment, the p-type impurity concentration in the p-type diffusion region 21 formed in the SBD region 20 is lower than that in the p + -type diffusion region 5 formed in the MOSFET region 10. It has been. The p-type diffusion region 21 of the SBD region 20 has an impurity concentration of about 1E17 cm ⁻³ . With this impurity concentration, the depletion layer normally spreads sufficiently in the p-type diffusion region 21, and the breakdown voltage can be maintained in the SBD region 20. On the other hand, since the impurity concentration of the p + -type diffusion region 5 in the MOSFET region 10 is about 1E20 cm ⁻³ , the connection between the source electrode S of the MOSFET and the p-type base region 3 is kept good, and the MOSFET is operated stably. be able to. Here, in the MOSFET region 10, since the p-type diffusion region 5 ′ is provided in the p-type base region below the p + -type diffusion region 5, the channel region on the side wall of the gate trench T is not affected. The p-type diffusion region 5 ′ provided in the MOSFET region 10 does not greatly change the MOSFET characteristics.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described. 8 to 10 are process diagrams showing the manufacturing process of the semiconductor device according to the present embodiment. FIGS. 8A to 10A are cross-sectional views showing the MOSFET region 10 of the semiconductor device, and FIGS. 8B to 10B are cross-sectional views showing the SBD region 20 of the semiconductor device. is there.

  The manufacturing method of the semiconductor device according to the present embodiment is the same as the manufacturing method of the semiconductor device according to the first embodiment until the step of forming the contact trench t1 and the Schottky junction trench t2 shown in FIG. .

Next, as shown in FIG. 8, a p-type impurity, for example, boron ( ¹¹ B) is ion-implanted into the entire surface of the n + -type semiconductor substrate 1 at an acceleration voltage of 70 keV and a dose amount of 3E13 cm ⁻² . Thus, boron ions are implanted into both the bottom of the contact trench t1 in the MOSFET region 10 and the bottom of the Schottky junction trench t2 in the SBD region 20.

Next, as shown in FIG. 9, a resist R <b> 2 is uniformly deposited on the MOSFET region 10 and the SBD region 20 and patterned to form the resist R <b> 2 only on the SBD region 20. Using this resist R2 as a mask, a p-type impurity, for example, boron difluoride ( ⁴⁹ BF ₂ ) is ion-implanted into the entire surface of the n + -type semiconductor substrate 1 at an acceleration voltage of 30 keV and a dose of 5E15 cm ⁻² . After removing the resist R2, activation annealing is performed in a nitrogen (N ₂ ) atmosphere at 900 ° C. for 20 minutes. As a result, p type impurities are diffused to form p + type diffusion region 5 and p type diffusion region 5 ′ in p type base region 3 of MOSFET region 10, and p type impurity layer 2 in SBD region 20 has p A mold diffusion region 21 is formed.

  Next, as shown in FIG. 10, wet etching is performed to remove the interlayer insulating film 7 in the SBD region 20. At this time, a part of the interlayer insulating film 7 on the gate electrode G in the MOSFET region 10 is also removed, and a part of the upper surface of the n + -type source region 4 is exposed.

  Thereafter, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment, a metal is sputtered on the MOSFET region 10 and the SBD region 20 and then etched, and the p + type diffusion region 5 and the n + type source are formed in the MOSFET region 10. A source electrode S electrically connected to the region 4 is formed. At the same time, an anode electrode 22 that is electrically joined to the n-type epitaxial layer 2 is formed in the SBD region 20. Then, after the lower surface of the n + type semiconductor substrate 1 is polished, the drain electrode D and the cathode electrode 23 are provided. As described above, the semiconductor device shown in FIG. 7 can be manufactured.

  Also by the method for manufacturing a semiconductor device according to the present embodiment, p + type diffusion region 5 formed in MOSFET region 10 and p type diffusion region 21 formed in SBD region 20 can be formed with different impurity concentrations. Since the impurity concentration of the p-type diffusion region 21 in the SBD region 20 can be formed to be lower than the impurity concentration of the p + -type diffusion region 5 in the MOSFET region 10, a depletion layer is usually sufficient in the p-type diffusion region 21. And the breakdown voltage can be maintained in the SBD region 20. On the other hand, the impurity concentration of p + -type diffusion region 5 in MOSFET region 10 can be made higher than the impurity concentration of p-type diffusion region 21 in SBD region 20. Therefore, the connection between the source electrode S of the MOSFET and the p-type base region 3 is kept good, and the MOSFET can be operated stably.

  Further, according to the method for manufacturing a semiconductor device according to the present embodiment, the number of times of forming a resist can be reduced as compared with the method for manufacturing a semiconductor device according to the first embodiment. Therefore, a semiconductor device can be formed with a simpler process.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to these, A various change, addition, a combination, etc. are possible within the range which does not deviate from the meaning of invention.

  For example, in the embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. Although the semiconductor device has been described as a trench gate type MOSFET, it may be a planar gate type MOSFET. In the embodiment, the MOSFET using silicon as the semiconductor material has been described. As the semiconductor material, for example, a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) or a wide band gap semiconductor such as diamond is used. be able to.

It is sectional drawing which shows the structure of the semiconductor device which concerns on 1st Embodiment. It is process drawing explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process drawing explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process drawing explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process drawing explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process drawing explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is process drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is process drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is process drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... n + type semiconductor substrate, 2 ... n type epitaxial layer, 3 ... p type base region, 4 ... n + type source region, 5 ... p + type diffusion region, 6 ... Gate Insulating film, 7 ... Interlayer insulating film, 10 ... MOSFET region, 20 ... SBD region, 21 ... p-type diffusion region, 22 ... anode electrode, 23 ... cathode electrode, G. ..Gate electrode, S ... Source electrode, D ... Drain electrode, T ... Gate trench, t1 ... Contact trench, t2 ... Schottky junction trench, R1, R2 ... Resist .

Claims (5)

A first conductivity type semiconductor substrate in which a transistor region in which a transistor is formed and a Schottky barrier diode region in which a Schottky barrier diode is formed;
An epitaxial layer of a first conductivity type provided on the semiconductor substrate,
In the transistor region,
A base region of a second conductivity type provided on the upper surface of the epitaxial layer;
A first high-concentration diffusion region of a second conductivity type provided in the base region and having a first impurity concentration;
A first conductivity type diffusion region selectively provided on the upper surface of the base region;
A control electrode provided via an insulating film in a region extending from the diffusion region to the epitaxial layer via the base region; and
In the Schottky barrier diode region,
A second conductivity type second high-concentration diffusion region formed on the upper surface of the epitaxial layer and having a second impurity concentration lower than the first impurity concentration;
The transistor region is electrically connected to the first high concentration diffusion region and the diffusion region, and is electrically connected to the epitaxial layer and the second high concentration diffusion region in the Schottky barrier diode region. A first main electrode forming a Schottky junction with the epitaxial layer in the Schottky barrier diode region;
A semiconductor device, comprising: a second main electrode electrically connected to a lower surface of the semiconductor substrate. The first impurity concentration is 1E19 cm ⁻³ or more and 1E21 cm ⁻³ or less on the surface of the first high concentration diffusion region,
2. The semiconductor device according to claim 1, wherein the second impurity concentration is 1E16 cm ⁻³ or more and 1E18 cm ⁻³ or less on the surface of the second high concentration diffusion region. A value obtained by line-integrating the first impurity concentration from the surface of the first high-concentration diffusion region to a depth of 0.5 μm is:
3. The semiconductor device according to claim 1, wherein the second impurity concentration is larger than a value obtained by line integration from the surface of the second high concentration diffusion region to a depth of 0.5 μm. A value obtained by linearly integrating the first impurity concentration from the surface of the first high-concentration diffusion region to a depth of 0.5 μm is 5E14 cm ⁻² or more and 1E16 cm ⁻² or less,
The value obtained by line-integrating the second impurity concentration from the surface of the second high-concentration diffusion region to a depth of 0.5 μm is 1E13 cm ⁻² or more and 1E14 cm ⁻² or less. Any one of the semiconductor devices. The first main electrode is
In the transistor region, embedded in a contact trench formed so as to penetrate the diffusion region, and connected to the first high concentration diffusion region at the bottom of the contact trench,
The Schottky barrier diode region is embedded in a Schottky junction trench formed on the surface of the epitaxial layer, and is connected to the second high-concentration diffusion region at the bottom of the Schottky junction trench. The semiconductor device according to claim 1, wherein the semiconductor device is provided.

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