CN108346688A - SiC trench junction barrier schottky diodes with CSL transport layers and preparation method thereof - Google Patents
SiC trench junction barrier schottky diodes with CSL transport layers and preparation method thereof Download PDFInfo
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- CN108346688A CN108346688A CN201810075436.5A CN201810075436A CN108346688A CN 108346688 A CN108346688 A CN 108346688A CN 201810075436 A CN201810075436 A CN 201810075436A CN 108346688 A CN108346688 A CN 108346688A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Abstract
Present disclose provides a kind of SiC trench junction barrier schottky diodes and preparation method thereof with CSL transport layers, including multiple first CSL current transport layers and multiple 2nd CSL current transport layers；Selective P on first CSL current transport layers++The regions SiC ring, P++It is corresponding groove structure on the ring of the regions SiC, has Schottky contact electrode on groove structure；Directly it is Schottky contact electrode on 2nd CSL current transport layers；Schottky contact electrode periphery is equipped with multiple P+SiC protection rings and a N+Field cut-off ring；Schottky contact electrode edge is equipped with SiO2Passivation layer.The disclosure adds P using groove technology++The complex art injected deeply reduces chip surface electric field, reduce the reduction effect of Schottky barrier, inhibit leakage current, and optimizes cooperation CSL transport layer structures and greatly increase current capacity, reduce the temperature dependency and sensibility of device electrology characteristic, in the case where reverse breakdown characteristics are unaffected lower, high temperature high current SiC power electronic devices is obtained, it is simple for process, repeatable.
Description
Technical field
The disclosure belongs to technical field of semiconductor device, is related to a kind of SiC trench junction barriers Xiao Te with CSL transport layers
Based diode (Trench-JBS) and preparation method thereof, more particularly to one kind (forward current raceway groove) and P between Trench++Note
Enter lower section and carry out N-type ion implanting, realizing has N+The SiC TJBS structures of CSL transport layers.
Background technology
Carbofrax material has excellent physically and electrically characteristic, with its wide energy gap, high thermal conductivity, big full
With the particular advantages such as drift velocity and high critical breakdown electric field, becomes and make high power, high frequency, high temperature resistant, radioresistance device
Ideal semiconductor material, have broad application prospects at military and civil aspect.The power electronics device made with SiC material
Part has become one of hot spot device and research frontier of current semiconductor applications.
In the diode of SiC, trench junction barrier schottky diode is the base in junction barrier schottky structure (JBS)
On plinth, pn-junction potential barrier is advanced further towards device inside using groove structure, fully reduces device table under high reverse blocking voltage
Face Schottky barrier reduces effect, excludes limitation of the reverse leakage current to highest blocking voltage.In the SiC bis- of high speed, high voltage
Pole pipe field has prodigious advantage.However while introducing Trench structures, the length of conducting channel compared with JBS structure into
One step lengthens so that forward resistance increases, and forward current reduces under same forward voltage.Therefore tradition TJBS structures are being promoted instead
Forward conduction resistance is sacrificed while to blocking ability.
Disclosure
(1) technical problems to be solved
For the disclosure for the larger situation of tradition TJBS structure forward conduction resistance, proposition is a kind of to improve forward characteristic
SiC trench junction barrier schottky diodes with CSL transport layers and preparation method thereof.
(2) technical solution
Present disclose provides a kind of SiC trench junction barrier schottkies diodes, including：N++SiC substrate；N-- SiC extensions
Layer, is formed in the N++SiC substrate front；The N+Surface on back side of SiC substrate is equipped with N-type Ohmic contact；Further include：CSL electric currents
Transport layer is formed in the N-In SiC epitaxial layer, including：Multiple first CSL current transport layers and multiple 2nd CSL electric currents are defeated
Layer is transported, the first CSL current transport layers and the 2nd CSL current transport layers are spaced；There is choosing on first CSL current transport layers
Selecting property P++The regions-SiC ring, P++It is corresponding groove structure on the ring of the regions-SiC, there is schottky junctions electric shock on groove structure
Pole；Directly it is Schottky contact electrode on 2nd CSL current transport layers；Schottky contact electrode periphery is equipped with multiple P+- SiC is protected
Retaining ring and a N+Field cut-off ring；Schottky contact electrode edge is equipped with SiO2Passivation layer；In SiO2Field is equipped with above passivation layer
Plate.
In some embodiments of the present disclosure, the doping concentration of the CSL current transport layers is 8E16cm-3-1E18cm-3Between, injection depth is more than 0.5um, is less than N-SiC epitaxial layer thickness；And/or multiple first CSL current transport layers, second
CSL current transport layers and N+Field cut-off ring injects to be formed together.
In some embodiments of the present disclosure, the groove width of the groove structure is between 1um-8um, separation 1um-
Between 10um, groove depth is between 0.5um-1um.
In some embodiments of the present disclosure, the P++The doping concentration of the regions-SiC ring is higher than P+The regions-SiC ring and
The doping concentration of one CSL current transport layers；And/or Schottky contact electrode is formed by Mo, Al or lower barrier metal.
Present disclose provides a kind of production method of SiC trench junction barrier schottkies diode, which includes：It carries
For N+SiC substrate, in N+SiC substrate front grows N-SiC epitaxial layer, in N-Selective etch groove in SiC epitaxial layer；
In N-CSL current transport layers and N are made in SiC epitaxial layer+Field cut-off ring；On N--SiC epitaxial layers, shape is injected below groove
At P++Region and P+Field limiting ring region；N+-SiC substrate backs form back surface ohmic contacts；It is deposited in N--SiC epi-layer surfaces
SiO2And Schottky window is formed, Schottky contact electrode and field plate are formed, and grow encapsulation and thicken metal.
It is described in N in some embodiments of the present disclosure+SiC substrate front grows N-SiC epitaxial layer includes：It is adulterating
A concentration of 1018~1019cm-3Horizontal N+SiC substrate front utilizes CVD technique extensions N-SiC layer；The N-SiC epitaxial layer
Doped level is 5 × 1015cm-3~2 × 1016cm-3, thickness is 5~100 μm.
It is described in N in some embodiments of the present disclosure-Selective etch groove includes in SiC epitaxial layer：Using
SiO2、Si3N4Equal mask materials, simultaneously dry etching goes out selective notch window to photolithography patterning, is formed using dry etch process
Selective groove structure, the etching gas used are HBr, Cl2、SF6、O2In one kind or mixing.
It is described in N in some embodiments of the present disclosure-CSL current transport layers and N are made in SiC epitaxial layer+Field cut-off
Ring includes：In N-Barrier layer of the dielectric as N ion implantings is made in SiC epitaxial layer；In 200 DEG C~500 DEG C of temperature
N ions are carried out to be injected；Arbitrary combination of the N ion energies between 40kev~550kev；The N ion energies
It is 4 × 10 to inject accumulated dose12cm-2~1 × 1014cm-2Between；The high temperature after N ion implantings is carried out in atmosphere of inert gases to swash
Annealing living, it is 1300 DEG C~1700 DEG C to activate the temperature range of annealing, forms CSL current transport layers and N+Field cut-off ring.
In some embodiments of the present disclosure, in N-The SiC epitaxial layer last time injects to form P++Region and P+Field limiting ring area
Domain, including：Using insulating dielectric materials, selective ion implanting masking layer is made；Al is carried out in 200 DEG C~500 DEG C of temperature
Ion is injected；The P++It is Al ions that ion is injected in region, and Implantation Energy is 50kev~450kev, total injection of injection
Dosage is 1 × 1014cm-2~1 × 1015cm-2Between；The P+It is Al ions that ion is injected in field limiting ring region, and Implantation Energy is
Total implantation dosage of 50kev~450kev, injection are 1 × 1014cm-2~8 × 1014cm-2Between；In atmosphere of inert gases into
Row high temperature activation anneal forms P++Region and P+Field limiting ring region.
In some embodiments of the present disclosure, the N+Surface on back side of SiC substrate forms back surface ohmic contacts；Including：In N++-
The back side grows Ni metals in SiC substrate；In 900 DEG C~1000 DEG C temperature ranges, in vacuum environment or atmosphere of inert gases
Rapid thermal annealing is carried out, N is formed+The Ohmic contact of-SiC.
(3) advantageous effect
It can be seen from the above technical proposal that the disclosure has the advantages that：
(1) CSL transport layer structures are added using JBS groove structures, the metal that can neatly select potential barrier low is as Schottky
Contact, while increasing substantially forward conduction ability, and without worrying that reverse leakage current can increase；
(2) due to forming multiple first, second CSL current transport layers structures and N using a N-type ion implantation technology+
Cut-off ring, reduce the complexity of technique, reduce twice or repeatedly ion implantation technology introduce adverse effect factor can
It can property；
(3) when device forward direction works, the CSL transport layers structure below schottky metal can greatly increase current lead-through energy
Power reduces the temperature dependency and sensibility of device electrology characteristic；Meanwhile groove and P++CSL below the ring of the regions-SiC is transported
The P of layer respective outer side edges high concentration++The regions-SiC ring, is equivalent to N+- SiC locality protection rings, can effectively disperse P++The regions-SiC ring
The field distribution at edge plays the role of good protection in reverse breakdown.
Description of the drawings
Fig. 1 is the sectional view for the SiC trench junction barrier schottky diodes that the disclosure has CSL transport layers；
Fig. 2 to Fig. 9 is the disclosure, and there is the SiC trench junction barrier schottkies diode manufacturing method of CSL transport layers respectively to walk
Rapid schematic diagram；(a) of Fig. 2 shows N+- SiC linings show that (b) of Fig. 2 shows N+SiC substrate front grows N-- SiC extensions
Layer；(a) of Fig. 3 shows N-SiO is deposited in SiC epitaxial layer2Layer, (b) of Fig. 3 are shown in N-Selectivity in SiC epitaxial layer
Etched recesses；(a) of Fig. 4 shows erosion removal CSL current transport layers and N+SiO above field cut-off ring window2, Fig. 4's
(b) it shows to form CSL current transport layers and N+Field cut-off ring；(a) of Fig. 5 is shown in N-It is deposited again in SiC epitaxial layer
SiO2Layer is used as ion implantation mask, (b) of Fig. 5 to show to form P++Regioselectivity injects window；(a) of Fig. 6 is shown
In N-SiO is deposited in SiC epitaxial layer again2Layer is used as ion implantation mask, (b) of Fig. 6 to show to form P+Field limiting ring region
Selective implantation window；
Figure 10 is the flow chart for the SiC trench junction barrier schottky diode manufacturing methods that the disclosure has CSL transport layers.
Specific implementation mode
It is comprehensive that there is the disclosure SiC Schottky diode of CSL transport layers not injected deeply plus P++ only with groove technology
Conjunction technology reduces chip surface electric field, reduces the reduction effect of Schottky barrier, inhibits leakage current, and optimization is matched on this basis
It closes CSL transport layer structures and greatly increases current capacity, the temperature dependency and sensibility of device electrology characteristic are reduced, anti-
In the case of unaffected time of breakdown characteristics, high temperature high current SiC power electronic devices is obtained, it is simple for process, repeatable, it can
Applied to fields such as the new energy vehicle of " efficient, energy saving ", urban track traffic, photovoltaic, wind-powered electricity generation, industrial motors.
Below in conjunction with the attached drawing in embodiment and embodiment, to the technical solution in the embodiment of the present disclosure carry out it is clear,
Complete description.Obviously, described embodiment is only disclosure a part of the embodiment, instead of all the embodiments.Base
Embodiment in the disclosure, it is obtained by those of ordinary skill in the art without making creative efforts it is all its
His embodiment belongs to the range of disclosure protection.
The embodiment of the present disclosure provides a kind of structure of the SiC trench junction barrier schottky diodes with CSL transport layers
Figure, as shown in Figure 1, SiC trench junction barrier schottky diodes include：N+SiC substrate, N-SiC epitaxial layer, N-type Ohmic contact
Layer, CSL current transport layers, P++The regions-SiC ring, P+- SiC protection rings, N+Field cut-off ring, Schottky contact electrode, SiO2Passivation
Layer and field plate.
N-SiC epitaxial layer is formed in N+SiC substrate front, the N-type ohmic contact layer are formed in N+SiC substrate is carried on the back
Face.
CSL current transport layers are formed in the N-In SiC epitaxial layer, including two parts：Multiple first CSL current transfers
Layer and multiple 2nd CSL current transport layers, the first CSL current transport layers and the 2nd CSL current transport layers are spaced.
Selective P on first CSL current transport layers++The regions-SiC ring, P++If being corresponding on the ring of the regions-SiC
The groove of spacing is done, has Schottky contact electrode on groove structure.Directly it is that schottky junctions are got an electric shock on 2nd CSL current transport layers
Pole.
Schottky contact electrode periphery is equipped with multiple P+- SiC protection rings and a N+Field cut-off ring.
Schottky contact electrode edge is equipped with SiO2Passivation layer, SiO2Passivation layer covers multiple P+- SiC protection rings and one
A N+Field cut-off ring.In SiO2Field plate is equipped with above passivation layer.
The disclosure applies the SiC trench junction barrier schottky diodes with CSL transport layers of example, the N--SiC epitaxial layers
On there are two parts CSL current transport layers all can effectively extend high current, optimize current conducting path, prevent high current crowding effect
With promotion high current ducting capacity；Selective P on first CSL current transport layers++The regions-SiC ring, P++On the ring of the regions-SiC
It is the groove of corresponding several spacing, as the P for reducing electric field at schottky interface++- SiC adds groove complex protection knot
Structure；There are Schottky contacts on the CSL current transport layers and groove structure, the Schottky contact metal is by low Schottky barrier
Metal is formed, and low Schottky metal is filled in slot, reduces cut-in voltage, increases schottky area；Outside the Schottky contacts
It encloses and is equipped with multiple P+- SiC protection rings, the terminal protection structure as the diode component.
The CSL current transport layers, when device forward direction works, the first CSL current transport layers and the 2nd CSL current transfers
Layer can greatly increase current capacity, reduce the temperature dependency and sensibility of device electrology characteristic；When device reverse operation,
Groove structure and P++The regions-SiC ring is combined, and can reduce device surface potential barrier reduces effect；Meanwhile the P++The regions-SiC
There are corresponding first CSL current transport layers (to be equivalent to N below ring+- SiC locality protections ring), it can effectively disperse P+The areas-SiC
The field distribution at domain ring edge, plays the role of good protection in reverse breakdown.
Another embodiment of the disclosure provides a kind of SiC trench junction barrier schottky diodes with CSL transport layers
Production method, as shown in Figure 10, the production method include the following steps：
N is provided+SiC substrate, in N+SiC substrate front grows N-SiC epitaxial layer, in N-Selectivity in SiC epitaxial layer
Etched recesses.
In N-CSL current transport layers and N are made in SiC epitaxial layer+Field cut-off ring
In N-In SiC epitaxial layer, P is formed+Field limiting ring region and the reeded P of tool++Region.
N+Surface on back side of SiC substrate forms back surface ohmic contacts,
In N-SiC epitaxial layer surface deposition SiO2And Schottky window is formed, Schottky contact electrode and field plate are formed, and
Growth encapsulation thickeies metal.
Specifically, above-mentioned production method includes：
Step 1：N is provided+SiC substrate, as shown in (a) of Fig. 2, in N+SiC substrate front grows N-SiC epitaxial layer,
As shown in (b) of Fig. 2.
It is 10 in doping concentration18~1019cm-3Horizontal N+SiC substrate front utilizes CVD technique extensions N-SiC layer, institute
State N-SiC epitaxial layer doped level is 5 × 1015cm-3~2 × 1016cm-3, thickness is 5~100 μm, it is preferable that it adulterates water
Put down is 1 × 1016cm-3, thickness 11um.
Step 2：In N-Selective etch groove in SiC epitaxial layer, as shown in Figure 3.
As shown in (a) of Fig. 3, in N-SiO is deposited in SiC epitaxial layer2Layer.Preferably, using pecvd process to SiO2Layer
It is deposited.Preferably, SiO2Layer thickness be
Then, as shown in (b) of Fig. 3, in SiO2Spin coating photoresist on layer passes through photoetching and dry etching SiO2Technology, it is real
Present N-Selective etch groove in SiC epitaxial layer, depth of groove are 1 μm.Between the groove groove width 1um-8um, separation
Between 1um-10um, between groove depth 0.5um-1um.Using SiO2、Si3N4Equal mask materials, first photolithography patterning and dry etching
Go out selective notch window, selective groove structure is formed using dry etch process, the etching gas used is HBr, Cl2In
One kind or any mixture, it may also be necessary to add SF6、O2Equal gases.
Step 3：In N-CSL current transport layers and N are made in SiC epitaxial layer+Field cut-off ring, as shown in Figure 4.
As shown in (a) of Fig. 4, N is completed-In SiC epitaxial layer after selective etch groove, using photoetching technique, corrosion
Remove CSL current transport layers and N+SiO above field cut-off ring window2。
As shown in (b) of Fig. 4, the SiO that leaves2As ion implantation mask, in the environment of 500 DEG C of temperature, carry out not
Co-energy and dosage combination N ion boxes are injected, and CSL current transport layers and N are formed+Field cut-off ring, doping concentration are
8E16cm-3, injection depth is 1 μm.
Specifically, first in N-Dielectric SiO is made in SiC epitaxial layer2Barrier layer as N ion implantings.
N ions are carried out in 200 DEG C~500 DEG C of temperature to be injected.
Arbitrary combination of the N ion energies between 40kev~550kev；The injection accumulated dose of the energy is 4
×1012cm-2~1 × 1014cm-2Between.
The high temperature activation anneal after N ion implantings is carried out in atmosphere of inert gases, activates the temperature range of annealing to be
1300 DEG C~1700 DEG C, form N+Ring is ended in-SiC CSL current transport layers and field.
Step 4：It is injected on N--SiC epitaxial layers, below groove and forms the regions P++ and P+Field limiting ring region.
As shown in (a) of Fig. 5, in N-SiO is deposited in SiC epitaxial layer again2Layer is used as ion implantation mask.Preferably,
Using pecvd process to SiO2Layer is deposited, and thickness is
Then, as shown in (b) of Fig. 5, in SiO2Spin coating photoresist on layer passes through photoetching and dry etching SiO2Technology, shape
At P++Regioselectivity injects window, in the environment of 500 DEG C of temperature, carries out the Al ion boxes of different-energy and dosage combination
Injection, doping concentration 2E19cm-3, injection depth is 0.5 μm.
As shown in (a) of Fig. 6, in N-SiO is deposited in SiC epitaxial layer again2Layer is used as ion implantation mask.Preferably,
Using pecvd process to SiO2Layer is deposited, and thickness is
Then, as shown in (b) of Fig. 6, in SiO2Spin coating photoresist on layer, by photoetching and dry etching SiO2 technologies,
Form P+Field limiting ring regioselectivity injects window, in the environment of 500 DEG C of temperature, carries out the Al of different-energy and dosage combination
Ion box is injected, doping concentration 8E18cm-3, injection depth is 0.5 μm.
Finally, the laggard line activating annealing of this ion implanting is completed, for activating step 3, step 4, step 5 intermediate ion note
Enter region, activation annealing temperature is 1700 DEG C, time 30min.
This step can also N-The SiC epitaxial layer last time injects to form P++Region and P+Field limiting ring region, including：
Using insulating dielectric materials, selective ion implanting masking layer is made, insulating dielectric materials can be SiO2, polycrystalline
It is one or more in silicon, non-crystalline silicon；
Al ions are carried out in 200 DEG C~500 DEG C of temperature to be injected；
The P++The regions-SiC ring injection ion is Al ions, and the Implantation Energy is 50kev~450kev；The note
The total implantation dosage entered is 1 × 1014cm-2~1 × 1015em-2Between.
The P+It is Al ions that-SiC protection rings, which inject ion, and the Implantation Energy is 50kev~450kev；The note
The total implantation dosage entered is 1 × 1014cm-2~8 × 1014cm-2Between.
The high temperature activation anneal after Al ion implantings is carried out in atmosphere of inert gases, activates the temperature range of annealing to be
1600 DEG C~1850 DEG C, form P++The regions-SiC ring and multiple P+-SiC protection rings.
Step 5：N+Surface on back side of SiC substrate forms back surface ohmic contacts, as shown in Figure 7.
By sputtering technology in N+Surface on back side of SiC substrate grows Ni metals, thicknessUsing rapid thermal anneal process,
In 900 DEG C~1000 DEG C temperature ranges, rapid thermal annealing is carried out in vacuum environment or atmosphere of inert gases, forms N+-SiC
Ohmic contact.Preferably, in nitrogen atmosphere, at a temperature of 950 DEG C, the rapid thermal annealing of 5min is carried out, is connect with forming ohm
It touches.
Step 6：In N-SiC epitaxial layer surface deposition SiO2, Schottky window is formed, as shown in Figure 8.
Using thermal oxidation technology in SiO2Upper growthSiO2, recycle pecvd process to be deposited in sample surfaces thick
Degree isSiO2.Using photoetching technique, corrode SiO2Trepanning reserves Schottky window.
Step 7：Schottky contact electrode and field plate are formed, and grows encapsulation and thickeies metal, as shown in Figure 9.
Grow schottky metal Ti, thicknessUsing rapid thermal anneal process, in nitrogen atmosphere, 500 DEG C of temperature
Under, the rapid thermal annealing of 5min is carried out, Schottky contact electrode and field plate are formed.Finally, 4 μm are grown using evaporation of metal technique
Encapsulation thickeies metal Al.
It can also all be Al metals, schottky metal 2000A, encapsulation thickening that the schottky metal and encapsulation, which thicken metal,
4μm。
In the preparation method of the embodiment of the present disclosure, the CSL current transport layers are formed using extensional mode,
But formed using N-type ion implanting mode, including N ions and P ion injection, from Schottky pole, groove and P++The regions-SiC
Ring uses Gauss to inject distribution form down, and maximum concentration is no more than 20 times of substrate concentration, and doping concentration is preferably 8E16cm-3-1E18cm-3Between；It injects depth and is more than 0.5um or more, be less than N--SiC epitaxy layer thickness.
The N+Field cut-off ring injects to be formed together with CSL current transport layers, simple for process without increasing other technique,
It is repeatable.The P++The regions-SiC ring is not and P+- SiC protection rings inject to be formed together, and doping concentration is higher than P+- SiC is protected
Retaining ring, while its doping concentration necessarily also is greater than P++Corresponding first CSL current transport layers mixes below the ring of the regions-SiC
Miscellaneous concentration.
The Schottky contacts are formed using low barrier schottky metal low temp annealing process, metal can by Mo, Al or
Person is lower, and barrier metal is formed, and conducting voltage is about 0.8V or 0.8V or less.The low temperature annealing process can make metal with
The contact of SiC is partial to the class Schottky contacts of Schottky contacts between Schottky contacts and Ohmic contact, in this way can be with
Increase substantially forward conduction ability, due to reeded presence, surface of SiC electric field can be greatly lowered, device it is reversed
Blocking capability can also be protected, and the temperature range of low temperature annealing process is 400-900 degree, time 2min-30min.
So far, attached drawing is had been combined the present embodiment is described in detail.According to above description, those skilled in the art
There should be clear understanding to the disclosure.
It should be noted that in attached drawing or specification text, the realization method for not being painted or describing is affiliated technology
Form known to a person of ordinary skill in the art, is not described in detail in field.In addition, above-mentioned definition to each element and not only limiting
Various concrete structures, shape or the mode mentioned in embodiment, those of ordinary skill in the art can carry out simply more it
Change or replaces, such as：
(1) direction term mentioned in embodiment, such as "upper", "lower", "front", "rear", "left", "right" etc. are only ginsengs
The direction of attached drawing is examined, not is used for limiting the protection domain of the disclosure；
(2) above-described embodiment can be based on the considerations of design and reliability, and the collocation that is mixed with each other uses or and other embodiment
Mix and match uses, i.e., the technical characteristic in different embodiments can freely form more embodiments.
Particular embodiments described above has carried out further in detail the purpose, technical solution and advantageous effect of the disclosure
It describes in detail bright, it should be understood that the foregoing is merely the specific embodiment of the disclosure, is not limited to the disclosure, it is all
Within the spirit and principle of the disclosure, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the disclosure
Within the scope of shield.
Claims (10)
1. a kind of SiC trench junction barrier schottky diodes with CSL transport layer structures, including：
N++SiC substrate；
N-SiC epitaxial layer is formed in the N++SiC substrate front；
The N+Surface on back side of SiC substrate is equipped with N-type Ohmic contact；
It is characterized in that：
Further include：CSL current transport layers are formed in the N-In SiC epitaxial layer, including：Multiple first CSL current transport layers and
Multiple 2nd CSL current transport layers, the first CSL current transport layers and the 2nd CSL current transport layers are spaced；
Selective P on first CSL current transport layers++The regions-SiC ring, P++It is corresponding groove knot on the ring of the regions-SiC
Structure has Schottky contact electrode on groove structure；Directly it is Schottky contact electrode on 2nd CSL current transport layers；
Schottky contact electrode periphery is equipped with multiple P+- SiC protection rings and a N+ cut-off rings；
Schottky contact electrode edge is equipped with SiO2Passivation layer；
In SiO2Field plate is equipped with above passivation layer.
2. SiC trench junction barrier schottkies diode according to claim 1, it is characterised in that：
The doping concentration of the CSL current transport layers is 8E16cm-3-1E18cm-3Between, injection depth is more than 0.5um, is less than
N-SiC epitaxial layer thickness；And/or
Multiple first CSL current transport layers, the 2nd CSL current transport layers and N+ cut-off rings inject to be formed together.
3. SiC trench junction barrier schottkies diode according to claim 1, it is characterised in that：
The groove width of the groove structure is between 1um-8um, and separation is between 1um-10um, and groove depth is between 0.5um-1um.
4. SiC trench junction barrier schottkies diode according to claim 1, it is characterised in that：
The P++The doping concentration of the regions-SiC ring is higher than P+The doping concentration of the regions-SiC ring and the first CSL current transport layers；
And/or
Schottky contact electrode is formed by Mo, Al or lower barrier metal.
5. a kind of production method of SiC trench junction barrier schottkies diode, which is characterized in that the production method includes：
N is provided+SiC substrate, in N+SiC substrate front grows N-SiC epitaxial layer, in N-Selective etch in SiC epitaxial layer
Groove；
In N-CSL current transport layers and N are made in SiC epitaxial layer+Field cut-off ring；
In N-It is injected in SiC epitaxial layer, below groove and forms P++Region and P+Field limiting ring region；
N+Surface on back side of SiC substrate forms back surface ohmic contacts；
In N-SiC epitaxial layer surface deposition SiO2And Schottky window is formed, Schottky contact electrode and field plate are formed, and grow
Encapsulation thickeies metal.
6. production method according to claim 5, which is characterized in that described in N+SiC substrate front grows N-Outside-SiC
Prolonging layer includes：
It is 10 in doping concentration18~1019cm-3Horizontal N+SiC substrate front utilizes CVD technique extensions N-SiC layer；It is described
N-SiC epitaxial layer doped level is 5 × 1015cm-3~2 × 1016cm-3, thickness is 5~100 μm.
7. production method according to claim 5, which is characterized in that the selective etch on N--SiC epitaxial layers is recessed
Slot includes：
Using SiO2、Si3N4Equal mask materials, simultaneously dry etching goes out selective notch window to photolithography patterning, using dry etching
Technique forms selective groove structure, and the etching gas used is HBr, Cl2、SF6、O2In one kind or mixing.
8. production method according to claim 5, which is characterized in that described in N-It is defeated that CSL electric currents are made in SiC epitaxial layer
Transport layer and N+End ring in field：
In N-Barrier layer of the dielectric as N ion implantings is made in SiC epitaxial layer；
N ions are carried out in 200 DEG C~500 DEG C of temperature to be injected；
Arbitrary combination of the N ion energies between 40kev~550kev；The injection accumulated dose of the N ion energies be 4 ×
1012cm-2~1 × 1014cm-2Between；
The high temperature activation anneal after N ion implantings is carried out in atmosphere of inert gases, it is 1300 DEG C to activate the temperature range of annealing
~1700 DEG C, form CSL current transport layers and N+Field cut-off ring.
9. production method according to claim 5, which is characterized in that in N-The SiC epitaxial layer last time injects to form P++Area
Domain and P+Field limiting ring region, including：
Using insulating dielectric materials, selective ion implanting masking layer is made；
Al ions are carried out in 200 DEG C~500 DEG C of temperature to be injected；
The P++It is Al ions that ion is injected in region, and Implantation Energy is 50kev~450kev, total implantation dosage of injection is 1 ×
1014cm-2~1 × 1015cm-2Between；
The P+It is Al ions that ion is injected in field limiting ring region, and Implantation Energy is 50kev~450kev, total implantation dosage of injection
It is 1 × 1014cm-2~8 × 1014cm-2Between；
High temperature activation anneal is carried out in atmosphere of inert gases, forms P++Region and P+Field limiting ring region.
10. production method according to claim 5, which is characterized in that the N+Surface on back side of SiC substrate forms back ohmic and connects
It touches；Including：
In N++The back side grows Ni metals in SiC substrate；
In 900 DEG C~1000 DEG C temperature ranges, rapid thermal annealing is carried out in vacuum environment or atmosphere of inert gases, forms N+-
The Ohmic contact of SiC.
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