CN113299735B - Semiconductor device terminal structure with slope and manufacturing method thereof - Google Patents
Semiconductor device terminal structure with slope and manufacturing method thereof Download PDFInfo
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- CN113299735B CN113299735B CN202110515569.1A CN202110515569A CN113299735B CN 113299735 B CN113299735 B CN 113299735B CN 202110515569 A CN202110515569 A CN 202110515569A CN 113299735 B CN113299735 B CN 113299735B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A semiconductor device terminal structure with a slope and a manufacturing method thereof are provided, the structure comprises: the slope structure formed by the semiconductor after dry etching is positioned at the periphery of the active region of the semiconductor device, the length of the slope structure is larger than 100 micrometers, and the height of the slope structure is smaller than 10 micrometers. The structure also comprises a trench structure and a filling medium, or also comprises an injection structure or a field plate structure or any combination thereof. The groove structure is formed by etching a semiconductor by a dry method and is positioned at the periphery of the slope structure; the filling medium is a filling material positioned in the groove structure; the implantation structure is formed by ion implantation on the semiconductor, and the implanted region contains the surface of the slope structure; the field plate structure is formed by introducing a conductor on the surface of the semiconductor, a passivation layer can be contained between the conductor and the semiconductor, and the conductor covering region contains the surface of the slope structure. The invention consumes smaller chip area under the same voltage-resistant grade, and can be widely applied to materials such as silicon carbide and the like which are difficult to wet-process corrosion and difficult to thermally diffuse after ion implantation.
Description
Technical Field
The invention belongs to the field of semiconductor power chips, and particularly relates to a semiconductor device terminal structure with a slope and a manufacturing method thereof.
Background
In a semiconductor device, in order to reduce a high electric field at the edge of the device due to a curvature effect, a terminal structure of an optimal design is required. For some semiconductors that are relatively inert in physical and chemical properties, such as silicon carbide, it is difficult to perform wet etching like silicon, so ion implantation or step etching is generally used to form the termination structure. For high voltage devices, an ideal termination should form a lateral profile with a graded doping concentration. However, since the thermal diffusion rate of doping after ion implantation of a material such as silicon carbide is extremely low, such a graded profile cannot be formed by thermal diffusion as in silicon. Therefore, for silicon carbide high voltage devices, large area implantation, multiple rounds of implantation or multi-step etching are often required, and therefore, these methods either require a large terminal area, or require a long process cycle or high process cost, which greatly increases the manufacturing cost of the devices.
Disclosure of Invention
The invention aims to provide a terminal structure with a slope and a manufacturing method thereof, which have low manufacturing cost, consume smaller chip area under the same voltage-resistant level and can be widely applied to materials such as silicon carbide and the like which are difficult to wet-process corrosion and difficult to thermally diffuse after ion implantation.
The above object of the present invention is achieved by the following means.
In the context of the present invention, for the sake of brevity, the following terms are used, wherein:
"ramp" means a structure that macroscopically has a cross-section characterized by a high on one side and a low on the other side. The shape of the middle of the two sides can comprise a straight line, a broken line, a curved line and can also have undulation. But not by a few flat steps of different structure heights, wherein a few means less than ten.
"dry etching" is a concept opposite to "wet etching" and refers to an etching method in which the etching action on the etching body does not originate from liquid chemicals. The present invention relates to a method for etching a semiconductor substrate, and more particularly to a method for etching a semiconductor substrate.
The term "structure length" refers to the dimension parallel to the original surface of the semiconductor being processed.
"feature height" refers to the dimension perpendicular to the original surface of the semiconductor being processed.
The "active region" refers to a portion of the semiconductor device surrounded by the termination structure. The active region of most devices is used to participate in conduction, while the termination structure is used to improve withstand voltage when the device is blocked.
By "graded design" is meant that the pattern has a graded feature in size, or spacing, or material thickness, or material areal density.
The invention provides a semiconductor device terminal structure with a slope, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, and has a structure length of more than 100 micrometers and a structure height of less than 10 micrometers;
the groove structure is formed by etching a semiconductor by a dry method and is positioned at the periphery of the slope structure; and
and the filling medium is filled with filling materials in the groove structure.
The present invention also provides a semiconductor device terminal structure with a slope, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, and has a structure length of more than 100 micrometers and a structure height of less than 10 micrometers; and
and an implanted structure formed by ion implantation on the semiconductor, the implanted region including a surface of the ramp structure.
The present invention also provides a semiconductor device terminal structure with a slope, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, and has a structure length of more than 100 micrometers and a structure height of less than 10 micrometers; and
and the field plate structure is formed by introducing a conductor on the surface of the semiconductor, the conductor is in direct contact with the semiconductor or is in contact with the semiconductor through a passivation layer, and the conductor covering region comprises the surface of the slope structure.
The present invention also provides a semiconductor device terminal structure with a slope, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, and has a structure length of more than 100 micrometers and a structure height of less than 10 micrometers;
the groove structure is formed by etching a semiconductor by a dry method and is positioned at the periphery of the slope structure;
the filling medium is filled with filling materials in the groove structure; and
and the implantation structure is formed by ion implantation on the semiconductor, and the implantation area contains the surface of the slope structure or the surface of the groove structure.
The present invention also provides a semiconductor device terminal structure with a slope, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, and has a structure length of more than 100 micrometers and a structure height of less than 10 micrometers;
the groove structure is formed by etching a semiconductor by a dry method and is positioned at the periphery of the slope structure;
the filling medium is filled with filling materials in the groove structure; and
and the field plate structure is formed by introducing a conductor on the surface of the semiconductor, wherein the conductor is in direct contact with the semiconductor or is in contact with the semiconductor through a passivation layer, and the conductor covering region comprises the surface of the slope structure or the surface containing the filling medium.
The present invention also provides a semiconductor device terminal structure with a slope, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, and has a structure length of more than 100 micrometers and a structure height of less than 10 micrometers;
an implanted structure formed by ion implantation on a semiconductor, the implanted region including a surface of the ramp structure or a surface of the trench structure; and
and the field plate structure is formed by introducing a conductor on the surface of the semiconductor, wherein the conductor is in direct contact with the semiconductor or is in contact with the semiconductor through a passivation layer, and the conductor covering region comprises the surface of the slope structure or the surface containing the filling medium.
The present invention also provides a semiconductor device terminal structure with a slope, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, and has a structure length of more than 100 micrometers and a structure height of less than 10 micrometers;
the groove structure is formed by etching a semiconductor by a dry method and is positioned at the periphery of the slope structure;
the filling medium is filled with filling materials in the groove structure;
the field plate structure is formed by introducing a conductor on the surface of the semiconductor, the conductor is in direct contact with the semiconductor or is in contact with the semiconductor through a passivation layer, and the conductor covering region comprises the surface of the slope structure or the surface containing the filling medium; and
and the implantation structure is formed by ion implantation on the semiconductor, and the implantation area contains the surface of the slope structure or the surface of the groove structure.
The invention also provides a manufacturing method of the slope structure in the terminal structure, which comprises the following steps:
coating a layer of photoresist on the surface of the semiconductor;
placing a photolithography plate with a gradual change design above the photoresist;
exposing the photoresist through the photoetching plate;
putting the semiconductor and the photoresist covered on the semiconductor into a developing solution;
heating the developed semiconductor and the residual photoresist on the developed semiconductor together until the photoresist locally flows and forms a photoresist slope, wherein the structural length of the photoresist slope is more than 100 micrometers;
putting the semiconductor and the photoresist slope on the semiconductor into a dry etching device; and
and removing the photoresist slope and part of the semiconductor by dry etching to finally form a semiconductor slope structure.
The present invention also provides a method for manufacturing the injection structure in the above terminal structure, including:
in the forming process of the active region of the semiconductor device, an ion implantation step is used;
the implantation structure is formed by utilizing or partially utilizing an ion implantation step used in the formation of the active region of the semiconductor device.
The invention also provides a manufacturing method of the field plate structure in the terminal structure, which comprises the following steps:
in the forming process of the active region of the semiconductor device, a conductor deposition or growth step is used; and
the field plate structure is formed using, or in part using, conductor deposition or growth steps used during the formation of the active region of the semiconductor device.
The invention has the following beneficial effects:
in the terminal structure, the slope structure has charges distributed in a gradual change mode, so that the effect of smoothing a surface electric field can be achieved under the condition of small chip area consumption, and the withstand voltage of a device is improved.
Meanwhile, the manufacturing method of the slope structure does not use wet etching, ion implantation or doping thermal diffusion, so that the method is suitable for materials such as silicon carbide and the like which are difficult to wet etching and thermal diffusion after ion implantation.
In addition, compared with a structure formed by multiple etching or injection, the structure provided by the invention can be formed in one round, so that the process time and the equipment cost are greatly reduced.
Drawings
The technical process of the invention is further illustrated with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a terminal structure with a ramp structure according to the present invention, wherein (a) is a cross-sectional view and (b) is a top view;
FIG. 2 is a schematic top view of another example of a possible configuration of a termination structure with a ramp structure according to the present invention;
FIG. 3 is a schematic diagram of a terminal structure with a ramp structure and a trench structure according to the present invention, wherein (a) is a cross-sectional view and (b) is a top view;
FIG. 4 is a schematic cross-sectional view of another exemplary possible termination structure with a ramp structure and a trench structure according to the present invention;
FIG. 5 is a schematic top view of another exemplary termination structure with a ramp structure and a trench structure according to the present invention;
FIG. 6 is a schematic cross-sectional view of an example of one possible implementation of a termination structure with a ramp structure and an implant structure in accordance with the present invention;
fig. 7 is a schematic cross-sectional view of an example of one possible case of a termination structure with a ramp structure and a field plate structure according to the present invention;
fig. 8 is a schematic cross-sectional view of another exemplary possible termination structure with a ramp structure and a field plate structure according to the present invention;
fig. 9 is a schematic cross-sectional view of an example of one possible implementation of a termination structure with a ramp structure, an implant structure, and a field plate structure in accordance with the present invention;
FIG. 10 is a schematic cross-sectional view of an example of one possible implementation of a termination structure with a ramp structure, an implant structure, and a trench structure in accordance with the present invention;
fig. 11 is a schematic cross-sectional view of an example of one possible case of a termination structure with a ramp structure, a field plate structure and a trench structure according to the present invention;
fig. 12 is a schematic cross-sectional view of an example of one possible implementation of a termination structure with a ramp structure, an implant structure, a field plate structure, and a trench structure in accordance with the present invention;
FIG. 13 is a partial photomicrograph of a reticle with a graded design according to the present invention;
fig. 14 is a result of a ramp experiment test finally formed by the ramp structure manufacturing method of the present invention, in which each line represents a ramp, and there are five ramps with different slopes;
fig. 15 shows the computer simulation results of one of the terminal structures of the present invention, in which (a) is the lateral electric field distribution under the interface, (b) is the voltage withstand curve, and A, B, C has terminal slope lengths of 120, 180, and 300 μm, respectively.
Description of reference numerals:
1 processed semiconductor
2 slope structure
2b a slope structure with a gap
2c a slope structure with a notch, and a side wall of the notch having an inclination angle
3 periphery of slope structure
4 active region of device
5 structural height
6 structural length
7 bottom of trench structure
7b bottom of trench structure with trench sidewall having dip angle
7c bottom of trench structure, trench sidewall with another slope angle
7d a groove structure with a gap
7e a groove structure with a notch, a side wall of the notch having an inclination angle
Filling medium in 8-groove structure
8b filling medium in trench structure, trench sidewall having inclination angle
Filling medium in 8c groove structure, the side wall of the groove has another inclination angle
9 side wall of trench structure
9b side walls of the trench structure, the trench side walls having an inclination angle
9c side walls of the trench structure with another tilt angle
10-injection structure
10b another region implantation structure
11 field plate structure
11b field plate structure in another region
12 passivation layer
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example 1
The present embodiments provide a termination structure for a silicon carbide semiconductor power device, the semiconductor itself having two or more layers of differently doped epitaxy. In this embodiment, the terminal structure adopts a slope structure, i.e., a layer of the terminal structure is epitaxially formed with a gradually changing slope, as shown in fig. 1. For an eight kv sic power device, a preferred ramp has a structure length of between 100 and 200 microns and a structure height that varies depending on the doping concentration, typically between 1 and 5 microns.
The manufacturing method of the slope structure comprises the following steps:
and coating a layer of photoresist on the surface of the semiconductor. Here, the photoresist should be coated as uniformly as possible, and for convenience of subsequent etching, the photoresist with a thicker coating layer should be selected. To enhance the adhesion of the coating, it is also possible to carry out an adhesive spray before the coating, such as hexamethyldisilazane; other mask growth processes, such as silicon oxide or silicon nitride, may also be performed prior to coating in order to enhance the final etch depth.
A reticle with a graded design is placed over the photoresist. The main body of the photolithography panel used in this embodiment is transparent glass, which is covered with a chromium metal layer to partially block light. The gradual change design is realized through the pattern size and the density of the chromium metal layer. FIG. 13 is a photomicrograph of a real object of a reticle of the gradation design according to this embodiment.
And exposing the photoresist through the photoetching plate. In the embodiment, non-contact exposure is adopted, so as to leave a certain distance, enhance diffraction and interference effects, and enable the exposure pattern to form a smoother transition effect.
The semiconductor and the photoresist covered thereon are placed into a developing solution together. In order to keep the incompletely exposed photoresist, the developing time is not longer. In this embodiment, the development time is controlled within one minute.
The developed semiconductor is heated with the remaining photoresist until the photoresist locally flows and a photoresist ramp is formed. Here, the surface topography of the possible unevenness is improved by utilizing a certain degree of fluidity of the photoresist after heating. In order to improve the voltage endurance, the reasonable ramp structure length is greater than 100 μm, so the photoresist ramp should have a similar length.
And putting the semiconductor and the photoresist slope on the semiconductor into a dry etching device. This step is performed by etching using the photoresist as a mask. Because the photoresist is in a slope shape, a slope structure can be obtained on the etched semiconductor and is used as a part of the terminal. In this embodiment, the photoresist slope and a portion of the semiconductor are removed by plasma etching, and finally, a semiconductor slope structure is formed.
Since the slope is formed by the pattern of the gradual change design on the photolithography mask, different overall shapes, such as rounded rectangles, circles, rectangles, etc., can be formed by changing the overall layout of the pattern, and the different layouts can also include notches, etc., as shown in fig. 2. This ability to form a rounded layout, forming different indentations, is also another advantage of the manufacturing scheme.
Example 2
This example provides a termination structure for a silicon carbide semiconductor power device, the ramp structure of which is based in part on example 1, while also containing a trench structure, as shown in fig. 3. The trench structure is formed by a single high selectivity dry etch and then backfilled with an insulating fill dielectric such as silicon oxide, silicon nitride, polyimide, benzocyclobutene, or the like. Preferably, the filling medium is a medium with high dielectric constant and high breakdown field strength, so that the potential line diffusion at the periphery of the slope can be reduced, and the purpose of saving the chip area is achieved. Meanwhile, the groove structure can improve the electric field distribution at the edge of the slope to a certain degree, and the effect of improving the withstand voltage or the yield is achieved.
Ion implantation or other doping may also be performed at the trench sidewalls or bottom if further improvement in the electric field profile is desired. If the surface appearance of the groove needs to be further improved, the modes of plasma etching, thermal oxidation and the like can be adopted.
Furthermore, the trench structure may also be used directly on a ramp structure, as shown in fig. 4. Thus, for some longer ramp structures, the local electric field can be adjusted by the trench structure therein. The trench sidewalls may also be sloped or curved, thus further increasing the ability to control the local electric field.
Example 3
This example provides a termination structure for a silicon carbide semiconductor power device having a ramp structure based in part on example 1, and also having an implant structure, as shown in fig. 6. The implanted structure is completed by a separate ion implantation, typically followed by a high temperature annealing step. The purpose of injection is to introduce different doping, regulate and control the charge distribution on the surface and improve the voltage endurance or yield of the device. The number of the ion implantation regions may be one or more. The injection region may be on the ramp or at the periphery of the ramp. In this embodiment, the implanted ions are aluminum, and the annealing temperature after implantation is 1700 ℃. In addition, the implanted ions can also be selected from boron, phosphorus, nitrogen and other elements.
Example 4
This example provides a termination structure for a silicon carbide semiconductor power device, the ramp structure of which is partially based on example 1, and which also contains a field plate structure, as shown in fig. 7. The field plate structure is completed by a separate conductor deposition or growth, commonly used as metal or polysilicon. The purpose of the field plate is to form a local equipotential body and regulate and control the charge distribution on the surface. The field plate structure can be one or more. The field plate structure can be arranged on the slope or at the periphery of the slope. The field plate structure may or may not be connected to other electrodes of the semiconductor.
In addition, an insulating material may be deposited as a passivation layer under the field plate structure, as shown in fig. 8. In this example, the passivation layer is silicon dioxide and has a thickness of 1 micron. In addition, the passivation layer can also be selected from silicon nitride, aluminum oxide, aluminum nitride and the like.
Example 5
This example provides a termination structure for a silicon carbide semiconductor power device, which has a ramp structure based in part on example 1, and also includes an implant structure and a field plate structure, as shown in fig. 9. The formation and operation of the implantation structure are based on example 3, and the formation and operation of the field plate structure are based on example 4. By combining the two, the control capability of the terminal on the surface electric field can be further improved.
Example 6
This example provides a termination structure for a silicon carbide semiconductor power device, the ramp structure of which is partially based on example 1, and which also contains an implant structure and a trench structure, as shown in fig. 10. The formation and operation of the implantation structure are based on example 3, and the formation and operation of the trench structure are based on example 2. By combining the two, the control capability of the terminal on the surface electric field can be further improved.
Alternatively, a partial or full ion implantation may be performed in the trench structure at the sidewall or bottom of the trench along with the formation of the implant structure. Therefore, the two structures can share one-time injection, and injection dose distribution is formed on the surface of the slope and the side wall of the groove, so that extra electric field regulation and control capacity is brought. This corresponds to an improvement in the performance of the terminal without increasing the cost.
Example 7
This example provides a termination structure for a silicon carbide semiconductor power device, the ramp structure of which is partially based on example 1, and which also includes a field plate structure and a trench structure, as shown in fig. 11. The field plate structure is formed in a manner and functions based on example 4, and the trench structure is formed in a manner and functions based on example 2. By combining the two, the control capability of the terminal on the surface electric field can be further improved.
Optionally, the field plate structure may be formed in the trench structure with partial or full field plate coverage over the trench fill dielectric. Therefore, the two structures can share a primary field plate forming process, and field plate equipotential bodies are formed on the surface of the slope and above the groove, so that extra electric field regulation and control capacity is brought. This corresponds to an improvement in the performance of the terminal without increasing the cost.
Example 8
This example provides a termination structure for a silicon carbide semiconductor power device, which has a ramp structure based in part on example 1, and further includes a field plate structure, an implant structure, and a trench structure, as shown in fig. 12. The formation and operation of the implantation structure are based on example 3, the formation and operation of the field plate structure are based on example 4, and the formation and operation of the trench structure are based on example 2. The control capability of the terminal on the surface electric field can be further improved through the combination of the three.
Alternatively, a partial or full ion implantation may be performed in the trench structure at the sidewall or bottom of the trench along with the formation of the implant structure. Therefore, the two structures can share one-time injection, and injection dose distribution is formed on the surface of the slope and the side wall of the groove, so that extra electric field regulation and control capacity is brought. This corresponds to an improvement in the performance of the terminal without increasing the cost.
Optionally, the field plate structure may be formed in the trench structure with partial or full field plate coverage over the trench fill dielectric. Therefore, the two structures can share a primary field plate forming process, and field plate equipotential bodies are formed on the surface of the slope and above the groove, so that extra electric field regulation and control capacity is brought. This corresponds to an improvement in the performance of the terminal without increasing the cost.
Example 9
This example demonstrates typical process capabilities of the terminal manufacturing process. Fig. 14 shows the test results of the slope portion of the final structure formed by the method for manufacturing the slope structure, wherein each line represents a slope, five different slopes, the structure length is 200 to 400 microns, and the structure height is 3 microns. However, the structure length and the structure height in the present invention are not limited by the method of the present invention, because the structure length completely depends on the pattern length of the reticle with the gradual design, and the structure height depends on the etching material and the etching method.
In addition, all slopes in the figure are completed under the same process, and the structural length difference of the slopes is only derived from the difference of the pattern lengths of the photoetching plates with gradual change design, so that devices with different terminal structures can be manufactured together, and the method has strong capability of wide application.
Example 10
This embodiment shows the capability of the terminal structure to improve the voltage resistance of the device. Fig. 15 shows the computer simulation results of one of the terminal structures of the present invention, in which (a) is the lateral electric field distribution under the interface and (b) is the voltage withstanding curve, and A, B, C has terminal slope lengths of 120, 180, and 300 μm, respectively. This shows that the inventive termination structure can achieve a withstand voltage of 8 kv within a structure length of 120 μm. In contrast, conventional termination structures have been reported to require a structure length of about 250 microns or more to block the same voltage. Therefore, the invention can save the chip area occupied by the terminal by nearly 50 percent and greatly improve the device yield.
While the technical solutions of the present invention have been described above with reference to specific embodiments, it will be understood by those skilled in the art that the various parameters in the above embodiments are merely illustrative and not restrictive, and those skilled in the art can make various modifications according to the technical solutions provided by the present invention.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that the technical solutions of the present invention may be modified or substituted with equivalents without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered by the scope of the claims of the present invention.
Claims (10)
1. A semiconductor device termination structure with a ramp, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, has a structure length of more than 100 micrometers, a structure height of less than 10 micrometers and a smooth surface, and utilizes a photoetching plate with a gradual change design in the forming process;
the groove structure is formed by etching a semiconductor by a dry method and is positioned at the periphery of the slope structure; and
and the filling medium is filled with filling materials in the groove structure.
2. A semiconductor device termination structure with a ramp, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, has a structure length of more than 100 micrometers, a structure height of less than 10 micrometers and a smooth surface, and utilizes a photoetching plate with a gradual change design in the forming process; and
and an implanted structure formed by ion implantation on the semiconductor, the implanted region including a surface of the ramp structure.
3. A semiconductor device termination structure with a ramp, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, has a structure length of more than 100 micrometers, a structure height of less than 10 micrometers and a smooth surface, and utilizes a photoetching plate with a gradual change design in the forming process; and
and the field plate structure is formed by introducing a conductor on the surface of the semiconductor, the conductor is in direct contact with the semiconductor or is in contact with the semiconductor through a passivation layer, and the conductor covering region comprises the surface of the slope structure.
4. A semiconductor device termination structure with a ramp, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, has a structure length of more than 100 micrometers, a structure height of less than 10 micrometers and a smooth surface, and utilizes a photoetching plate with a gradual change design in the forming process;
the groove structure is formed by etching a semiconductor by a dry method and is positioned at the periphery of the slope structure;
the filling medium is filled with filling materials in the groove structure; and
and an implantation structure formed by performing ion implantation on the semiconductor, wherein the implantation region includes a surface of the slope structure or a surface of the trench structure.
5. A semiconductor device termination structure with a ramp, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, has a structure length of more than 100 micrometers, a structure height of less than 10 micrometers and a smooth surface, and utilizes a photoetching plate with a gradual change design in the forming process;
the groove structure is formed by etching a semiconductor by a dry method and is positioned at the periphery of the slope structure;
the filling medium is filled with filling materials in the groove structure; and
and the field plate structure is formed by introducing a conductor on the surface of the semiconductor, wherein the conductor is in direct contact with the semiconductor or is in contact with the semiconductor through a passivation layer, and the conductor covering region comprises the surface of the slope structure or the surface containing the filling medium.
6. A semiconductor device termination structure with a ramp, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, has a structure length of more than 100 micrometers, a structure height of less than 10 micrometers and a smooth surface, and utilizes a photoetching plate with a gradual change design in the forming process;
an implanted structure formed by ion implantation on a semiconductor, the implanted region including a surface of the ramp structure or a surface of a trench structure; and
and the field plate structure is formed by introducing a conductor on the surface of the semiconductor, the conductor is in direct contact with the semiconductor or is in contact with the semiconductor through a passivation layer, and the conductor covering region comprises the surface of the slope structure or the surface containing the filling medium.
7. A semiconductor device termination structure with a ramp, comprising:
the slope structure is formed by a semiconductor after dry etching, is positioned at the periphery of an active region in the semiconductor device, has a structure length of more than 100 micrometers, a structure height of less than 10 micrometers and a smooth surface, and utilizes a photoetching plate with a gradual change design in the forming process;
the groove structure is formed by etching a semiconductor by a dry method and is positioned at the periphery of the slope structure;
the filling medium is filled with filling materials in the groove structure;
the field plate structure is formed by introducing a conductor on the surface of the semiconductor, the conductor is in direct contact with the semiconductor or is in contact with the semiconductor through a passivation layer, and the conductor covering region comprises the surface of the slope structure or the surface containing the filling medium; and
and an implantation structure formed by performing ion implantation on the semiconductor, wherein the implantation region includes a surface of the slope structure or a surface of the trench structure.
8. The method of fabricating a ramp structure for a semiconductor device termination structure according to any one of claims 1 to 7, comprising:
coating a layer of photoresist on the surface of the semiconductor;
placing a photolithography plate with a gradual change design above the photoresist;
exposing the photoresist through the photoetching plate;
putting the semiconductor and the photoresist covered on the semiconductor into a developing solution;
heating the developed semiconductor and the residual photoresist on the developed semiconductor together until the photoresist locally flows and forms a photoresist slope, wherein the structural length of the photoresist slope is more than 100 micrometers;
putting the semiconductor and the photoresist slope on the semiconductor into a dry etching device; and
and removing the photoresist slope and part of the semiconductor by dry etching to finally form a semiconductor slope structure.
9. The method of fabricating an implanted structure of a termination structure of a semiconductor device according to any of claims 2, 4, 6, 7, comprising:
in the forming process of the active area of the semiconductor device, an ion implantation step is used; and
the implantation structure is formed using, or in part using, an ion implantation step used in the formation of the active region of the semiconductor device.
10. The method of fabricating a field plate structure of a termination structure of a semiconductor device according to any of claims 3, 5, 6, 7, comprising:
in the forming process of the active area of the semiconductor device, a conductor deposition or growth step is used; and
the field plate structure is formed using, or in part using, conductor deposition or growth steps used during the formation of the active region of the semiconductor device.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103353209A (en) * | 2013-06-20 | 2013-10-16 | 京东方科技集团股份有限公司 | Vacuum drying device and photolithographic process |
| CN103579073A (en) * | 2012-07-20 | 2014-02-12 | 上海华虹Nec电子有限公司 | Deep trench filling method |
| CN104576345A (en) * | 2013-10-29 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Preparation method of slope field plate structure in power device |
| CN104681681A (en) * | 2013-12-03 | 2015-06-03 | 上海蓝光科技有限公司 | Substrate structure for growth of nitrides of III-V families and preparation method thereof |
| CN107275382A (en) * | 2017-06-20 | 2017-10-20 | 中国科学院微电子研究所 | Device based on mesa multi-region composite JTE terminal structure and manufacturing method thereof |
| CN108346688A (en) * | 2018-01-25 | 2018-07-31 | 中国科学院微电子研究所 | SiC trench junction barrier Schottky diode with CS L transport layer and manufacturing method thereof |
| CN109814329A (en) * | 2018-12-14 | 2019-05-28 | 浙江大学 | A kind of gradual change lithography layout and its semiconductor surface manufacturing method |
| CN112201686A (en) * | 2020-09-08 | 2021-01-08 | 浙江大学 | Super junction device and terminal |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4532005A (en) * | 1984-05-21 | 1985-07-30 | At&T Bell Laboratories | Device lithography using multi-level resist systems |
| US7470556B2 (en) * | 2005-06-28 | 2008-12-30 | Aptina Imaging Corporation | Process for creating tilted microlens |
| CN106504981A (en) * | 2016-10-14 | 2017-03-15 | 电子科技大学 | A kind of method for preparing the controllable gentle slope micro structure of angle |
| CN107706108A (en) * | 2017-10-11 | 2018-02-16 | 中国科学院微电子研究所 | Method for manufacturing junction terminal of silicon carbide device |
| DE102017125244B3 (en) * | 2017-10-27 | 2019-02-28 | Infineon Technologies Ag | SEMICONDUCTOR WITH JUNCTION CLOSING ZONE and method of making the same |
-
2021
- 2021-05-12 CN CN202110515569.1A patent/CN113299735B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579073A (en) * | 2012-07-20 | 2014-02-12 | 上海华虹Nec电子有限公司 | Deep trench filling method |
| CN103353209A (en) * | 2013-06-20 | 2013-10-16 | 京东方科技集团股份有限公司 | Vacuum drying device and photolithographic process |
| CN104576345A (en) * | 2013-10-29 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Preparation method of slope field plate structure in power device |
| CN104681681A (en) * | 2013-12-03 | 2015-06-03 | 上海蓝光科技有限公司 | Substrate structure for growth of nitrides of III-V families and preparation method thereof |
| CN107275382A (en) * | 2017-06-20 | 2017-10-20 | 中国科学院微电子研究所 | Device based on mesa multi-region composite JTE terminal structure and manufacturing method thereof |
| CN108346688A (en) * | 2018-01-25 | 2018-07-31 | 中国科学院微电子研究所 | SiC trench junction barrier Schottky diode with CS L transport layer and manufacturing method thereof |
| CN109814329A (en) * | 2018-12-14 | 2019-05-28 | 浙江大学 | A kind of gradual change lithography layout and its semiconductor surface manufacturing method |
| CN112201686A (en) * | 2020-09-08 | 2021-01-08 | 浙江大学 | Super junction device and terminal |
Non-Patent Citations (1)
| Title |
|---|
| Single-Mask Implantation-Free Technique Based on Aperture Density Modulation for Termination in High-Voltage SiC Thyristors;Hu Long;《IEEE》;20210215;全文 * |
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