CN107275382A - Device based on mesa multi-region composite JTE terminal structure and manufacturing method thereof - Google Patents
Device based on mesa multi-region composite JTE terminal structure and manufacturing method thereof Download PDFInfo
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- CN107275382A CN107275382A CN201710470828.7A CN201710470828A CN107275382A CN 107275382 A CN107275382 A CN 107275382A CN 201710470828 A CN201710470828 A CN 201710470828A CN 107275382 A CN107275382 A CN 107275382A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000002131 composite material Substances 0.000 title abstract 3
- 239000000463 material Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 5
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 77
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 22
- 239000011248 coating agent Substances 0.000 claims description 16
- 238000000576 coating method Methods 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 7
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 230000035945 sensitivity Effects 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract 3
- 230000005684 electric field Effects 0.000 description 19
- 229910052681 coesite Inorganic materials 0.000 description 13
- 229910052906 cristobalite Inorganic materials 0.000 description 13
- 229910052682 stishovite Inorganic materials 0.000 description 13
- 229910052905 tridymite Inorganic materials 0.000 description 13
- 239000000758 substrate Substances 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910003978 SiClx Inorganic materials 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910001439 antimony ion Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a device manufacturing method based on a mesa multi-region composite JTE terminal structure, which comprises the following steps: manufacturing an active area on the surface of the wafer, depositing an oxide layer and patterning to form a mesa area opening; etching the oxide layer and the wafer material to form a terminal table board; depositing an oxide layer on the surface of the terminal table top and patterning to form a wafer sheet material groove opening; etching the oxide layer and the wafer sheet material to form a wafer sheet material groove; depositing an oxide layer, and opening a JTE region to form a JTE terminal; depositing an oxide layer, and opening a hole on the stop ring to form the stop ring; depositing an oxide layer on the front side of the device to form field oxygen protection, and forming a cathode on the back side of the device; and patterning the oxide on the front surface of the device to form an anode on the front surface of the device. The invention also provides a device based on the mesa multi-region composite JTE terminal structure. The invention can reduce the sensitivity of JTE ion implantation dosage and improve the pressure resistance of the device.
Description
Technical field
JTE terminal structures are combined the present invention relates to technical field of semiconductor device, more particularly to a kind of table top multi-region that is based on
Device and preparation method thereof.
Background technology
Modern science and technology is to the volume of semiconductor power device, and reliability is pressure-resistant, and higher want constantly is proposed in terms of power consumption
Ask.With the diminution of transistor feature size, due to the limitation of the physics laws such as short-channel effect and cost of manufacture, main flow silicon substrate
Material is just developing into 10 nanometer technology nodes with CMOS technology and is difficult to continue to lift up.
Carborundum has the energy gap bigger than silicon, has higher mix compared to the Si power device of equal stress levels
Miscellaneous concentration and smaller epitaxy layer thickness, therefore forward conduction resistance can greatly reduce, power attenuation is greatly reduced；Together
When, carborundum has higher thermal conductivity and heat-resisting ability, is adapted to the high-power utilization of high current, can reduce heat dissipation equipment
It is required that, equipment volume is reduced, reliability is improved, reduces cost.So carborundum is considered as IC semiconductor of new generation
Material, has broad application prospects.
It is the terminal technology commonly used in power device that knot terminal, which expands (JTE),.The high field region of general power device leads to
Chang Zhu ties edge, and knot terminal prolongation structure is by introducing electric charge in main knot edge so that the electric field of main knot edge
Reduction, Electric Field Distribution is gentler, and depletion region is expanded to terminal, so as to reach the purpose for improving the pressure-resistant performance of device.Existing
In technology, JTE is very sensitive to the dosage for injecting ion, if the ion dose of injection is too small, device can puncture at main knot, such as
Fruit implantation dosage is excessive, then device can puncture in terminal end.But, influenceed by existing process condition, it is difficult to obtain most
Excellent JTE ion implantation dosages, so that the performance of device can be influenceed.
Therefore, a kind of silicon carbide power device and preparation method thereof is needed badly, reduction device is wanted to JTE ion implantation dosages
Ask, improve the pressure-resistant performance of power device.
The content of the invention
Device that JTE terminal structures are combined based on table top multi-region that the present invention is provided and preparation method thereof, can be for existing
There is the deficiency of technology, sensitivity of the reduction device to JET ion implantation dosages makes the Electric Field Distribution of high field area more uniform,
Effectively improve the lateral breakdown voltage of device.
In a first aspect, the present invention provides a kind of device manufacture method that JTE terminal structures are combined based on table top multi-region, wherein
Including：
Step 1: making active area in wafer surface, deposit the first oxide skin(coating) and be patterned, form table section
Perforate；
Step 2: etching first oxide skin(coating) and wafer sheet material, form terminal table top；
Step 3: the terminal table top the oxide skin(coating) of surface deposition second and be patterned, formed wafer sheet material
Expect groove perforate；
Step 4: etching second oxide skin(coating) and wafer sheet material, form wafer material pocket；
Step 5: deposit trioxide layer, carries out JTE area's perforates, ion implanting formation JTE terminals；
Step 6: deposit tetroxide layer, carries out cut-off ring perforate, ion implanting formation cut-off ring；
Step 7: forming the protection of field oxygen in device front deposit pentoxide layer, formed at the device back side
Negative electrode；
Step 8: the pentoxide positive to the device is patterned, sun is formed in device front
Pole.
Alternatively, above-mentioned wafer sheet material is carborundum.
Alternatively, above-mentioned steps one also include cleaning the wafer.
Alternatively, above-mentioned device is carborundum PiN power devices, silicon carbide MOSFET power device, carborundum IGBT work(
Rate device or carborundum JBS power devices.
Alternatively, above-mentioned first oxide skin(coating), the second oxide skin(coating), trioxide layer, tetroxide layer and/or the
Pentoxide layer is silica.
Alternatively, the number of recesses in above-mentioned steps four is one or more, is shaped as rectangle, trapezoidal or U-shaped.
Alternatively, the groove in above-mentioned steps four is once formed by dry etching or wet etching, and etching depth is identical.
Alternatively, the JTE terminals in above-mentioned steps five are below whole district JTE, including inclined-plane lower section, the groove and side
JTE between wall, adjacent grooves, the groove part or whole are contained in the JTE terminals.
Alternatively, all covering oxide layer is as media protection for above-mentioned JTE terminal structures, and the oxide layer is last from active area
End extends to the cut-off ring.
On the other hand, the present invention is also provided a kind of is combined JTE terminal knots according to what the above method made based on table top multi-region
The device of structure, including：
Positioned at the active area of wafer surface；
Table top and groove positioned at the active area end；
Table top multi-region is combined JTE, including the JTE under the table top and below the groove, side wall and phase
JTE between adjacent groove；
Fill the groove and cover the oxide layer above the terminal structure, the coverage of the oxide layer is from described
Active area end to the terminal structure outer rim cut-off ring；
Negative electrode and anode metal.
Device provided in an embodiment of the present invention that JTE terminal structures are combined based on table top multi-region and preparation method thereof, can
By etching silicon carbide formation silicon carbide table board and carborundum groove, then with ion implanting formation JTE areas so that in the middle of JTE areas
Partial pressure is played a part of in part, multiple peak electric field points is formed, so as to reduce the sensitivity of JTE ion implantation dosages, further
Improve the voltage endurance capability of device.
Brief description of the drawings
Fig. 1 is combined the structural representation of JTE power device terminal structure for the table top multi-region of one embodiment of the invention；
Fig. 2 is depletion region structural representation of the terminal structure of the power device of one embodiment of the invention in reverse blocking
Figure；
Fig. 3 is the structural representation of power device list area JTE structures in the prior art；
Fig. 4 is single area JTE configuration terminals of power device in the prior art and the power device of one embodiment of the invention
The breakdown voltage simulation result contrast schematic diagram of JTE configuration terminals；
Fig. 5 is the surface one-dimensional electric field distributed simulation of the terminal structure horizontal direction of the power device of one embodiment of the invention
Result schematic diagram；
Fig. 6 is the process chart of the terminal structure making of the power device of one embodiment of the invention；
Fig. 7 A to 7H are the device fabrication steps knots that JTE terminal structures are combined based on table top multi-region of one embodiment of the invention
Structure schematic diagram.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only
Only it is a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, ordinary skill
The every other embodiment that personnel are obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
Fig. 1 shows that the table top multi-region of one embodiment of the invention is combined the terminal structure schematic diagram of JTE power device.It is excellent
Choosing, terminal part of the invention includes but is not limited to carborundum JBS devices, silicon carbide MOSFET device, carborundum IGBT devices
Part or carborundum PiN devices.Wafer is provided first, specifically, the material of wafer includes but is not limited to Si, SiC, Al2O3、
The materials such as GaAS, AlN, ZnO, it is preferred that one embodiment of the present of invention uses carborundum (SiC) wafer.As illustrated, 1
It is N-Drift region, specifically, addition such as phosphorus, arsenic or Ti Deng V races impurity formation N are lightly doped in a semiconductor material-Drift region；
Optionally, 1 can be intrinsic semiconductor i areas, i.e., do not mix impurity and the intrinsic semiconductor region without lattice defect.7 be N+Lining
Bottom, specifically, heavy doping in a semiconductor material add such as phosphorus, arsenic or Ti Deng V races impurity formation N+Substrate.2 be that ohm connects
Touch P++Area, specifically, Ohmic contact P++Area is contacted with metal, and is pure resistance in contact position, can be by being served as a contrast in semiconductor
A large amount of group-III elements formation high-doped zone such as boron, indium is mixed in the superficial layer at bottom.3 be N-P above drift region+Area,
Specifically, the P+Area can pass through the group-III element formation heavy doping such as boron, indium of the middle incorporation in Semiconductor substrate.
4 be below carborundum groove and the JTE of side wall, specifically, in the embodiment of invention, and multi-region is combined JTE can be with
By being formed to the group-III element such as boron, indium is lightly doped around main knot；Particularly, the width of each JTE subregion can not
Together, for example successively decreased with certain factor ratio.When device is in reverse-biased, JTE regions are depleted simultaneously, are equal in drift
Negative electrical charge is introduced in the depletion region in area, so that depletion region be extended, pressure voltage and end use efficiency is improved.5 be oxide layer, typical case
, oxide layer can include but is not limited to SiO2Deng oxide.It is preferred that, oxidated layer thickness is 3 μm, and length is since main knot end
Extend to cut-off ring.6 be the N positioned at device outermost+End ring, specifically, the N in the embodiment of the present invention+Ending ring can
With by device outermost inject higher dosage n-type doping formed, the V group element such as phosphorus, arsenic or antimony, it is main knot and
P can be formed between cut-off ring+N-N+Structure, when horizontal direction depletion layer extends to cut-off ring position, because depletion layer doping is dense
Degree is high, and the depletion width in cut-off ring can be greatly shortened, and electric field is terminated in cut-off ring.
8 be to be located at N+End the floating electrode of the top of ring 6.9 be cathodic metal, including but not limited to Ti or Ni etc., specifically
, cathodic metal can be realized and heavy doping N by techniques such as PVD, CVD, sputtering, ALD+The contact of substrate.10 be anode gold
Category, including but not limited to Ti or Ni etc., specifically, anode metal can be realized and Europe by techniques such as PVD, CVD, sputtering, ALD
Nurse contacts P++The contact in area.
11 be carborundum groove, specifically, carborundum groove can be multiple, and multiple carborundum grooves can have
Identical or different width or depth, the spacing of carborundum groove can arbitrarily change, the carborundum groove part of outermost or
Multi-region is all contained in be combined in JTE.It is preferred that, the quantity of carborundum groove is 3.It is preferred that, the shape of carborundum groove
For rectangle, trapezoidal or U-shaped.It is preferred that, carborundum groove is once formed by wet etching, and corrosion depth is unified.Particularly, it is adjacent
JTE between carborundum groove ensure that the JTE with side wall below carborundum groove is not punctured in advance, and make adjacent
The spacing and carborundum bottom portion of groove width of carborundum groove have larger process window.
12 be silicon carbide table board, specifically, silicon carbide table board 12 can include Ohmic contact P++Area, P+Area and JTE shapes
Into table top, silicon carbide table board is highly 2 μm, and table top angle is at 45 ° or so, in the case of identical area, expands eventually
The length at end, and play a part of electric field and be concentrically formed peak electric field.13 be the JTE between adjacent carbons SiClx groove.
Fig. 2 shows that exhaust plot structure of the terminal structure of the power device of one embodiment of the invention in reverse blocking shows
It is intended to.Conventional JTE configuration terminals can reduce the High-Field concentration phenomenon of main knot end to a certain extent, but the electricity in the middle part of terminal
Field intensity is very low, and terminal, which does not have, to be fully utilized.In an embodiment of the present invention, plus earth is worked as, when negative electrode connects high pressure
The table top multi-region of termination environment is combined JTE structures and bears pressure-resistant.As illustrated, 1 is N-Drift region, 2 be Ohmic contact P++Area, 3 are
N-P above drift region+Area, 4 be below carborundum groove and the JTE of side wall.As illustrated, 14 be the boundary electric potentials of depletion region
Line, when device is in reverse-biased, JTE regions are depleted simultaneously, are equal to and are introduced negative electricity in the depletion region of drift region
Lotus, so that depletion region be extended, border 14 is located at JTE outer rims, improves the pressure voltage and end use efficiency of device.
Fig. 3 shows the structural representation of power device list area JTE structures in the prior art.As illustrated, 1 is N-Drift
Area, 7 be N+Substrate, 2 be Ohmic contact P++Area, 3 be N-P above drift region+Area, 4 be single area JTE, and 5 be oxide layer, typical case
, oxide layer can include but is not limited to SiO2Deng oxide.6 be the N positioned at device outermost+End ring, 8 be to be located at N+Cut
The only floating electrode of the top of ring 6.9 be cathodic metal, and 10 be anode metal.
Fig. 4 shows the single area JTE configuration terminals and the power device of one embodiment of the invention of power device in the prior art
The breakdown voltage simulation result contrast schematic diagram of the JTE configuration terminals of part.Traditional JTE structures of the prior art are to JTE areas
Doping concentration is more sensitive, can realize that the high doping concentration scope punctured is narrower, if JTE areas excessive concentration, JTE outward flanges
Place can produce larger electric field spike, cause JTE afterbodys to puncture in advance；If JTE areas concentration is too low, JTE areas can be in main knot
Edge produces electric field spike, causes puncturing in advance for main knot.As illustrated, transverse axis is backward voltage, the longitudinal axis is reverse current,
The breakdown voltage contrast of the JTE configuration terminals of traditional JTE structures and one embodiment of the invention of the prior art, compared to tradition
JTE structures 1000V or so breakdown voltage, the breakdown voltage of the JTE configuration terminals of one embodiment of the invention is obviously improved, and is about existed
In the range of 1400-1600V.
Fig. 5 shows the surface one-dimensional electric field distribution of the terminal structure horizontal direction of the power device of one embodiment of the invention
Simulation result schematic diagram.As illustrated, transverse axis is the length in end level direction, the longitudinal axis is electric-field intensity, and the present invention one is implemented
Example is combined JTE terminals in the table top multi-region by etching silicon carbide formation, and middle part electric field is elevated, and multiple electric field spikes occurs,
Termination environment is fully utilized, and the pressure-resistant performance of device is also further lifted.
Fig. 6 is the process chart of the terminal structure making of the power device of one embodiment of the invention；As illustrated, S61
Cleaning sic wafer is represented, active area is made, the first oxide skin(coating) is deposited and is patterned, form table section perforate；
S62 represents the first oxide skin(coating) of etching and carborundum, forms terminal table top, particularly, the first oxide skin(coating) includes but do not limited
In SiO2；S63 represents the second oxide skin(coating) of deposit and is patterned, and forms carborundum groove perforate, particularly, the second oxidation
Nitride layer includes but is not limited to SiO2；S64 represents the second oxide skin(coating) of etching and carborundum, forms carborundum groove；S65 represents to form sediment
Product trioxide floor simultaneously carries out the perforate of JTE areas, unified to carry out ion implanting formation JTE terminals, particularly, trioxide layer
Including but not limited to SiO2；S66 represents deposition tetroxide layer and carries out cut-off ring perforate, and ion implanting formation ends ring,
Particularly, tetroxide layer includes but is not limited to SiO2；S67 represents that deposit pentoxide layer in front forms the protection of field oxygen,
The back side forms negative electrode, particularly, particularly, and pentoxide layer includes but is not limited to SiO2；S68 is represented to positive 5th oxidation
Thing is patterned, and forms anode.
Fig. 7 A to 7H are the device fabrication steps knots that JTE terminal structures are combined based on table top multi-region of one embodiment of the invention
Structure schematic diagram.
As shown in Figure 7 A, 1 is N-Drift region, 2 be Ohmic contact P++Area, 3 be N-P above drift region+Area, 5 be oxidation
Layer, 7 be N+Substrate.Specifically, by deposited oxide layer on silicon carbide whisker disk, and wet etching is carried out, form table section
Perforate.It is preferred that, silicon carbide whisker disk is by cleaning.Particularly, oxide layer includes but is not limited to SiO2。
As shown in Figure 7 B, 1 is N-Drift region, 2 be Ohmic contact P++Area, 3 be N-P above drift region+Area, 7 be N+Lining
Bottom, 12 be silicon carbide table board.Specifically, etching oxidation layer and carborundum, form terminal table top.It is preferred that, lithographic method includes
But it is not limited to dry etching.It is preferred that, oxide layer includes but is not limited to SiO2。
As seen in figure 7 c, 1 is N-Drift region, 2 be Ohmic contact P++Area, 3 be N-P above drift region+Area, 5 be oxidation
Layer, 7 be N+Substrate, 12 be silicon carbide table board.Specifically, on silicon carbide whisker disk deposited oxide layer, and etching oxidation layer shape
Into carborundum groove perforate.It is preferred that, lithographic method includes but is not limited to wet etching.It is preferred that, oxide layer includes but not limited
In SiO2。
As illustrated in fig. 7d, 1 is N-Drift region, 2 be Ohmic contact P++Area, 3 be N-P above drift region+Area, 7 be N+Lining
Bottom, 11 be carborundum groove, and 12 be silicon carbide table board.Specifically, etching oxidation nitride layer and silicon nitride, form carborundum groove.
It is preferred that, lithographic method includes but is not limited to dry etching.It is preferred that, oxide layer includes but is not limited to SiO2。
As seen in figure 7e, 1 is N-Drift region, 2 be Ohmic contact P++Area, 3 be N-P above drift region+Area, 4 be carborundum
With the JTE of side wall below groove, 5 be oxide layer, and 7 be N+Substrate, 11 be carborundum groove, and 12 be silicon carbide table board, and 13 be phase
JTE between adjacent carborundum groove.Specifically, on silicon carbide whisker disk deposited oxide layer, and graphically, form p-type ion note
Enter mask and multi-region is combined JTE perforates, by the p-type ion implanting of the group-III element such as boron, indium, form multi-region and be combined
JTE.It is preferred that, oxide layer includes but is not limited to SiO2。
As shown in Figure 7 F, 1 is N-Drift region, 2 be Ohmic contact P++Area, 3 be N-P above drift region+Area, 4 be carborundum
With the JTE of side wall below groove, 5 be oxide layer, and 6 be the N positioned at device outermost+End ring, 7 be N+Substrate, 11 be carborundum
Groove, 12 be silicon carbide table board, and 13 be the JTE between adjacent carbons SiClx groove.Specifically, removing oxide layer is removed, again in carborundum
New oxide layer is deposited on wafer, it is preferred that oxide layer includes but is not limited to SiO2.It is further graphical to form N+Area's perforate,
For example, by the V group element N-type such as phosphorus, arsenic or antimony ion implanting formation N+End ring.
As shown in Figure 7 G, 1 is N-Drift region, 2 be Ohmic contact P++Area, 3 be N-P above drift region+Area, 4 be carborundum
With the JTE of side wall below groove, 5 be oxide layer, and 6 be the N positioned at device outermost+End ring, 7 be N+Substrate, 9 be negative electrode gold
Category, 11 be carborundum groove, and 12 be silicon carbide table board, and 13 be the JTE between adjacent carbons SiClx groove.Specifically, removing oxide layer is removed,
Form back surface ohmic contacts as the protection of field oxygen medium, back side evaporated metal and annealing in device front again deposited oxide and close
Gold, row metal of going forward side by side thickeies, and forms negative electrode.
As shown in fig. 7h, 1 is N-Drift region, 2 be Ohmic contact P++Area, 3 be N-P above drift region+Area, 4 be carborundum
With the JTE of side wall below groove, 5 be oxide layer, and 6 be the N positioned at device outermost+End ring, 7 be N+Substrate, 8 be to be located at N+
End the floating electrode of the top of ring 6,9 be cathodic metal, and 10 be anode metal, and 11 be carborundum groove, and 12 be silicon carbide table board,
13 be the JTE between adjacent carbons SiClx groove.Device front carry out oxide layer perforate, evaporated metal and anneal form front ohmic
Contact alloy, row metal of going forward side by side thickeies, and forms anode.
Particularly, the embodiment that the present invention is provided forms silicon carbide table board by etching silicon carbide, then in the plane of table top
Partial etching carborundum formation groove, finally carries out ion implanting, makes some local radius of curvature of the compound JTE of multi-region smaller,
Electric field concentration is easily caused, multiple peak electric field points can be formed by being combined JTE in whole multi-region.Under identical terminal area,
By the multiple peak electric field points of original single peak electric field point till now, pressure voltage substantially increases, and multi-region, which is combined JTE, to fill
That divides is utilized, and Electric Field Distribution is more they tended to gently.
Particularly, in the embodiment that provides of the present invention, breakdown point be not only distributed across near main knot or JTE ends,
But possibly be present at any one position of terminal.The change of silicon carbide power device breakdown point position in the present invention is also said
Understand that multi-region is combined JTE terminals and is influenceed reduction by injection ion dose, so as to further reduce the quick of terminal-pair ion dose
Sense degree.In addition, the present invention has little to no effect while device reverse characteristic is improved to the forward characteristic of device.
The embodiment that the present invention is provided, can effectively improve device electric breakdown strength, reduce the sensitivity to ion dose
And the internal field of device surface, while reducing the impact ionization rate and surface leakage of device surface, improve device surface
Reliability.In addition, the present invention uses conventional silicon carbide silicon technology, it can be realized by existing silicon carbide diode manufacture craft, it is compatible
Property it is good, compared with traditional single area JTE structures, the present invention can effectively shorten terminal length, save chip area.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, the change or replacement that can be readily occurred in, all should
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be defined by scope of the claims.
Claims (10)
1. a kind of device manufacture method that JTE terminal structures are combined based on table top multi-region, it is characterised in that including：
Step 1: making active area in wafer surface, deposit the first oxide skin(coating) and be patterned, form table section and open
Hole；
Step 2: etching first oxide skin(coating) and wafer sheet material, form terminal table top；
Step 3: the terminal table top the oxide skin(coating) of surface deposition second and be patterned, formed wafer sheet material it is recessed
Groove perforate；
Step 4: etching second oxide skin(coating) and wafer sheet material, form wafer material pocket；
Step 5: deposit trioxide layer, carries out JTE area's perforates, ion implanting formation JTE terminals；
Step 6: deposit tetroxide layer, carries out cut-off ring perforate, ion implanting formation cut-off ring；
Step 7: forming the protection of field oxygen in device front deposit pentoxide layer, negative electrode is formed at the device back side；
Step 8: the pentoxide positive to the device is patterned, anode is formed in device front.
2. device manufacture method according to claim 1, it is characterised in that the wafer sheet material is carborundum.
3. device manufacture method according to claim 1, it is characterised in that the step one also includes to the wafer
Cleaned.
4. device manufacture method according to claim 2, it is characterised in that the device be carborundum PiN power devices,
Silicon carbide MOSFET power device, carborundum IGBT power devices or carborundum JBS power devices.
5. device manufacture method according to claim 2, it is characterised in that first oxide skin(coating), the second oxide
Layer, trioxide layer, tetroxide layer and/or pentoxide layer are silica.
6. device manufacture method according to claim 2, it is characterised in that the number of recesses in the step 4 is one
Or it is multiple, it is shaped as rectangle, trapezoidal or U-shaped.
7. device manufacture method according to claim 2, it is characterised in that the groove in the step 4 is carved by dry method
Erosion or wet etching are once formed, and etching depth is identical.
8. device manufacture method according to claim 2, it is characterised in that the JTE terminals in the step 5 are the whole district
JTE, including inclined-plane lower section, groove lower section and the JTE between side wall, adjacent grooves, the groove part or whole are included
In the JTE terminals.
9. device manufacture method according to claim 1, it is characterised in that the JTE terminal structures all covering oxidations
Layer is as media protection, and the oxide layer extends to the cut-off ring from active area end.
10. the device that JTE terminal structures are combined based on table top multi-region that a kind of method according to claim 1 makes, its feature
It is, including：
Positioned at the active area of wafer surface；
Table top and groove positioned at the active area end；
Table top multi-region is combined JTE, including the JTE under the table top and below the groove, side wall and adjacent recessed
JTE between groove；
Fill the groove and cover the oxide layer above the terminal structure, the coverage of the oxide layer is from described active
Area end to the terminal structure outer rim cut-off ring；
Negative electrode and anode metal.
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| CN112349770A (en) * | 2020-09-30 | 2021-02-09 | 湖南大学 | Silicon carbide power device composite terminal structure and preparation method thereof |
| CN113299735A (en) * | 2021-05-12 | 2021-08-24 | 浙江大学 | Semiconductor device terminal structure with slope and manufacturing method thereof |
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| CN105977310A (en) * | 2016-07-27 | 2016-09-28 | 电子科技大学 | Silicon carbide power device terminal structure and manufacturing method thereof |
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| CN101978502A (en) * | 2008-03-17 | 2011-02-16 | 三菱电机株式会社 | Semiconductor device |
| CN103000698A (en) * | 2012-11-23 | 2013-03-27 | 中国科学院微电子研究所 | SiC junction barrier Schottky diode and manufacturing method thereof |
| US9478673B2 (en) * | 2012-12-10 | 2016-10-25 | Rohm Co., Ltd. | Semiconductor device with trench structure and manufacturing method thereof |
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| CN112349770A (en) * | 2020-09-30 | 2021-02-09 | 湖南大学 | Silicon carbide power device composite terminal structure and preparation method thereof |
| CN113299735A (en) * | 2021-05-12 | 2021-08-24 | 浙江大学 | Semiconductor device terminal structure with slope and manufacturing method thereof |
| CN113299735B (en) * | 2021-05-12 | 2022-08-05 | 浙江大学 | Semiconductor device terminal structure with slope and manufacturing method thereof |
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