CN108198866A - A kind of groove-shaped low barrier Schottky diode and preparation method thereof - Google Patents
A kind of groove-shaped low barrier Schottky diode and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000004891 communication Methods 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 238000002347 injection Methods 0.000 claims description 26
- 239000007924 injection Substances 0.000 claims description 26
- 150000002500 ions Chemical class 0.000 claims description 19
- 238000000137 annealing Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052681 coesite Inorganic materials 0.000 claims description 13
- 229910052906 cristobalite Inorganic materials 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 229910052682 stishovite Inorganic materials 0.000 claims description 13
- 229910052905 tridymite Inorganic materials 0.000 claims description 13
- 238000002161 passivation Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 229910002804 graphite Inorganic materials 0.000 claims description 5
- 239000010439 graphite Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
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- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000005036 potential barrier Methods 0.000 abstract description 20
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- 238000010586 diagram Methods 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052779 Neodymium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
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- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- -1 and in bottom Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000005404 monopole Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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Abstract
The invention discloses a kind of groove-shaped low barrier Schottky diodes and preparation method thereof, the active area of the Schottky diode is groove structure, the top of table top is Schottky contacts, the side wall and channel bottom of table top are the highly doped p-type area of electrical communication, and channel bottom forms p-type Ohmic contact；The depth of groove is dt, width Wt；Mesa width is Wm, and the junction depth of the p-type area is dp；Wt is more than 1 μm, and Wm is more than 0.5 μm, and dt is more than 0.5 μm, and dp is more than 0.5 μm.The present invention forms low barrier schottky using the method that image force potential barrier reduces on table top and contacts.Mesa side walls and channel bottom carry out p+ doping and carry out Ohmic contact, form pn diodes in parallel, enhance the surge capacity of device, while shield Schottky conducting channel, increase the voltage endurance capability and heat-resisting ability of device.The Schottky diode of the present invention can reduce the potential barrier of device, while keep superior high pressure resistant, hot properties and surge capacity.
Description
Technical field
The present invention relates to semiconductor applications, and in particular to a kind of groove-shaped low barrier Schottky diode and its preparation side
Method.
Background technology
Schottky diode, almost without reverse recovery current, has better due to being monopole type device than pn diode
Reverse recovery characteristic.The Schottky diode of wide bandgap semiconductor silicon carbide (SiC) can accomplish pressure-resistant more than 3300V, in height
There is better advantage in pressure, high-frequency switch circuit.But also due to the broad-band gap characteristic of carbofrax material, SiC Schottky
The potential barrier of diode is generally all higher, as industrial quarters through common Ti, MO potential barrier between 1.2-1.3eV, and the gesture of Ni, Pt
It builds and is then more than 1.6eV.Potential barrier height can make device bear higher pressure resistance and heat safe application power, but high potential barrier
So that the forward voltage drop raising of diode, conduction loss increase.Loss particularly on Schottky barrier can become main portion
Point.Such as the device of conventional 10A, forward voltage drop 1.5V, and the pressure drop in potential barrier reaches 0.9V, becomes the main portion of loss
Point.Therefore, conduction loss can further be reduced by studying low potential barrier SiC Schottky diode.But reverse-biased electric leakage after potential barrier reduction
Stream can also increase, and how remain high pressure resistant while potential barrier is reduced, hot properties is the key that research.
Invention content
For problems of the prior art, the purpose of the present invention is to provide a kind of groove-shaped low barrier schottkies two
Pole pipe by improving device architecture and technique, under the premise of Schottky contact metal is not changed, reduces the Schottky of device
Contact berrier, the final forward voltage drop and conduction loss for reducing device.It is a kind of groove-shaped another object of the present invention is to provide
The preparation method of low barrier Schottky diode.
To achieve the above object, the present invention uses following technical scheme：
A kind of groove-shaped low barrier Schottky diode, the active area of the Schottky diode are groove structure, table top
Top for Schottky contacts, the side wall and channel bottom of table top are the highly doped p-type area of electrical communication, and channel bottom shape
Into p-type Ohmic contact；The depth of groove is dt, width Wt；Mesa width is Wm, and the junction depth of the p-type area is dp；Wherein,
Wt is more than 1 μm, and Wm is more than 0.5 μm, and dt is more than 0.5 μm, and dp is more than 0.5 μm.
Further, the thickness of the buffer layer of the Schottky diode is 0.5-2 μm, a concentration of 1E18cm-3；Drift layer
Concentration is in 1E14cm-3-5E16cm-3Between, thickness is between 5-200 μm；The concentration of channel layer is in 1E16-1E17cm-3Between,
Thickness is more than 0.5 μm；The concentration of barrier modulation layer is more than the concentration of the channel layer, and thickness is less than 0.2 μm.
A kind of preparation method of groove-shaped low barrier Schottky diode, described method includes following steps：
1) it takes and has grown the epitaxial wafer for having barrier modulation layer or used ion on the epitaxial wafer of no barrier modulation layer
The mode of injection forms barrier modulation layer, to n-type material injection N, P ion；Then the photo-etching mark on epitaxial wafer is done uses
PECVD or LPCVD methods deposit SiO2Layer, and etched after carrying out photoetching, form the mask pattern of SiC etchings；With ICP or RIE
Method for etching plasma, with SiO2Layer is mask, and etching SiC forms groove；
2) knot termination environment is protected with photoresist, with reference to SiO remaining in step 1)2Layer carries out ion implanting, note for mask
It is p-type Doped ions to enter, and is repeatedly infused in bottom portion of groove, side wall one p-type doped region of formation, removes and cover after the completion of injection
Film；Again with photolithography method formed knot termination environment inject mask, carry out knot termination environment ion implanting, similary implanted with p-type adulterate from
Son；
3) it anneals later into line activating as protection in device surface deposit a thin layer graphite linings；
4) graphite linings are removed, surface of SiC is cleaned；Sacrificial oxidation process is carried out later, with the side of thermal oxide
Method grows layer of oxide layer, then erodes the oxide layer with HF or BOE；
5) thermal oxide growth SiO is carried out again2Passivation layer grows field dielectric layer with PECVD or CVD method, with photoetching, etching
Or the method for BOE corrosion removes the medium in active area, retains the medium of knot termination environment, forms protection of the medium to termination environment；
6) metal ohmic contact, back side deposit gold are done in bottom portion of groove p areas with the method for photoetching, evaporated metal and stripping
Belong to, carry out short annealing and form Ohmic contact；
7) in surface deposition metal, Schottky contacts are formed in the mesa top of active area, recess sidewall respectively；Then into
Row annealing, to improve the Schottky contacts of n-type surface；
8) it deposits and forms electrode metal, deposit dielectric passivation；And be patterned and selective etching, expose the gold of electrode
Belong to；Carry out baking-curing；Finally, overleaf deposition of electrode metal.
Further, repeatedly injection is divided into part in step 2), and first part is vertical injection, injects junction depth in bottom portion of groove
More than 0.5 μm, concentration is more than 1E17cm-3P+ areas；Second part is vertical plus tilts injection, while on the surface of bottom portion of groove
Concentration, which is formed, with recess sidewall is more than 1E19cm-3P+ areas.
Further, the temperature of the activation annealing in step 3) is more than 1500 DEG C, and the time is more than 3 minutes.
Further, the thickness of oxide layer is 10nm-50nm in step 4).
Further, SiO described in step 5)2The thickness of passivation layer is 10nm-50nm, and the thickness of the field dielectric layer is more than
200nm。
Further, the temperature of short annealing is 950-1050 DEG C in step 6), and the time is 2-5 minutes.
Further, the annealing temperature made annealing treatment in step 7) is 400-800 DEG C.
Further, electrode metal described in step 8) is Al or the Al for mixing Si, Cu, the thickness of electrode metal are more than 3 μ
m。
The present invention has following advantageous effects：
The present invention forms low barrier schottky using the method that image force potential barrier reduces on table top and contacts.Mesa side walls and
Channel bottom carries out p+ doping and carries out Ohmic contact, forms pn diodes in parallel, enhances the surge capacity of device, shield simultaneously
Schottky conducting channel is covered, increases the voltage endurance capability and heat-resisting ability of device.The Schottky diode of the present invention can reduce
The potential barrier of device, while keep superior high pressure resistant, hot properties and surge capacity.
Description of the drawings
Fig. 1 is the cross section structure schematic diagram of Schottky diode of the embodiment of the present invention；
Fig. 2 is the cross section structure schematic diagram after Schottky diode preparation process concave of the embodiment of the present invention is groove etched；
Fig. 3 is the cross section structure schematic diagram after the injection of Schottky diode preparation process of embodiment of the present invention intermediate ion；
Fig. 4 is the cross section structure schematic diagram after activation annealing in Schottky diode preparation process of the embodiment of the present invention；
Fig. 5 is the cross section structure schematic diagram after the media technology of Schottky diode preparation process of embodiment of the present invention midfield；
Fig. 6 is the cross section structure schematic diagram after Ohmic contact in Schottky diode preparation process of the embodiment of the present invention；
Fig. 7 is the cross section structure schematic diagram of schottky junctions after touch in Schottky diode preparation process of the embodiment of the present invention；
Fig. 8 is electrode metal in Schottky diode preparation process of the embodiment of the present invention and the cross section structure after passivation protection
Schematic diagram.
Specific embodiment
In the following, refer to the attached drawing, more fully illustrates the present invention, shown in the drawings of the exemplary implementation of the present invention
Example.However, the present invention can be presented as a variety of different forms, it is not construed as being confined to the exemplary implementation described here
Example.And these embodiments are to provide, so as to make the present invention fully and completely, and it will fully convey the scope of the invention to this
The those of ordinary skill in field.
The present invention is by improving device architecture and technique, under the premise of Schottky contact metal is not changed, reduces device
Schottky contact barrier, the final forward voltage drop and conduction loss for reducing device.
In the SiC substrate of the first conduction type, the first conductive type buffer layer of extension, the thickness of buffer layer is 0.5-2 μ
Between m, a concentration of 1E18cm-3Left and right；Extension the first conduction type drift layer, the concentration of drift layer is in 1E14cm-3-5E16cm-3
Between, thickness is between 5-200 μm, and the concentration of drift layer, thickness are depending on the pressure resistance of design device；Epitaxial growth first is led
Electric type channel layer, the concentration ratio drift layer of channel layer is slightly higher, in order to reduce the conducting resistance of raceway groove, a concentration of 1E16-
1E17cm-3Between, thickness is more than 0.5 μm；The barrier modulation layer of the first conduction type of epitaxial growth, concentration ratio channel layer is more
Height, in order to form the lower Schottky contacts of potential barrier, thickness is less than 0.2 μm.The concentration of barrier modulation layer, thickness are according to design
Depending on potential barrier.Barrier modulation layer can also be formed by the method that ion implanting reactivation is annealed.First conduction type can be n
Type or p-type, principle is consistent, is illustrated below with N-shaped.
Principle is reduced according to image force potential barrier, if forming the doping of high concentration on surface, the dosage of superficial layer is much larger than
Depletion region charge during the zero bias of drift region, then compared with metal and drift region contact the potential barrier to be formed, potential barrier reduces △ φ,
△ φ=q/ ε * sqrt (a*Ns/ (4* π))
A*Ns is the dosage of surface heavily doped layer, and wherein a is thickness, and Ns is concentration.That is, increase the dosage of superficial layer,
Schottky barrier can effectively be reduced.Usually superficial layer dosage is more than 9E11cm-2, potential barrier reduction more than 0.05eV.Such as surface
The doping concentration of 0.1 μ m-thick is 4E17cm-3, then Ns is 4E12cm-2, △ φ are equal to 0.1eV, i.e. potential barrier reduction 0.1eV.Therefore
It can be controlled by the high dose of skin layer, adjust barrier height.
As shown in Figure 1, the groove-shaped low barrier Schottky diode of the present invention is broadly divided into intermediate active area and periphery
Knot termination environment.Active area is groove structure, and mesa top is Schottky contacts 1, side wall and the height that channel bottom is electrical communication
The p-type area of doping, and channel bottom forms p-type metal ohmic contact 2.The p+ types of channel bottom and side wall are adulterated by multiple
Vertical injection and inclination injection are formed.Knot terminal can be the diversified forms such as the combination of field limiting ring, JTE and the two.Active area
The n-layer concentration of mesa top is higher than raceway groove and drift layer, and concentration, thickness are by depending on the potential barrier that designs, being such as equal to △ φ
0.1eV, concentration can be 7E17cm-3, thickness 50nm or a concentration of 1.75E18cm-3, thickness 20nm.The depth of groove
It spends for dt, width Wt, the junction depth in mesa width Wm, p+ areas is dp.When the electric current that current density is Jf flows through raceway groove, ditch
The top in road 6 and pn-junction bottom section can form potential difference △ V, △ V=Jf* ρ * (dt+dp), and wherein ρ is the resistivity of raceway groove,
It is doping concentration that doping concentration relationship with raceway groove, which is ρ=1/q* μ * Nd, Nd,.When △ V are equal to pn-junction with Schottky barrier difference,
The pn diodes of trench bottom will be opened, and a large amount of few son injection carries out the modulation of conductivity, so as to further promote surge electricity
Stream ability.Under normal circumstances, Wm is more than 1 μm, and Wm is more than 0.5 μm, and dt is more than 0.5 μm, and dp is more than 0.5 μm.The groove of the present invention
The low barrier Schottky diode of type further includes barrier modulation layer 3, field dielectric layer 4 and passivation layer 5.
The groove-shaped low barrier Schottky diode preparation method of the present invention is as follows：
The epitaxial wafer for having barrier modulation layer or the epitaxial wafer in no barrier modulation layer have been grown as shown in Fig. 2, taking
On with the mode of ion implanting form barrier modulation layer 3, to n-type material injection N, P ion.Photo-etching mark is done first.PECVD
Or LPCVD methods deposit SiO2Layer 7, and etched after carrying out photoetching, form the mask pattern of SiC etchings.SiO2The thickness of layer 7 is big
In 500nm, determined by the thickness needed for etching SiC groove.With the method for etching plasma of ICP or RIE, with SiO2Layer 7 is
Mask, etching SiC form groove, and remaining enough SiO2Thickness for next step process ion implantation mask.
As shown in figure 3, carrying out photoetching process, knot termination environment is protected with photoresist, with reference to remaining SiO2Layer 7, formation is covered
Film carries out ion implanting, and injection is p-type Doped ions, such as Al, B plasma, is repeatedly infused in bottom portion of groove, side wall is formed
One p-type doped region.Injection is divided into part, and first part is vertical injection, and in bottom, injection junction depth is more than 0.5 μm, and concentration is big
In 1E17cm-3P+ areas.Second part is vertical plus tilts injection, while form concentration on the surface of bottom and side wall and be more than
1E19cm-3P+ areas.Removal mask after the completion of injection.The mask of knot termination environment injection is formed with photolithography method again, carries out knot eventually
Petiolarea ion implanting, similary implanted with p-type Doped ions, such as Al, B plasma.
It anneals as shown in figure 4, being used as to protect into line activating in surface deposition a thin layer graphite linings 8, activates the temperature of annealing
More than 1500 DEG C, the time is more than 3 minutes.
As shown in figure 5, thermal oxide growth SiO is carried out again2Passivation layer, thickness can be 10nm-50nm, can be wet oxygen or
Dry oxide growth method.Control the thickness of thermal oxide growth twice so that the thickness of the highly doped barrier modulation layer in remaining surface,
Concentration meets design requirement.With PECVD or other CVD methods growth field dielectric layer 4, medium can be SiO2Or Si3N4Or
SiO2/Si3N4, SiOxNy etc., thickness is more than 200nm, removes the medium in active area with photoetching, etching, the method for BOE corrosion,
Retain the medium of knot termination environment.Form protection of the medium to termination environment.
As shown in Figure 6.With the method for photoetching, evaporated metal and stripping metal ohmic contact 2 is done in bottom portion of groove p areas.
The back side deposits metal, carries out short annealing and forms Ohmic contact 9.P-type metal ohmic contact can be TiAl etc., and back metal is
Ni, carries out 950-1050 DEG C, and the short annealing of 2-5 minutes forms Ohmic contact.
As shown in Figure 7.In surface deposition metal, schottky junctions are formed in the mesa top of active area, recess sidewall respectively
Touch 1.Carrying out annealing improves the Schottky contacts of n-type surface.Such as, metal material can be Ti, Mo, annealing temperature 400-
800℃.Doping after annealing due to recess sidewall is very high, can form Ohmic contact.
As shown in Figure 8.It deposits and forms electrode metal 10, such as Al or the Al for mixing Si or Cu, more than 3 μ m-thicks or Ag
Or Cu, thickness are more than 2 μm.Passivation layer 5 is deposited, such as SiO2/Si3N4, thickness can be respectively 500nm and 300nm.And carry out figure
Shape and selective etching expose the metal of electrode.Polyimides is coated with, is patterned, exposes the metal of electrode.It is toasted
Curing.Finally, overleaf deposition of electrode metal, such as TiNiAg, overall thickness are more than 1 μm.
It is described above simply to illustrate that of the invention, it is understood that the invention is not limited in above example, meet
The various variants of inventive concept are within protection scope of the present invention.
Claims (10)
1. a kind of groove-shaped low barrier Schottky diode, which is characterized in that the active area of the Schottky diode is groove
Structure, the top of table top is Schottky contacts, and the side wall and channel bottom of table top are the highly doped p-type area of electrical communication, and
Channel bottom forms p-type Ohmic contact；The depth of groove is dt, width Wt；Mesa width is Wm, the junction depth of the p-type area
For dp；Wherein, Wt is more than 1 μm, and Wm is more than 0.5 μm, and dt is more than 0.5 μm, and dp is more than 0.5 μm.
2. groove-shaped low barrier Schottky diode according to claim 1, which is characterized in that the Schottky diode
Buffer layer thickness for 0.5-2 μm, a concentration of 1E18cm-3；The concentration of drift layer is in 1E14cm-3-5E16cm-3Between, thickness
Between 5-200 μm；The concentration of channel layer is in 1E16-1E17cm-3Between, thickness is more than 0.5 μm；The concentration of barrier modulation layer
More than the concentration of the channel layer, thickness is less than 0.2 μm.
3. a kind of preparation method of any groove-shaped low barrier Schottky diodes of claim 1-2, which is characterized in that
Described method includes following steps：
1) it takes and has grown the epitaxial wafer for having barrier modulation layer or used ion implanting on the epitaxial wafer of no barrier modulation layer
Mode form barrier modulation layer, to n-type material injection N, P ion；Then the photo-etching mark on epitaxial wafer is done, using PECVD
Or LPCVD methods deposit SiO2Layer, and etched after carrying out photoetching, form the mask pattern of SiC etchings；With the grade of ICP or RIE from
Daughter lithographic method, with SiO2Layer is mask, and etching SiC forms groove；
2) knot termination environment is protected with photoresist, with reference to SiO remaining in step 1)2Layer carries out ion implanting for mask, and injection is
P-type Doped ions are repeatedly infused in bottom portion of groove, side wall forms a p-type doped region, removal mask after the completion of injection；It uses again
Photolithography method forms the mask of knot termination environment injection, carries out knot termination environment ion implanting, similary implanted with p-type Doped ions；
3) it anneals later into line activating as protection in device surface deposit a thin layer graphite linings；
4) graphite linings are removed, surface of SiC is cleaned；Sacrificial oxidation process is carried out later, is given birth to the method for thermal oxide
Long layer of oxide layer, then erode the oxide layer with HF or BOE；
5) thermal oxide growth SiO is carried out again2Passivation layer grows field dielectric layer, with photoetching, etching or BOE with PECVD or CVD method
The method of corrosion removes the medium in active area, retains the medium of knot termination environment, forms protection of the medium to termination environment；
6) metal ohmic contact is done in bottom portion of groove p areas with the method for photoetching, evaporated metal and stripping, the back side deposits metal,
It carries out short annealing and forms Ohmic contact；
7) in surface deposition metal, Schottky contacts are formed in the mesa top of active area, recess sidewall respectively；Then it is moved back
Fire processing, to improve the Schottky contacts of n-type surface；
8) it deposits and forms electrode metal, deposit dielectric passivation；And be patterned and selective etching, expose the metal of electrode；
Carry out baking-curing；Finally, overleaf deposition of electrode metal.
4. the preparation method of groove-shaped low barrier Schottky diode according to claim 3, which is characterized in that step 2)
In repeatedly injection be divided into part, first part is vertical injection, bottom portion of groove injection junction depth be more than 0.5 μm, concentration is more than
1E17cm-3P+ areas；Second part is vertical plus tilts injection, while form concentration on the surface of bottom portion of groove and recess sidewall
More than 1E19cm-3P+ areas.
5. the preparation method of groove-shaped low barrier Schottky diode according to claim 3, which is characterized in that step 3)
In activation annealing temperature be more than 1500 DEG C, the time be more than 3 minutes.
6. the preparation method of groove-shaped low barrier Schottky diode according to claim 3, which is characterized in that step 4)
The thickness of middle oxide layer is 10nm-50nm.
7. the preparation method of groove-shaped low barrier Schottky diode according to claim 3, which is characterized in that step 5)
Described in SiO2The thickness of passivation layer is 10nm-50nm, and the thickness of the field dielectric layer is more than 200nm.
8. the preparation method of groove-shaped low barrier Schottky diode according to claim 3, which is characterized in that step 6)
The temperature of middle short annealing is 950-1050 DEG C, and the time is 2-5 minutes.
9. the preparation method of groove-shaped low barrier Schottky diode according to claim 3, which is characterized in that step 7)
The annealing temperature of middle annealing is 400-800 DEG C.
10. the preparation method of groove-shaped low barrier Schottky diode according to claim 3, which is characterized in that step
8) electrode metal described in is Al or the Al for mixing Si, Cu, and the thickness of electrode metal is more than 3 μm.
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