CN116344625A - Gallium oxide rectifier and manufacturing process thereof, gallium oxide rectifier structure and manufacturing process thereof - Google Patents
Gallium oxide rectifier and manufacturing process thereof, gallium oxide rectifier structure and manufacturing process thereof Download PDFInfo
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 150
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 150
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000059 patterning Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 28
- 238000001259 photo etching Methods 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 5
- 238000009825 accumulation Methods 0.000 abstract description 2
- 239000000969 carrier Substances 0.000 abstract description 2
- 230000001419 dependent effect Effects 0.000 abstract 1
- 238000005566 electron beam evaporation Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 238000001704 evaporation Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The invention discloses a gallium oxide rectifier and a manufacturing process thereof, a gallium oxide rectifier structure and a manufacturing process thereof, and relates to the technical field of semiconductors, wherein the gallium oxide rectifier comprises the following structures: the gallium oxide substrate layer, the gallium oxide epitaxial layer, locate the upper surface of gallium oxide substrate layer; a cathode arranged on the upper surface of one side of the gallium oxide channel layer; a p-type semiconductor layer provided on an upper surface of the other side of the gallium oxide channel layer opposite to the cathode; the first anode layer is arranged on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode, is close to the p-type semiconductor layer and has a gap with the p-type semiconductor layer; the second anode layer is arranged on the upper surface of the p-type semiconductor layer; and a third anode layer electrically connecting the first anode layer and the second anode layer. The invention realizes rectification characteristic by utilizing accumulation and exhaustion of channel carriers, so that the invention is not dependent on barrier height and can break the trade-off between the starting voltage and the off-state leakage.
Description
Technical Field
The invention relates to the technical field of semiconductor structures, in particular to a gallium oxide rectifier and a manufacturing process thereof, and a gallium oxide rectifier structure and a manufacturing process thereof.
Background
Ideally, the smaller the turn-on voltage of the diode, the better the reverse leakage. There are two structures for gallium oxide existing diodes, including schottky diodes and hetero-pn junction diodes. Their rectification characteristics depend on the barrier height. The higher the barrier, the greater the turn-on voltage and the less reverse leakage. Conversely, the smaller the turn-on voltage, the greater the reverse leakage. The rectifying characteristics of schottky diodes are dominated by the thermionic emission model of the schottky junction. The PN junction is dominated by the minority carrier diffusion model. In either structure, the rectifying characteristics depend on the junction barrier height, and as is known from thermionic emission models, there must be an incompatibility between the low on voltage and the low off leakage.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a gallium oxide field effect rectifier structure for solving the problem of incompatibility between low starting voltage and low off-state electric leakage in the prior art.
In order to solve the technical problems, the invention is solved by the following technical scheme:
a gallium oxide rectifier comprising the structure:
a gallium oxide substrate layer,
the gallium oxide epitaxial layer is arranged on the upper surface of the gallium oxide substrate layer;
a cathode arranged on the upper surface of one side of the gallium oxide channel layer;
a p-type semiconductor layer provided on an upper surface of the other side of the gallium oxide channel layer opposite to the cathode;
the first anode layer is arranged on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode, is close to the p-type semiconductor layer and has a gap with the p-type semiconductor layer;
the second anode layer is arranged on the upper surface of the p-type semiconductor layer;
and a third anode layer electrically connecting the first anode layer and the second anode layer.
As one of the real-time modes, the p-type semiconductor layer adopts Si, niO, gaN, mgO, cu 2 O is any one material.
As one of the real-time modes, the gallium oxide substrate layer is a semi-insulating monocrystalline gallium oxide monocrystalline substrate doped with Fe or Mg.
As one of the real-time modes, the upper surface of the p-type semiconductor layer is partially covered by the second metal electrode, and the other part is an extension part which is not covered by the second metal electrode.
As one of the real-time modes, the doping ion concentration range of the gallium oxide epitaxial layer is 1e16 cm -3 To 1e18 cm -3 The thickness ranges from 50nm to 1500nm.
As one of the real-time modes, the thickness of the p-type semiconductor layer is 10nm-100nm;
as one of the real-time modes, the doping ion concentration of the gallium oxide epitaxial layer is 1e18 cm -3 The thickness of the gallium oxide epitaxial layer is 200nm.
The gallium oxide rectifier structure comprises more than two gallium oxide rectifiers, grooves are formed between two adjacent gallium oxide rectifiers, and the depth of each groove is larger than or equal to the thickness of a gallium oxide epitaxial layer.
The advanced technology provides a manufacturing process of the gallium oxide rectifier, which is used for manufacturing the gallium oxide rectifier and comprises the following steps:
selecting semi-insulating monocrystalline gallium oxide monocrystal as a gallium oxide substrate layer, and growing a gallium oxide epitaxial layer on the semi-insulating monocrystalline gallium oxide monocrystal;
patterning by adopting a photoetching method, and manufacturing an ohmic electrode on the upper surface of the gallium oxide epitaxial layer to form ohmic contact, a cathode and a first anode;
patterning by adopting a photoetching method, growing a p-type semiconductor layer on the upper surface of the gallium oxide epitaxial layer, and growing a second anode on the upper surface of the p-type semiconductor layer, wherein the second anode and the p-type semiconductor form ohmic contact;
patterning by photolithography, growing a third anode over the first anode and the second anode, the third anode connecting the first anode and the second electrode in contact with the p-type.
The advanced manufacturing process of the gallium oxide rectifier structure is provided, and the manufacturing process is used for manufacturing the gallium oxide rectifier structure and comprises the following steps:
selecting semi-insulating monocrystalline gallium oxide monocrystal as a gallium oxide substrate layer, and growing a gallium oxide epitaxial layer on the semi-insulating monocrystalline gallium oxide monocrystal;
etching a groove between two adjacent gallium oxide rectifiers;
patterning by adopting a photoetching method, and manufacturing an ohmic electrode on the upper surface of the gallium oxide epitaxial layer to form ohmic contact, a cathode and a first anode;
patterning by adopting a photoetching method, growing a p-type semiconductor layer on the upper surface of the gallium oxide epitaxial layer, and growing a second anode on the upper surface of the p-type semiconductor layer, wherein the second anode and the p-type semiconductor form ohmic contact;
patterning by photolithography, growing a third anode over the first anode and the second anode, the third anode connecting the first anode and the second electrode in contact with the p-type.
The invention has the beneficial effects that:
the invention provides a gallium oxide field effect rectifier structure, which utilizes accumulation and exhaustion of channel carriers to realize rectification characteristics, so that the balance between starting voltage and off-state leakage can be broken without depending on barrier height.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic diagram of a gallium oxide rectifier;
FIG. 2 is a schematic diagram of the conduction of a gallium oxide rectifier after application of a reverse voltage;
FIG. 3 is a schematic diagram of the conduction of a gallium oxide rectifier after a small forward voltage is applied;
FIG. 4 is a schematic diagram of the conduction of a gallium oxide rectifier after a forward larger voltage is applied;
FIG. 5 is a schematic diagram of a gallium oxide rectifier with grooves;
fig. 6 is a schematic diagram of another gallium oxide rectifier disclosed in example 3;
FIG. 7 is a schematic diagram of a gallium oxide rectifier structure;
fig. 8 is a flow chart of a gallium oxide rectifier fabrication process.
Detailed Description
Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Example 1:
a gallium oxide rectifier, as in fig. 1, comprising the structure:
a gallium oxide substrate layer,
the gallium oxide epitaxial layer is arranged on the upper surface of the gallium oxide substrate layer, namely a gallium oxide channel;
the cathode is arranged on the upper surface of one side of the gallium oxide channel layer and can adopt Ti/Au;
a p-type semiconductor layer arranged on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode, wherein the p-type semiconductor layer comprises NiO, si, gaN, mgO or Cu 2 An O material;
the first anode layer is arranged on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode, is close to the p-type semiconductor layer and has a gap with the p-type semiconductor layer;
the second anode layer is arranged on the upper surface of the p-type semiconductor layer and adopts Ni/Au, pt/Au metal and the like;
and the third anode layer is electrically connected with the first anode layer and the second anode layer, and Au metal can be adopted.
Wherein the third anode layer may be made of any conductive metal, and the p-type semiconductor layer, the first anode layer, the second anode layer, and the third anode layer as a whole are regarded as an anode. When negative voltage is applied to the cathode of the rectifier, the channel under the grid electrode of the transistor is exhausted due to low-potential electrons, so that current cannot pass. When a positive voltage is applied to the cathode of the rectifier, a channel under the original transistor gate is accumulated by high-potential electrons, so that current can pass through. Thereby achieving unidirectional conductivity. The rectifier structure realized by adopting the principle can realize the starting voltage close to 0 volt only by controlling the channel to a certain extent, and can have lower reverse electric leakage.
The schematic diagrams of rectifying characteristics of the device are shown in fig. 2 to 4. When a reverse voltage is applied to the anode, a depletion region is formed under the p-type semiconductor, and the device is in an off state as shown in fig. 2. When a small forward voltage is applied to the anode, i.e., the anode applied voltage is greater than 0V and less than the turn-on voltage of the pn junction, the depletion region under the p-type semiconductor decreases and the device is in an on state but with a small current, as shown in fig. 3. When a larger forward voltage is applied to the anode, namely the voltage is larger than the starting voltage of the pn junction, the depletion region under the p-type semiconductor disappears, the device is in an on state, the pn junction is conducted, the two paths of currents are combined, and the overall current becomes larger, as shown in fig. 4.
Wherein, the gallium oxide substrate layer adopts a semi-insulating monocrystalline gallium oxide monocrystalline substrate doped with Mg. As other embodiments, the gallium oxide substrate layer may also be a Fe-doped semi-insulating monocrystalline gallium oxide single crystal substrate.
As a preferable scheme, grooves are formed in the gallium oxide epitaxial layers on the outer sides of the cathode and the anode of the gallium oxide rectifier, and the depth of the grooves is larger than or equal to the thickness of the gallium oxide epitaxial layers. As shown in fig. 5, grooves are formed in the gallium oxide epitaxial layers on the outer sides of the cathode and the anode, so that current can flow through the opposite surfaces of the cathode and the anode, and the product performance is higher.
As a preferable scheme, the doping ion concentration of the gallium oxide epitaxial layer is in the range of 1e16 cm -3 To 1e18 cm -3 The thickness is 50nm to 1500nm, and further preferably can be 100-600nm, and the doped ion concentration of the gallium oxide epitaxial layer is 1e16 cm -3 To 1e18 cm -3 ；
As a preferred embodiment, the thickness of the p-type semiconductor layer is 10nm to 100nm.
Example 2:
in the technology of embodiment 1, a gallium oxide rectifier structure is further disclosed, which includes more than two gallium oxide rectifiers described in embodiment 1, a groove is disposed between two adjacent gallium oxide rectifiers, and the depth of the groove is greater than or equal to the thickness of the gallium oxide epitaxial layer.
In order to isolate more than two devices on the same wafer from each other and prevent crosstalk between the devices, some gallium oxide rectifier products need to isolate devices from each other, as shown in fig. 1, the depth of the groove is greater than or equal to the thickness of the gallium oxide epitaxial layer, as shown in fig. 7, if the depth of the groove is less than the thickness of the gallium oxide epitaxial layer, crosstalk between a plurality of devices cannot be completely avoided.
Example 3:
on the basis of embodiment 1 or embodiment 2, still another gallium oxide rectifier is further disclosed, as shown in fig. 6, comprising the following structure:
a gallium oxide substrate layer,
the gallium oxide epitaxial layer is arranged on the upper surface of the gallium oxide substrate layer, namely a gallium oxide channel;
a cathode arranged on the upper surface of one side of the gallium oxide channel layer;
a p-type semiconductor layer provided on an upper surface of the other side of the gallium oxide channel layer opposite to the cathode;
the first anode layer is arranged on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode, is close to the p-type semiconductor layer, and is a Ti/Au layer, wherein a gap is formed between the first anode layer and the p-type semiconductor layer;
the second anode layer is arranged on the upper surface of the p-type semiconductor layer and is a Ni/Au layer;
and a third anode layer electrically connecting the first anode layer and the second anode layer.
Wherein, the upper surface part of the p-type semiconductor layer is covered by the second metal electrode, and the other part is an extension part which is not covered by the second metal electrode. The structural design extends out the p-type semiconductor layer, so that the breakdown voltage of the device can be effectively improved.
Example 4:
the embodiment discloses a gallium oxide rectifier manufacturing process, which is used for manufacturing the gallium oxide rectifier disclosed above, and comprises the following steps:
selecting semi-insulating monocrystalline gallium oxide monocrystal as a gallium oxide substrate layer, and growing a gallium oxide epitaxial layer on the semi-insulating monocrystalline gallium oxide monocrystal;
patterning by adopting a photoetching method, and manufacturing an ohmic electrode on the upper surface of the gallium oxide epitaxial layer to form ohmic contact, a cathode and a first anode;
patterning by adopting a photoetching method, growing a p-type semiconductor layer on the upper surface of the gallium oxide epitaxial layer, and growing a second anode on the upper surface of the p-type semiconductor layer, wherein the second anode and the p-type semiconductor form ohmic contact;
patterning by photolithography, growing a third anode over the first anode and the second anode, the third anode connecting the first anode and the second electrode in contact with the p-type.
The present embodiment proposes a more specific scheme, and the disclosure related parameters are used as references:
step 1, selecting a Fe doped semi-insulating monocrystalline gallium oxide monocrystalline substrate layer, growing a 200nm gallium oxide epitaxial layer with the concentration of 1e18 cm -3 。
Step 2, patterning by adopting a photoetching means, evaporating and plating 20nm Ti and 200nm Au ohmic electrodes by utilizing electron beam evaporation to form ohmic contact, wherein a cathode and a first anode, namely the cathode and the first anode are both Ti/Au layers;
and 3, patterning by adopting a photoetching method, growing 50nm p-type NiO by using a magnetron sputtering or pulse laser deposition method to obtain a p-type semiconductor layer, and growing 20nm Ni and 200nm Au metal electrodes by using an electron beam evaporation method to obtain a second anode, wherein the second anode and the p-type semiconductor layer form ohmic contact.
And 4, patterning by adopting a photoetching method, evaporating 20nm Ni and 200nm Au metal by utilizing an electron beam evaporation mode to obtain a third anode, and connecting an ohmic electrode with a p-type contact electrode by the third anode.
(II) this embodiment proposes another scheme, and the relevant parameters are disclosed as references:
step 10, a semi-insulating monocrystalline gallium oxide monocrystalline substrate doped with Mg is selected, an epitaxial layer with the thickness of 5e17cm is grown at 400nm -3 ；
Step 20, patterning by adopting a photoetching means, evaporating and plating 20nm Ti and 200nm Au ohmic electrodes by utilizing electron beam evaporation to form ohmic contact, and preparing a cathode and a first anode at the moment;
step 30, patterning by adopting a photoetching method, and growing 50nm p-type Cu by using a magnetron sputtering or pulse laser deposition method 2 O, obtaining a p-type semiconductor layer, growing a 20nm Pt and 200nm Au metal electrode by using an electron beam evaporation method, and obtaining a second anode, wherein the second anode and the p-type semiconductor form ohmic contact;
and step 40, patterning by adopting a photoetching method, evaporating 200nm Au metal by utilizing an electron beam evaporation mode to obtain a third anode, and connecting an ohmic electrode with a p-type contact electrode by the third anode.
Example 5
In some fabrication processes, a plurality of gallium oxide rectifiers in series are fabricated on the same wafer, referring to fig. 8, comprising the steps of:
selecting semi-insulating monocrystalline gallium oxide monocrystal as a gallium oxide substrate layer, and growing a gallium oxide epitaxial layer on the semi-insulating monocrystalline gallium oxide monocrystal;
etching a groove between two adjacent gallium oxide rectifiers;
patterning by adopting a photoetching method, and manufacturing an ohmic electrode on the upper surface of the gallium oxide epitaxial layer to form ohmic contact, a cathode and a first anode;
patterning by adopting a photoetching method, growing a p-type semiconductor layer on the upper surface of the gallium oxide epitaxial layer, and growing a second anode on the upper surface of the p-type semiconductor layer, wherein the second anode and the p-type semiconductor form ohmic contact;
patterning by photolithography, growing a third anode over the first anode and the second anode, the third anode connecting the first anode and the second electrode in contact with the p-type.
The embodiment proposes a more specific scheme, and discloses relevant parameters as references:
step 100, selecting Fe doped semi-insulating monocrystalline gallium oxide monocrystalline substrate, growing 200nm epitaxial layer with concentration of 1e18 cm -3 ；
Step 200, device isolation manufacturing: with BCl 3 And Ar or Cl 2 As etching gas, performing inductively coupled plasma etching with etching depth of 400nm to form grooves between two adjacent anodes or cathodes, so as to avoid series interference;
step 300, patterning by adopting a photoetching means, evaporating and plating 20nm Ti and 200nm Au ohmic electrodes by utilizing electron beam evaporation to form ohmic contact, wherein a cathode and a first anode, namely the cathode and the first anode are both Ti/Au layers;
step 400, patterning by adopting a photoetching method, growing 50nm p-type NiO by using a magnetron sputtering or pulse laser deposition method to obtain a p-type semiconductor layer, and growing 20nm Ni and 200nm Au metal electrodes by using an electron beam evaporation method to obtain a second anode, wherein the second anode and the p-type semiconductor form ohmic contact;
and 500, patterning by adopting a photoetching method, evaporating 20nm Ni and 200nm Au metal by utilizing an electron beam evaporation mode to obtain a third anode, and connecting an ohmic electrode with a p-type contact electrode by the third anode.
The present embodiment proposes another scheme, and discloses relevant parameters as references:
step a, a semi-insulating monocrystalline gallium oxide monocrystalline substrate doped with Mg is selected, an epitaxial layer with the concentration of 5e17cm is grown at 400nm -3 ；
Step b, device isolation manufacturing: with BCl 3 And Ar or Cl 2 As an etching gas, performingInductively coupled plasma etching with etching depth of 600nm to form grooves between two adjacent anodes or cathodes to avoid series interference;
c, patterning by adopting a photoetching means, evaporating and plating 20nm Ti and 200nm Au ohmic electrodes by utilizing electron beam evaporation to form ohmic contact, and preparing a cathode and a first anode at the moment;
step d, patterning by adopting a photoetching method, and growing 50nm p-type Cu by using a magnetron sputtering or pulse laser deposition method 2 O, growing a 20nm Pt and 200nm Au metal electrode by using an electron beam evaporation method to obtain a second anode, wherein the second anode and the p-type semiconductor form ohmic contact;
and e, patterning by adopting a photoetching method, evaporating 200nm Au metal by utilizing an electron beam evaporation mode to obtain a third anode, and connecting an ohmic electrode with a p-type contact electrode by the third anode.
The foregoing is merely illustrative of specific embodiments of the present invention, and the scope of the present invention is not limited thereto, but any changes or substitutions within the technical scope of the present invention should be covered by the scope of the present invention. Meanwhile, the above embodiments and the technical solutions between the embodiments may be arbitrarily combined. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A gallium oxide rectifier characterized by comprising the following structure:
a gallium oxide substrate layer,
the gallium oxide epitaxial layer is arranged on the upper surface of the gallium oxide substrate layer;
a cathode arranged on the upper surface of one side of the gallium oxide channel layer;
a p-type semiconductor layer provided on an upper surface of the other side of the gallium oxide channel layer opposite to the cathode;
the first anode layer is arranged on the upper surface of the other side of the gallium oxide channel layer opposite to the cathode, is close to the p-type semiconductor layer and has a gap with the p-type semiconductor layer;
the second anode layer is arranged on the upper surface of the p-type semiconductor layer;
and a third anode layer electrically connecting the first anode layer and the second anode layer.
2. The gallium oxide rectifier of claim 1 wherein said p-type semiconductor layer employs Si, niO, gaN, mgO, cu 2 O is any one material.
3. Gallium oxide rectifier according to claim 1, wherein the gallium oxide substrate layer is a Fe or Mg doped semi-insulating monocrystalline gallium oxide monocrystalline substrate.
4. The gallium oxide rectifier of claim 1, wherein an upper surface portion of said p-type semiconductor layer is covered by a second metal electrode and another portion is an extension portion not covered by the second metal electrode.
5. A gallium oxide rectifier according to claim 1 or 3, wherein the gallium oxide epitaxial layer has a dopant ion concentration in the range of 1e16 cm -3 To 1e18 cm -3 The thickness ranges from 50nm to 1500nm.
6. Gallium oxide rectifier according to claim 1 or 2, characterized in that the p-type semiconductor layer has a thickness of 10nm-100nm.
7. Gallium oxide rectifier according to claim 1, characterized in that the doping ion concentration of the gallium oxide epitaxial layer is 1e18 cm -3 The thickness of the gallium oxide epitaxial layer is 200nm.
8. A gallium oxide rectifier structure, characterized by comprising more than two gallium oxide rectifiers of claims 1-7, wherein a groove is arranged between two adjacent gallium oxide rectifiers, and the depth of the groove is greater than or equal to the thickness of the gallium oxide epitaxial layer.
9. A process for manufacturing a gallium oxide rectifier according to any one of claims 1 to 7, comprising the steps of:
selecting semi-insulating monocrystalline gallium oxide monocrystal as a gallium oxide substrate layer, and growing a gallium oxide epitaxial layer on the semi-insulating monocrystalline gallium oxide monocrystal;
patterning by adopting a photoetching method, and manufacturing an ohmic electrode on the upper surface of the gallium oxide epitaxial layer to form ohmic contact, a cathode and a first anode;
patterning by adopting a photoetching method, growing a p-type semiconductor layer on the upper surface of the gallium oxide epitaxial layer, and growing a second anode on the upper surface of the p-type semiconductor layer, wherein the second anode and the p-type semiconductor form ohmic contact;
patterning by photolithography, growing a third anode over the first anode and the second anode, the third anode connecting the first anode and the second electrode in contact with the p-type.
10. A process for fabricating a gallium oxide rectifier structure according to any one of claims 8, comprising the steps of:
selecting semi-insulating monocrystalline gallium oxide monocrystal as a gallium oxide substrate layer, and growing a gallium oxide epitaxial layer on the semi-insulating monocrystalline gallium oxide monocrystal;
etching a groove between two adjacent gallium oxide rectifiers;
patterning by adopting a photoetching method, and manufacturing an ohmic electrode on the upper surface of the gallium oxide epitaxial layer to form ohmic contact, a cathode and a first anode;
patterning by adopting a photoetching method, growing a p-type semiconductor layer on the upper surface of the gallium oxide epitaxial layer, and growing a second anode on the upper surface of the p-type semiconductor layer, wherein the second anode and the p-type semiconductor form ohmic contact;
patterning by photolithography, growing a third anode over the first anode and the second anode, the third anode connecting the first anode and the second electrode in contact with the p-type.
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