CN110112207B - Gallium oxide-based mixed PiN Schottky diode and preparation method thereof - Google Patents
Gallium oxide-based mixed PiN Schottky diode and preparation method thereof Download PDFInfo
- Publication number
- CN110112207B CN110112207B CN201910417281.3A CN201910417281A CN110112207B CN 110112207 B CN110112207 B CN 110112207B CN 201910417281 A CN201910417281 A CN 201910417281A CN 110112207 B CN110112207 B CN 110112207B
- Authority
- CN
- China
- Prior art keywords
- gallium oxide
- layer
- type
- voltage
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 93
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 92
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims 3
- 238000010030 laminating Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 7
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 58
- 229910001020 Au alloy Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 229910000990 Ni alloy Inorganic materials 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 3
- 229910001260 Pt alloy Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
- H01L29/247—Amorphous materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
The invention discloses a gallium oxide-based mixed PiN Schottky diode and a preparation method thereof, and relates to the technical field of semiconductor devices. The method aims to solve the problems that the doping difficulty of P-type gallium oxide in the prior art is very high, and the prior art cannot achieve high enough doping concentration and cannot be applied to normal devices. A diode with a mixed PiN Schottky structure is realized by inserting a p-type oxide semiconductor layer into the surface of a gallium oxide voltage-resistant layer. The p-type doping problem of the gallium oxide material is ingeniously avoided, the reverse breakdown voltage and the leakage current of the diode are determined by the heterogeneous PN junction, and the diode has better voltage resistance while ensuring good forward opening characteristics.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a gallium oxide-based mixed PiN Schottky diode and a preparation method thereof.
Background
Rectifier diodes are widely used in switching power supplies, frequency converters, drivers, and other circuits. Gallium oxide (Ga)2O3) The semiconductor has an ultra-wide forbidden band of up to 4.8eV and an ultra-large breakdown field strength of 8MV/cm, and a large-size single crystal substrate can be prepared by a low-cost melting growth method, so that the semiconductor is an ideal material for preparing a high-power rectifier diode. However, since there is no reliable method for p-type doping of gallium oxide material, the existing gallium oxide-based diodes mostly adopt Schottky barrier structures (see documents k. konishi, et al.,1-kV vertical Ga2O3 field-planar Schottky barrier diodes, applied physics Letters 110(10),103506,2017 and chinese patent CN 106876484 a). Compared with PN junction diode, Schottky barrier diode has low forward turn-on voltage and short reverse recovery time, but has large reverse leakage current and low breakdown voltageAnd the temperature characteristics of the schottky barrier diode are relatively poor.
Although some patent documents cover diodes made of p-type gallium oxide materials, the diodes are all of a single anode structure, and a mixed PiN dual anode structure cannot be realized. Meanwhile, the doping difficulty of the P-type gallium oxide is very high, and the existing technology cannot achieve high enough doping concentration, so that the P-type gallium oxide can not be applied to normal devices at all.
Disclosure of Invention
In order to solve the problems in the prior art, the present invention aims to provide a gallium oxide-based mixed PiN schottky diode with a sufficiently high current density and a method for manufacturing the same.
The invention relates to a gallium oxide-based mixed PiN Schottky diode, which comprises: the gallium oxide voltage-withstanding layer is provided with a plurality of steps extending through the p-type oxide semiconductor layer on one side close to the p-type oxide semiconductor layer, and the steps penetrate through the p-type oxide semiconductor layer and then are contacted with the anode layer; the anode layer is in Schottky contact with the step of the gallium oxide voltage-withstanding layer; the anode layer is in Schottky or ohmic contact with the p-type oxide semiconductor layer.
Preferably, the anode layer comprises a first anode electrode and a second anode electrode, and the first anode electrode is in schottky or ohmic contact with the p-type oxide semiconductor layer; the second anode electrode is in Schottky contact with the step; the second anode electrode is coated outside the first anode electrode.
Preferably, the gallium oxide voltage-withstanding layer is of an n-type doped single crystal structure.
Preferably, the doping concentration of the gallium oxide voltage-withstanding layer is 5 × 1014cm-3To 1X 1018cm-3。
Preferably, the thickness of the gallium oxide pressure-resistant layer is 2 μm-5 mm.
Preferably, the p-type oxide semiconductor layer has an amorphous or polycrystalline structure and holesThe concentration is 1X 1017/cm3～1×1020/cm3。
Preferably, the doping concentration of the n-type doped gallium oxide substrate is 5 x 1017cm-3～1×1020cm-3。
A preparation method of a gallium oxide-based mixed PiN Schottky diode comprises a preparation step of a gallium oxide-based wafer, a step of preparing an electrode on the gallium oxide-based wafer, a step of etching a plurality of steps on the gallium oxide-based wafer, and a step of filling a p-type oxide semiconductor layer between the steps; so that the anode is in Schottky contact with the gallium oxide-based wafer and in Schottky or ohmic contact with the p-type oxide semiconductor layer.
Preferably, the preparation step of the gallium oxide-based wafer is to epitaxially grow an n-type doped gallium oxide voltage-withstanding layer on an n-type doped gallium oxide substrate; the step is obtained by etching the gallium oxide voltage-withstanding layer at the side far away from the n-type doped gallium oxide substrate.
Preferably, the step of preparing an electrode on the gallium oxide-based wafer comprises: depositing metal on the p-type oxide semiconductor layer to form ohmic contact or Schottky contact to prepare a first anode electrode; and depositing metal on the first anode electrode and the gallium oxide voltage-withstanding layer to form Schottky contact with the gallium oxide voltage-withstanding layer, so as to obtain a second anode electrode.
The gallium oxide-based mixed PiN Schottky diode and the preparation method thereof have the advantages that a heterogeneous PN junction is formed by adopting the amorphous or polycrystalline p-type oxide semiconductor and the single-crystal gallium oxide, the p-type doping problem of the gallium oxide material is ingeniously avoided, the reverse breakdown voltage and the leakage current of the diode are determined by the heterogeneous PN junction, and the diode has better withstand voltage characteristic while ensuring good forward opening characteristic. The size design of the step is related to parameters such as doping concentration and design withstand voltage of the device, mainly inversely related to the concentration of the gallium oxide withstand voltage layer, positively related to the design withstand voltage of the device, and simultaneously positively related to the concentration of the p-type oxide semiconductor layer. The size of the step is as long as the condition is satisfied: under reverse bias, the heterojunction PN junction depletion regions communicate with each other.
Drawings
Fig. 1 is a schematic structural diagram of a gallium oxide-based hybrid PiN schottky diode according to the present invention;
FIG. 2 is a schematic diagram of a longitudinal cross-sectional structure of a gallium oxide-based hybrid PiN Schottky diode according to the present invention;
fig. 3 is a cross-sectional view at a-a in fig. 2.
Fig. 4 is a schematic diagram comparing forward current curves of a gallium oxide based hybrid PiN schottky diode of the present invention with a conventional gallium oxide based schottky barrier diode;
fig. 5 is a schematic diagram comparing reverse current curves of the gallium oxide-based hybrid PiN schottky diode of the present invention and a conventional gallium oxide-based schottky barrier diode.
Reference numerals: 101-cathode electrode, 102-n type doped gallium oxide substrate, 103-gallium oxide voltage-withstanding layer, 104-p type oxide semiconductor layer, 105-first anode electrode, 106-second anode electrode.
Detailed Description
As shown in fig. 1-3, a cathode electrode 101, an n-type doped gallium oxide substrate 102, a gallium oxide voltage-withstanding layer 103, a p-type oxide semiconductor layer 104, and an anode layer are sequentially stacked, wherein a plurality of steps extending through the p-type oxide semiconductor layer 104 are disposed on one side of the gallium oxide voltage-withstanding layer 103 close to the p-type oxide semiconductor layer 104, and the steps extend through the p-type oxide semiconductor layer 104 and then contact the anode layer; the anode layer is in Schottky contact with the step of the gallium oxide voltage-withstanding layer 103; the anode layer is in schottky or ohmic contact with the p-type oxide semiconductor layer 104. The n-type doped gallium oxide substrate 102 and the cathode electrode 101 are in ohmic contact. The anode layer comprises a first anode electrode 105 and a second anode electrode 106, wherein the first anode electrode 105 is in Schottky or ohmic contact with the p-type oxide semiconductor layer 104; the second anode electrode 106 is in schottky contact with the step; the second anode electrode 106 is coated outside the first anode electrode 105. Said oxidationThe gallium voltage-withstanding layer 103 is of an n-type doped single crystal structure with a doping concentration of 5 × 1014cm-3To 1X 1018cm-3The thickness is 2 mu m-5 mm. The thickness includes the height of the step. The p-type oxide semiconductor layer 104 has an amorphous or polycrystalline structure and a hole concentration of 1 × 1017/cm3～1×1020/cm3. The doping concentration of the n-type doped gallium oxide substrate 102 is 5 multiplied by 1017cm-3～1×1020cm-3。
By adopting the amorphous or polycrystalline p-type oxide semiconductor and the single crystal gallium oxide to form the heterogeneous PN junction, the p-type doping problem of the gallium oxide material is ingeniously avoided, and the high electric field is shielded by the heterogeneous PN junction, so that the whole device has the forward turn-on characteristic of a Schottky diode and has the reverse withstand voltage characteristic similar to a Pin diode. The reverse breakdown voltage and the leakage current of the diode are determined by the heterojunction PN junction, and the diode has better voltage resistance while ensuring good forward starting characteristic. The dimension of the step is designed in such a way that the dimension is related to parameters such as doping concentration and design withstand voltage of the device, mainly inversely related to the concentration of the gallium oxide withstand voltage layer 103, positively related to the design withstand voltage of the device, and also positively related to the concentration of the p-type oxide semiconductor layer 104. The size of the step is as long as the condition is satisfied: under reverse bias, the heterojunction PN junction depletion regions communicate with each other. Under the technical conception provided by the invention, a person skilled in the art can completely obtain the step size meeting the requirements of certain parameters through limited times of tests without creative labor. The particular step size is therefore a technical measure clear to the skilled person. Such as: the concentration of the gallium oxide voltage-withstanding layer 103 is 8 × 1015cm-3The designed withstand voltage was 2kV, and the concentration of the p-type oxide semiconductor layer 104 was 1.5X 1018cm-3In the case of (2), the height of the step may be 500nm and the step pitch may be 2 μm.
The p-type oxide semiconductor layer 104 corresponds to p in the mixed PiN structure, the gallium oxide voltage-withstanding layer 103 corresponds to i layer in the PiN structure, and the n-type doped gallium oxide substrate 102 corresponds to n in the mixed PiN structure.
As shown in fig. 4 and 5, which are forward and reverse comparisons between the gan-based hybrid PiN schottky diode of the present invention and the conventional gan-based schottky barrier diode, the abscissa is the bias voltage applied to the diode device and the ordinate is the current of the device, and it can be seen that the gan-based hybrid PiN schottky diode of the present invention has smaller reverse leakage current and higher breakdown voltage than the conventional gan-based schottky barrier diode, while maintaining excellent forward turn-on characteristics of low turn-on voltage and high on-current.
The invention also provides a method for preparing the gallium oxide-based mixed PiN Schottky diode, which comprises the following steps:
epitaxially growing an n-type doped gallium oxide voltage-withstanding layer 103 on the n-type doped gallium oxide substrate 102 to obtain a gallium oxide-based wafer;
etching a groove on one side of the gallium oxide voltage-resisting layer 103 far away from the n-type doped gallium oxide substrate 102, and isolating the upper part of the gallium oxide voltage-resisting layer 103 into a plurality of steps separated from each other;
depositing an amorphous or polycrystalline p-type oxide semiconductor in the groove to obtain a p-type oxide semiconductor layer 104, and forming a heterojunction PN junction with the gallium oxide voltage-withstanding layer 103; the p-type oxide semiconductor layer 104 can be NiO or Cu prepared by magnetron sputtering, solution method, metal oxide method, physical or chemical vapor deposition and the like2O or other p-type oxide semiconductor material with single layer or multiple layers;
depositing metal on the upper surface of the p-type oxide semiconductor layer 104 to form ohmic contact or Schottky contact, and preparing a first anode electrode 105; the first anode electrode 105 can be made of Ni/Au alloy or Pt/Au alloy deposited by adopting a magnetron sputtering or electron beam evaporation method;
depositing metal on the upper surfaces of the first anode electrode 105 and the gallium oxide voltage-withstanding layer 103, and forming Schottky contact with the surface of the gallium oxide voltage-withstanding layer 103 to obtain a second anode electrode 106; the second anode electrode 106 can be made of Ni/Au alloy or Pt/Au alloy by magnetron sputtering or electron beam evaporation;
etching or grinding to thin the n-type doped gallium oxide substrate 102, and depositing metal on the lower surface of the n-type doped gallium oxide substrate 102 to form ohmic contact to prepare a cathode electrode 101; the cathode 101 may be made of Ti/Au alloy or Ti/Al/Ni/Au alloy deposited by magnetron sputtering or electron beam evaporation.
It will be apparent to those skilled in the art that various other changes and modifications may be made in the above-described embodiments and concepts and all such changes and modifications are intended to be within the scope of the appended claims.
Claims (9)
1. A gallium oxide-based hybrid PiN Schottky diode, comprising: the GaN-based light-emitting diode comprises a cathode electrode (101), an n-type doped GaN substrate (102), a GaN voltage-withstanding layer (103), a p-type oxide semiconductor layer (104) and an anode layer which are sequentially stacked, wherein one side, close to the p-type oxide semiconductor layer (104), of the GaN voltage-withstanding layer (103) is provided with a plurality of steps which extend through the p-type oxide semiconductor layer (104), and the steps penetrate through the p-type oxide semiconductor layer (104) and then are in contact with the anode layer; the anode layer is in Schottky contact with the step of the gallium oxide voltage-withstanding layer (103); the anode layer is in Schottky or ohmic contact with the p-type oxide semiconductor layer (104); the anode layer comprises a first anode electrode (105) and a second anode electrode (106), wherein the first anode electrode (105) is in Schottky or ohmic contact with the p-type oxide semiconductor layer (104); the second anode electrode (106) is in Schottky contact with the step; the second anode electrode (106) is coated outside the first anode electrode (105).
2. The gallium oxide-based hybrid PiN Schottky diode according to claim 1, wherein the gallium oxide voltage-withstanding layer (103) is of an n-type doped single crystal structure.
3. The gan-based hybrid PiN schottky diode of claim 2 wherein the gan voltage barrier (103) is doped at a concentration of 5 x 1014cm-3To 1X 1018cm-3。
4. The gallium oxide-based hybrid PiN Schottky diode according to claim 1, wherein the thickness of the gallium oxide voltage-withstanding layer (103) is 2 μm-5 mm.
5. The gan-based hybrid PiN schottky diode of claim 1 wherein the p-type oxide semiconductor layer (104) is amorphous or polycrystalline with a hole concentration of 1 x 1017/cm3～1×1020/cm3。
6. The gan-based hybrid PiN schottky diode of claim 1 wherein the n-type doped gan substrate (102) is doped at a concentration of 5 x 1017cm-3～1×1020cm-3。
7. A preparation method of a gallium oxide-based mixed PiN Schottky diode comprises a preparation step of a gallium oxide-based wafer and a step of preparing an electrode on the gallium oxide-based wafer, and is characterized by further comprising a step of etching a plurality of steps on the gallium oxide-based wafer and a step of filling a p-type oxide semiconductor layer (104) between the steps; making the anode in Schottky contact with the gallium oxide-based wafer and in Schottky or ohmic contact with the p-type oxide semiconductor layer (104); the gallium oxide-based wafer is formed by laminating an n-type doped gallium oxide substrate (102) and a gallium oxide voltage-withstanding layer (103).
8. The preparation method of the gallium oxide-based mixed Pin Schottky diode according to claim 7, wherein the preparation step of the gallium oxide-based wafer is to epitaxially grow an n-type doped gallium oxide voltage-withstanding layer (103) on an n-type doped gallium oxide substrate (102); the step is obtained by etching the side of the gallium oxide voltage-withstanding layer (103) far away from the n-type doped gallium oxide substrate (102).
9. The method of claim 8, wherein the step of fabricating an electrode on the gallium oxide-based wafer comprises: depositing metal on the p-type oxide semiconductor layer (104) to form ohmic contact or Schottky contact to prepare a first anode electrode (105); and depositing metal on the first anode electrode (105) and the gallium oxide voltage-withstanding layer (103) to form Schottky contact with the gallium oxide voltage-withstanding layer (103) to obtain a second anode electrode (106).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910417281.3A CN110112207B (en) | 2019-05-20 | 2019-05-20 | Gallium oxide-based mixed PiN Schottky diode and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910417281.3A CN110112207B (en) | 2019-05-20 | 2019-05-20 | Gallium oxide-based mixed PiN Schottky diode and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110112207A CN110112207A (en) | 2019-08-09 |
| CN110112207B true CN110112207B (en) | 2020-05-05 |
Family
ID=67490937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910417281.3A Active CN110112207B (en) | 2019-05-20 | 2019-05-20 | Gallium oxide-based mixed PiN Schottky diode and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110112207B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110783413B (en) * | 2019-11-08 | 2023-05-09 | 中国电子科技集团公司第十三研究所 | Preparation method of gallium oxide with transverse structure and gallium oxide with transverse structure |
| CN111739945A (en) * | 2020-06-17 | 2020-10-02 | 中山大学 | Diamond inclined table top heterojunction diode and preparation method thereof |
| CN112133757B (en) * | 2020-10-07 | 2022-03-04 | 西安电子科技大学 | Gate-controlled gallium oxide field effect transistor based on p-i-n structure and preparation method thereof |
| CN112186032A (en) * | 2020-10-20 | 2021-01-05 | 西安电子科技大学 | Gallium oxide junction barrier Schottky diode with field plate structure |
| CN112614781B (en) * | 2020-11-30 | 2023-01-17 | 中国电子科技集团公司第十三研究所 | Preparation method and structure of gallium oxide SBD |
| CN113066870B (en) * | 2021-03-25 | 2022-05-24 | 电子科技大学 | Gallium oxide-based junction barrier Schottky diode with terminal structure |
| CN113964211A (en) * | 2021-09-13 | 2022-01-21 | 西安电子科技大学 | Groove P-type modulated gallium oxide power diode and preparation method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6131949B2 (en) * | 2012-06-01 | 2017-05-24 | 三菱化学株式会社 | Method for producing metal oxide-containing semiconductor layer and electronic device |
| CN104091835A (en) * | 2014-06-17 | 2014-10-08 | 中国科学院半导体研究所 | Gallium nitride heterojunction schottky barrier diode and manufacturing method thereof |
| JP6690320B2 (en) * | 2016-03-11 | 2020-04-28 | 住友電気工業株式会社 | High electron mobility transistor and method of manufacturing high electron mobility transistor |
| CN107026209A (en) * | 2017-04-20 | 2017-08-08 | 中国科学院微电子研究所 | Junction barrier schottky diode based on gallium oxide and preparation method thereof |
| CN108376716A (en) * | 2018-03-01 | 2018-08-07 | 无锡华亿投资有限公司 | A kind of novel oxidized gallium base PIN structural UV photodetector and preparation method thereof |
| CN109192779B (en) * | 2018-08-28 | 2021-10-26 | 电子科技大学 | Silicon carbide MOSFET device and manufacturing method thereof |
-
2019
- 2019-05-20 CN CN201910417281.3A patent/CN110112207B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110112207A (en) | 2019-08-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110112207B (en) | Gallium oxide-based mixed PiN Schottky diode and preparation method thereof | |
| US11355594B2 (en) | Diode | |
| WO2018150451A1 (en) | Power semiconductor device | |
| WO2019003861A1 (en) | Oxide semiconductor device, and, method for manufacturing oxide semiconductor device | |
| CN107978642B (en) | GaN-based heterojunction diode and preparation method thereof | |
| US9171914B2 (en) | Semiconductor device | |
| CN113725296B (en) | Nitride semiconductor epitaxial lamination structure and power element thereof | |
| CN110148625B (en) | Gallium oxide vertical junction field effect transistor and preparation method thereof | |
| US20220115544A1 (en) | Semiconductor device | |
| CN111192928B (en) | Vertical GaN Schottky device structure with high breakdown voltage and low reverse leakage | |
| CN110085681A (en) | A kind of gallium oxide PN heterojunction diode and preparation method thereof | |
| CN115775730B (en) | GaN Schottky diode with quasi-vertical structure and preparation method thereof | |
| CN110416318A (en) | A kind of gallium nitride based diode structure and preparation method thereof | |
| CN110379863A (en) | A kind of silicon carbide junction barrier schottky diodes | |
| CN210349845U (en) | Silicon carbide junction barrier Schottky diode | |
| CN110676308A (en) | Preparation method of Schottky diode | |
| US11515395B2 (en) | Gallium nitride power device and manufacturing method thereof | |
| CN114400259B (en) | Junction barrier Schottky diode | |
| CN109346529A (en) | A kind of GaN base Schottky barrier diode with composite potential barrier layer | |
| CN115881827B (en) | Nickel oxide/gallium oxide heterojunction diode based on whole wafer and preparation method | |
| WO2023120443A1 (en) | Junction barrier schottky diode and method for manufacturing same | |
| US20230163221A1 (en) | Schottky barrier diode and method for manufacturing same | |
| CN116153780A (en) | Preparation method and device of Schottky diode | |
| CN116344625A (en) | Gallium oxide rectifier and manufacturing process thereof, gallium oxide rectifier structure and manufacturing process thereof | |
| CN114864656A (en) | Gallium nitride schottky diode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |