CN113013242A - P-channel GaN-based heterojunction field effect transistor based on n-GaN gate - Google Patents

P-channel GaN-based heterojunction field effect transistor based on n-GaN gate Download PDF

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CN113013242A
CN113013242A CN202110129625.8A CN202110129625A CN113013242A CN 113013242 A CN113013242 A CN 113013242A CN 202110129625 A CN202110129625 A CN 202110129625A CN 113013242 A CN113013242 A CN 113013242A
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gate
layer
electrode
effect transistor
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张苇杭
刘茜
张进成
张金风
付李煜
赵胜雷
黄韧
郝跃
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

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Abstract

The invention discloses a p-channel GaN-based heterojunction field effect transistor based on an n-GaN gate, which comprises the following components from bottom to top: the semiconductor device comprises a substrate, a buffer layer, a barrier layer and a p-GaN layer; wherein, both sides of the upper surface of the p-GaN layer are provided with a source electrode and a drain electrode, and a gate groove is carved in the middle of the upper surface of the p-GaN layer; the gate groove is filled with n-GaN material; the n-GaN material is higher than the gate groove, and the higher parts extend towards the directions of the source electrode and the drain electrode respectively and are not contacted with the source electrode and the drain electrode; a gate electrode is arranged on the upper surface of the n-GaN material; the upper surfaces of the p-GaN layer, the n-GaN material, the source electrode, the drain electrode and the gate electrode are covered with a passivation layer; the field effect transistor further includes: and an interconnection metal connected to the source electrode, the drain electrode and the gate electrode, respectively, through the passivation layer. The invention can regulate and control the threshold voltage of the device and improve the power loss and leakage current of the p-channel enhanced GaN device.

Description

P-channel GaN-based heterojunction field effect transistor based on n-GaN gate
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a p-channel GaN-based heterojunction field effect transistor based on an n-GaN gate and a preparation method thereof.
Background
The wide-bandgap semiconductor material gallium nitride (GaN) is a typical representative of the third-generation semiconductor, and has the advantages of high electron mobility, high thermal conductivity, high breakdown electric field, strong radiation resistance and the like. The power device based on the GaN heterojunction structure can obtain higher switching speed, higher blocking voltage, lower conduction loss and higher working temperature, thereby being capable of working under severe conditions of high power, high frequency, high temperature, irradiation and the like.
Compared with a power electronic system formed by GaN discrete devices, the monolithic integration technology has the advantage of cost, can inhibit the problems of parasitic capacitance and parasitic conductance, and is favorable for improving the working frequency, efficiency and reliability of the system. The complementary logic circuit realized by the GaN device is used for gate driving, so that the performance advantage of the GaN-based power device can be exerted to the maximum extent, and a power conversion system can be realized through monolithic integration; modules such as an enhancement type/depletion type device, a p-channel/n-channel device, a capacitor, a resistor and the like are realized on a single chip, so that the cost of the system can be greatly reduced, and the conversion frequency, the frequency and the reliability of the system can be improved. Therefore, in order to realize GaN-based complementary logic circuit integration applications, a p-channel enhancement type GaN device is indispensable.
The existing p-channel enhanced GaN device generally has the problems of high on-resistance, large off-state leakage, high sub-threshold slope, low threshold voltage and the like, which means that the existing p-channel enhanced GaN device has higher power consumption in on-state, off-state and switch conversion, thereby limiting the integrated application of the GaN-based complementary logic circuit.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a p-channel GaN-based heterojunction field effect transistor based on an n-GaN gate and a preparation method thereof.
The technical problem to be solved by the invention is realized by the following technical scheme:
in a first aspect, the present invention provides an n-GaN gate based p-channel GaN-based heterojunction field effect transistor, comprising from bottom to top: the semiconductor device comprises a substrate, a buffer layer, a barrier layer and a p-GaN layer; wherein,
a source electrode and a drain electrode are arranged on two sides of the upper surface of the p-GaN layer, and a gate groove is carved in the middle of the upper surface of the p-GaN layer; the gate groove is filled with n-GaN material; the n-GaN material is higher than the gate groove, and the higher parts of the n-GaN material extend towards the directions of the source electrode and the drain electrode respectively and are not contacted with the source electrode and the drain electrode;
a gate electrode is arranged on the upper surface of the n-GaN material;
the upper surfaces of the p-GaN layer, the n-GaN material, the source electrode, the drain electrode and the gate electrode are covered with passivation layers;
the n-GaN gate based p-channel GaN-based heterojunction field effect transistor further comprises: and an interconnection metal connected to the source electrode, the drain electrode and the gate electrode through the passivation layer, respectively.
Preferably, the buffer layer is made of GaN, and the barrier layer is made of AlGaN.
Preferably, the thickness of the GaN layer is 1-5 μm, the thickness of the AlGaN layer is 10-30 nm, the thickness of the part of the p-GaN layer where the gate groove is not etched is 50-100 nm, and the depth of the gate groove is 40-90 nm.
Preferably, the width of the gate trench accounts for 20% -50% of the distance between the source electrode and the drain electrode;
the thickness of the n-GaN material is 20 nm-100 nm.
Preferably, the doping concentration of the n-GaN material is 1-5 multiplied by 1019cm-3。
Preferably, the source electrode, the drain electrode and the gate electrode are all a double-layer metal stack structure composed of nickel and gold from bottom to top.
Preferably, the gate electrode is a four-layer metal stack structure consisting of titanium, aluminum, nickel and gold from bottom to top;
the source electrode and the drain electrode are both of a double-layer metal stack structure consisting of nickel and gold from bottom to top.
In a second aspect, the invention provides a method for preparing a p-channel GaN-based heterojunction field effect transistor based on an n-GaN gate, which comprises the following steps:
step A: sequentially epitaxially growing a buffer layer, a barrier layer and a p-GaN layer on a substrate;
and B: etching the middle of the upper surface of the p-GaN layer to form a gate groove;
and C: growing an n-GaN layer on the upper surface of the p-GaN layer so that the gate groove is filled with n-GaN materials and is higher than the gate groove;
step D: etching the n-GaN layer, and only reserving n-GaN materials in a preset gate region; the gate region is positioned right above the gate groove and is wider than the gate groove;
step E: manufacturing a source electrode and a drain electrode on two sides of the upper surface of the p-GaN layer;
step F: manufacturing a gate electrode on the upper surface of the n-GaN material;
step G: depositing a passivation layer on the upper surfaces of the p-GaN layer, the n-GaN material, the source electrode, the drain electrode and the gate electrode;
step H: etching off the source electrode, the drain electrode and part of the passivation layer above the gate electrode according to a preset electrode opening region to form an electrode opening;
step I: evaporating metal into the electrode openings to form interconnect metal through the passivation layer in contact with the source electrode, the drain electrode, and the gate electrode, respectively.
Preferably, step a comprises:
a metal organic chemical vapor deposition process is adopted, and a GaN buffer layer, an AlGaN barrier layer and a p-GaN layer are epitaxially grown on a substrate in sequence.
10 preferably, the method further comprises:
and D, manufacturing a mesa of the n-GaN gate-based p-channel GaN-based heterojunction field effect transistor between the step D and the step E, and etching to form device isolation.
In the p-channel GaN-based heterojunction field effect transistor based on the n-GaN gate, a special structure formed by n-GaN materials is additionally arranged between a gate electrode and a p-GaN layer by arranging a gate groove on the p-GaN layer; the doping concentration of the n-GaN in the structure is adjusted, so that holes in the p-GaN layer can be depleted, and an enhancement device is formed, and has the advantages that normally-off operation is realized at 0V, and power loss is reduced; and, the threshold voltage of the device can also be controlled by the doping concentration or growth thickness of n-GaN. Therefore, the invention can improve the power loss and the leakage current of the p-channel enhancement type GaN device, thereby tamping the foundation for the integration application of the GaN-based complementary logic circuit. That is to say, the p-channel GaN-based heterojunction field effect transistor based on the n-GaN gate and the n-channel GaN-based electronic device provided by the invention are integrated in a single chip, and the integrated application of the GaN-based complementary logic circuit can be realized.
In addition, the passivation layer is covered on the surface of the device to improve the interface state and further reduce the grid leakage.
The present invention will be described in further detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic structural diagram of a p-channel GaN-based heterojunction field effect transistor based on an n-GaN gate according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a prior art p-channel enhancement mode GaN device;
FIG. 3 illustrates the effect of an n-GaN gate based p-channel GaN-based heterojunction field effect transistor on the heterojunction band diagram provided by an embodiment of the invention;
FIG. 4 is a flow chart of a method for fabricating a p-channel GaN-based heterojunction field effect transistor based on an n-GaN gate according to an embodiment of the present invention;
fig. 5(a) to 5(j) are flowcharts graphically showing a method of manufacturing a field effect transistor in the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
In order to regulate and control the threshold voltage of a device, improve the power loss and leakage current of a p-channel enhanced GaN device and tamp the foundation for the integrated application of a GaN-based complementary logic circuit, the embodiment of the invention provides a p-channel GaN-based heterojunction field effect transistor based on an n-GaN gate and a preparation method thereof.
First, a p-channel GaN-based heterojunction field effect transistor based on an n-GaN gate provided in an embodiment of the present invention will be described in detail. Referring to fig. 1, the p-channel enhancement mode field effect transistor includes, from bottom to top: a substrate 1, a buffer layer 2, a barrier layer 3, and a p-GaN layer 4. n-GaN is n-type GaN, and p-GaN is n-type GaN.
Wherein, both sides of the upper surface of the p-GaN layer 4 are provided with an active electrode 5 and a drain electrode 6, and the middle of the upper surface of the p-GaN layer 4 is carved with a gate groove; the gate trench is filled with n-GaN material 7; the n-GaN material 7 is higher than the gate groove, and the higher parts extend towards the directions of the source electrode 5 and the drain electrode 6 respectively and are not contacted with the source electrode 5 and the drain electrode 6; the upper surface of the n-GaN material 7 is provided with a gate electrode 8; the upper surfaces of the p-GaN layer 4, the n-GaN material 7, the source electrode 5, the drain electrode 6 and the gate electrode 8 are covered with passivation layers; and, the p-channel enhancement mode field effect transistor further includes: and an interconnection metal 10 connected to the source electrode 5, the drain electrode 6, and the gate electrode 8, respectively, through the passivation layer.
As can be seen from a comparison of the structure of the prior p-channel enhancement GaN device shown in figure 2,
in the p-channel GaN-based heterojunction field effect transistor based on the n-GaN gate, a special structure formed by n-GaN materials is additionally arranged between a gate electrode and a p-GaN layer by arranging a gate groove on the p-GaN layer; the doping concentration of the n-GaN in the structure is adjusted, so that holes in the p-GaN layer can be depleted, and an enhancement device is formed, and has the advantages that normally-off operation is realized at 0V, and power loss is reduced; and, the threshold voltage of the device can also be controlled by the doping concentration or growth thickness of n-GaN. Therefore, the invention can improve the power loss and the leakage current of the p-channel enhancement type GaN device, thereby tamping the foundation for the integration application of the GaN-based complementary logic circuit. That is to say, the p-channel GaN-based heterojunction field effect transistor based on the n-GaN gate and the n-channel GaN-based electronic device provided by the invention are integrated in a single chip, and the integrated application of the GaN-based complementary logic circuit can be realized.
In addition, the passivation layer is covered on the surface of the device to improve the interface state and further reduce the grid leakage.
Preferably, the buffer layer 2 is made of GaN, and the barrier layer 3 is made of AlGaN. Wherein, the thickness of GaN is preferably 1-5 μm, and the thickness of AlGaN is preferably 10-30 nm; the thickness of the part of the p-GaN layer where the grid groove is not etched is 50 nm-100 nm, and the depth of the grid groove is 40 nm-90 nm.
Preferably, the width of the gate groove occupies 20% to 50% of the interval between the source electrode 5 and the drain electrode 6.
On the premise that the depth of the gate trench is smaller than the thickness of the p-GaN layer, the maximum thickness of the n-GaN material is preferably 20nm to 100 nm. That is, the thickness of the n-GaN material from the bottom of the gate trench to above the top of the gate trench is preferably 20nm to 100 nm.
Preferably, the doping concentration of the n-GaN material is 1-5 multiplied by 1019cm-3Thus, the p-channel enhancement type field effect transistor has the advantages of low on resistance, small off-state leakage, small sub-threshold slope and relatively high threshold voltage, and the power consumption in the on-state, the off-state and the switching conversion is lower than that of the conventional p-channel enhancement type GaN device.
In one embodiment, the source electrode 5, the drain electrode 6 and the gate electrode 8 are all a double-layer metal stack structure composed of nickel and gold from bottom to top. Thus, the source electrode 5 and the drain electrode 6 each form an ohmic contact with the p-GaN layer 4 thereunder, and the gate electrode 8 forms a schottky contact with the n-GaN layer 4 thereunder. Here, the ohmic contact refers to a region having a linear and symmetrical current-voltage characteristic curve in the device, and if the current-voltage characteristic curve is not linear, the contact is a schottky contact.
In another embodiment, the source electrode 5 and the drain electrode 6 are both a double-layered metal stack structure composed of nickel and gold from bottom to top, and the gate electrode 8 is a four-layered metal stack structure composed of titanium, aluminum, nickel, and gold from bottom to top. Thus, the source electrode 5 and the drain electrode 6 each form an ohmic contact with the p-GaN layer 4 thereunder, and the gate electrode 8 also forms an ohmic contact with the n-GaN layer 4 thereunder.
Preferably, the thickness of each of the source electrode 5 and the drain electrode 6 is preferably 200nm to 300 nm; the thickness of the gate electrode 8 is preferably 200nm to 350 nm.
Preferably, the passivation layer 9 is made of Al2O3And is not limited thereto. The thickness of the passivation layer 9 is preferably 20 nm.
Preferably, the substrate 1 may be a silicon substrate or an soi (silicon On insulator) substrate.
FIG. 3 illustrates the effect of an n-GaN gate based p-channel GaN-based heterojunction field effect transistor on the heterojunction band diagram provided by an embodiment of the invention; wherein, the dotted line is an energy band under the influence of two-dimensional hole gas and two-dimensional electron gas generated by the heterojunction due to polarization effect, and the solid line is the change of energy band caused by depletion of the two-dimensional hole gas after n-GaN is grown.
Corresponding to the p-channel GaN-based heterojunction field effect transistor based on the n-GaN gate, the embodiment of the invention also provides a preparation method of the p-channel enhancement type field effect transistor. For convenience, the p-channel enhancement type field effect transistor which is not prepared can be subsequently called a sample; referring to fig. 4, the method comprises the steps of:
step A: and sequentially epitaxially growing a buffer layer, a barrier layer and a p-GaN layer on the substrate.
The buffer layer is preferably made of GaN, and the barrier layer 3 is preferably made of AlGaN. The step can be specifically realized by adopting a metal organic chemical vapor deposition process and epitaxially growing a GaN buffer layer, an AlGaN barrier layer and a p-GaN layer on the substrate in sequence. The substrate may be a silicon substrate or an soi (silicon On insulator) substrate.
The sample after this step is completed can be seen in fig. 5 (a).
And B: and etching the middle of the upper surface of the p-GaN layer to form a gate groove.
Specifically, a gate groove can be etched in the middle of the upper surface of the p-GaN layer by adopting a photoetching process and an inductive coupling plasma etching process; it will be appreciated that the depth of the gate trench is less than the thickness of the p-GaN layer, i.e., this step does not etch through the p-GaN layer.
The sample after this step is completed can be seen in fig. 5 (b).
And C: and growing an n-GaN layer on the upper surface of the p-GaN layer, so that the gate groove is filled with the n-GaN material and is higher than the gate groove.
Specifically, an n-GaN layer is grown on the upper surface of the current p-GaN layer by using a metal organic chemical vapor deposition process, and the grown thickness is based on the fact that the thickness of the n-GaN layer can be higher than that of the gate groove. That is, the maximum thickness of the n-GaN material is higher than the depth of the gate trench. Illustratively, when the p-GaN layer has a thickness of 50nm to 100nm, the n-GaN layer grown in this step may have a thickness of 20nm to 100 nm.
It is understood that electrons in the n-GaN material may deplete the two-dimensional hole gas (2 DHG) in the underlying heterojunction, thereby forming an enhancement mode device. It should be noted that the doping concentration and the growth thickness of the n-GaN material grown in the step can be adjusted, so that the effects of adjusting the threshold voltage of the device and improving the power loss and the leakage current of the device are achieved; for example, the doping concentration of the n-GaN material can be 1-5 multiplied by 1019cm-3。
Step D: etching the n-GaN layer, and only reserving the n-GaN material in the preset gate region; the grid region is positioned right above the grid groove and is wider than the grid groove.
It will be appreciated that the gate region is of equal length to the gate trench length.
In the step, the n-GaN material of the n-GaN layer outside the gate region can be etched by adopting a photoetching process and an inductive coupling plasma etching process, so that only the n-GaN material in the gate region is reserved.
The sample obtained after the step D is completed can be seen in fig. 5 (D).
In addition, in an alternative embodiment, after the step D is completed, a mesa etching of the p-channel enhancement type field effect transistor may be further performed to form a device isolation. Specifically, the outer edges of the p-GaN layer, the barrier layer, and the buffer layer are sequentially etched to make the upper ends of the p-GaN layer, the barrier layer, and the buffer layer recede toward the center of the device, thereby forming the device isolation as shown in fig. 5 (e).
Step E: manufacturing a source electrode and a drain electrode on two sides of the upper surface of the p-GaN layer; and the manufactured source electrode and the manufactured drain electrode are not in contact with the reserved n-GaN material.
Specifically, the step E may include a plurality of sub-steps as follows:
step E-1: photoetching a source electrode pattern and a drain electrode pattern on two sides of the upper surface of the p-GaN layer;
step E-2: cleaning the sample with a BOE (Buffered Oxide Etch) solution for 1 minute to remove the Oxide in the source electrode pattern and the drain electrode pattern;
step E-3: sequentially depositing a plurality of metals into the source electrode pattern and the drain electrode pattern by adopting an electron beam evaporation process to form a source electrode and a drain electrode;
step E-4: and annealing for 10 minutes in an oxygen atmosphere at the temperature of 550 ℃ to enable the source electrode and the drain electrode to form ohmic contact with the p-GaN layer below.
Wherein, the metals deposited in the step E-3 can be nickel and gold from bottom to top, wherein the thickness of the nickel is preferably 20-50nm, and the thickness of the gold is preferably 200-250 nm.
The sample obtained after the step E is completed can be seen in fig. 5 (f).
Step F: and manufacturing a gate electrode on the upper surface of the n-GaN material.
Specifically, the step E may include a plurality of sub-steps as follows:
step F-1: photoetching gate electrode patterns on two sides of the upper surface of the p-GaN layer;
step F-2: cleaning the sample with BOE solution for 1 minute to remove the oxide in the gate electrode pattern;
step F-3: sequentially depositing a plurality of gate metals into the gate electrode pattern by adopting an electron beam evaporation process to form a gate electrode;
step F-4: and carrying out annealing treatment on the sample to obtain the manufactured gate electrode.
When the gate metals deposited in the step F-3 comprise nickel and gold from bottom to top, the thickness of the nickel is preferably 20nm to 50nm, and the thickness of the gold is preferably 200nm to 250 nm; accordingly, the annealing process in step F-4 may be specifically annealing at 400 ℃ for 5 minutes in a nitrogen atmosphere, thereby forming schottky contact between the gate electrode and the underlying n-GaN material.
Or, when the plurality of gate metals deposited in step F-3 include titanium, aluminum, nickel and gold from bottom to top, the thickness of titanium is preferably 20nm, the thickness of aluminum is preferably 140nm, the thickness of nickel is preferably 45nm, and the thickness of gold is preferably 55 nm; accordingly, the annealing treatment in step F-4 may be specifically annealing at 550 to 750 ℃ for 30 to 60 seconds in a nitrogen atmosphere, so that the gate electrode forms ohmic contact with the underlying n-GaN material.
The sample obtained after the step F is completed can be seen in fig. 5 (g).
Step G: and depositing a passivation layer on the upper surfaces of the p-GaN layer, the n-GaN material, the source electrode, the drain electrode and the gate electrode.
Specifically, an atomic layer deposition process is adopted to deposit a passivation layer on the upper surface of the sample. Wherein the passivation layer may be made of Al2O3And is not limited thereto. Exemplarily, when the passivation layer is made of Al2O3When the thickness of the passivation layer is 20nm, it is preferable.
The sample obtained after the step G is completed can be seen in FIG. 5 (h).
Step H: and etching off parts of the passivation layer above the source electrode, the drain electrode and the gate electrode according to a preset electrode opening region to form an electrode opening.
Specifically, the step may employ a wet etching process to etch away the source electrode, the drain electrode, and a portion of the passivation layer above the gate electrode, thereby forming an electrode opening. Alternatively, a reactive ion etching process may be used to etch three electrode openings.
In another embodiment, this step may be modified to etch away all of the passivation layer on the upper surfaces of the source, drain and gate electrodes.
The sample obtained after the step H is completed can be seen in fig. 5 (i).
Step I: metal is evaporated into the electrode openings to form interconnect metal through the passivation layer in contact with the source, drain and gate electrodes, respectively.
Specifically, several metals are deposited in the electrode openings of the source electrode, the drain electrode and the gate electrode by an electron beam evaporation process, thereby forming interconnection metals which penetrate through the passivation layer and are respectively in contact with the source electrode, the drain electrode and the gate electrode. Wherein, the deposited metals preferably comprise nickel alloy from bottom to top, the thickness of the nickel is preferably 20nm to 50nm, and the thickness of the gold is preferably 200nm to 500 nm.
The sample obtained after the step I is completed can be seen in FIG. 5 (j).
In the description of the specification, reference to the description of the term "one embodiment", "some embodiments", "an example", "a specific example", or "some examples", etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. A p-channel GaN-based heterojunction field effect transistor based on an n-GaN gate is characterized by comprising the following components from bottom to top: the buffer layer structure comprises a substrate (1), a buffer layer (2), a barrier layer (3) and a p-GaN layer (4); wherein,
an active electrode (5) and a drain electrode (6) are arranged on two sides of the upper surface of the p-GaN layer (4), and a gate groove is carved in the middle of the upper surface of the p-GaN layer (4); the gate trench is filled with an n-GaN material (7); the n-GaN material (7) is higher than the gate groove, and the higher parts extend towards the directions of the source electrode (5) and the drain electrode (6) respectively and are not contacted with the source electrode (5) and the drain electrode (6);
a gate electrode (8) is arranged on the upper surface of the n-GaN material (7);
the upper surfaces of the p-GaN layer (4), the n-GaN material (7), the source electrode (5), the drain electrode (6) and the gate electrode (8) are covered with a passivation layer (9);
the n-GaN gate based p-channel GaN-based heterojunction field effect transistor further comprises: and an interconnection metal (10) which is connected to the source electrode (5), the drain electrode (6) and the gate electrode (8) through the passivation layer (9).
2. The n-GaN gate based p-channel GaN-based heterojunction field effect transistor according to claim 1, wherein the buffer layer (2) is made of GaN and the barrier layer (3) is made of AlGaN.
3. The n-GaN gate based p-channel GaN-based heterojunction field effect transistor according to claim 2, wherein the thickness of GaN is 1 μm to 5 μm, the thickness of AlGaN is 10nm to 30nm, the thickness of the p-GaN layer at the portion where the gate trench is not etched is 50nm to 100nm, and the depth of the gate trench is 40nm to 90 nm.
4. The n-GaN gate based p-channel GaN-based heterojunction field effect transistor according to claim 1, wherein the width of the gate trench accounts for 20% to 50% of the spacing between the source electrode (5) and the drain electrode (6);
the thickness of the n-GaN material is 20 nm-100 nm.
5. The n-GaN gate-based p-channel GaN-based heterojunction field effect transistor according to claim 2, wherein the doping concentration of the n-GaN material is 1-5 x 1019cm-3。
6. The n-GaN gate based p-channel GaN-based heterojunction field effect transistor according to claim 1, wherein the source electrode (5), the drain electrode (6) and the gate electrode (8) are all double-layer metal stack structures composed of nickel and gold from bottom to top.
7. The n-GaN gate based p-channel GaN-based heterojunction field effect transistor according to claim 1,
the gate electrode (8) is a four-layer metal stack structure composed of titanium, aluminum, nickel and gold from bottom to top;
the source electrode (5) and the drain electrode (6) are both of a double-layer metal stack structure composed of nickel and gold from bottom to top.
8. A preparation method of a p-channel GaN-based heterojunction field effect transistor based on an n-GaN gate is characterized by comprising the following steps:
step A: sequentially epitaxially growing a buffer layer, a barrier layer and a p-GaN layer on a substrate;
and B: etching the middle of the upper surface of the p-GaN layer to form a gate groove;
and C: growing an n-GaN layer on the upper surface of the p-GaN layer so that the gate groove is filled with n-GaN materials and is higher than the gate groove;
step D: etching the n-GaN layer, and only reserving n-GaN materials in a preset gate region; the gate region is positioned right above the gate groove and is wider than the gate groove;
step E: manufacturing a source electrode and a drain electrode on two sides of the upper surface of the p-GaN layer;
step F: manufacturing a gate electrode on the upper surface of the n-GaN material;
step G: depositing a passivation layer on the upper surfaces of the p-GaN layer, the n-GaN material, the source electrode, the drain electrode and the gate electrode;
step H: etching off the source electrode, the drain electrode and part of the passivation layer above the gate electrode according to a preset electrode opening region to form an electrode opening;
step I: evaporating metal into the electrode openings to form interconnect metal through the passivation layer in contact with the source electrode, the drain electrode, and the gate electrode, respectively.
9. The method for preparing the n-GaN gate based p-channel GaN-based heterojunction field effect transistor according to claim 8, wherein the step A comprises:
a metal organic chemical vapor deposition process is adopted, and a GaN buffer layer, an AlGaN barrier layer and a p-GaN layer are epitaxially grown on a substrate in sequence.
10. The method of claim 6, wherein the method further comprises:
and D, etching the mesa for manufacturing the p-channel enhancement type field effect transistor between the step D and the step E to form device isolation.
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