CN102376777A - Junction barrier schottky having low forward voltage drop - Google Patents
Junction barrier schottky having low forward voltage drop Download PDFInfo
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- CN102376777A CN102376777A CN2010102631630A CN201010263163A CN102376777A CN 102376777 A CN102376777 A CN 102376777A CN 2010102631630 A CN2010102631630 A CN 2010102631630A CN 201010263163 A CN201010263163 A CN 201010263163A CN 102376777 A CN102376777 A CN 102376777A
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- 230000004888 barrier function Effects 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 167
- 239000012535 impurity Substances 0.000 claims description 39
- 230000005764 inhibitory process Effects 0.000 claims description 26
- 239000011248 coating agent Substances 0.000 claims description 22
- 238000000576 coating method Methods 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 16
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 230000000452 restraining effect Effects 0.000 abstract 2
- 230000003139 buffering effect Effects 0.000 abstract 1
- 238000005036 potential barrier Methods 0.000 description 33
- 230000001413 cellular effect Effects 0.000 description 23
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 12
- 229910052698 phosphorus Inorganic materials 0.000 description 12
- 239000011574 phosphorus Substances 0.000 description 12
- 125000004429 atom Chemical group 0.000 description 9
- 238000000034 method Methods 0.000 description 3
- 125000004437 phosphorous atom Chemical group 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a novel junction barrier schottky device which comprises a substrate layer, a buffering layer, a drifting layer, a light doping layer, a plurality of restraining areas, a heavy doping layer and a schottky barrier layer, wherein the restraining areas which are separated from each other are located in the light doping layer and the heavy doping layer. When a reverse bias is applied to a semiconductor device, a large-area exhausting region is spread and formed in a semiconductor material of the light doping layer. The invention also provides a manufacturing method for the semiconductor device. The semiconductor device provided by the invention has a low forward voltage drop and a high device-switching speed. Electrical parameter characteristics of the semiconductor device are further optimized.
Description
Technical field
The present invention is mainly concerned with the structure and the manufacture craft of junction barrier schottky device, relates in particular to a kind of structure and manufacture craft of the novel junction barrier schottky device with low forward voltage drop.
Background technology
Three kinds of rectifiers are arranged usually; (1) Schottky barrier diode; Be the device that a kind of metal contacts with semiconductor, have lower forward voltage drop and high switching speed, but reverse leakage current big with the not high unfavorable properties influence of reverse voltage the interior application of device certain limit.
(2) P-i-N diode provides lower leakage current and higher reverse voltage, but in switching process, thereby the stored charge that on PN junction, stores some influences the switching speed of device.
(3) junction barrier type Schottky diode; Be a kind of PN junction modulation to be integrated into the Schottky junction structure of drift region, key character is, when reversed bias voltage surpasses certain value; Depletion layer under the Schottky overlaps; If continuing increases voltage, then add pressure drop and all fall on depletion layer, thereby eliminate that traditional schottky exists because the electric leakage that the reverse voltage increase causes increases the generation of phenomenon.In the extensive use switching power circuit.But the electrical quantity of above-mentioned device, forward voltage drop and reverse leakage current need a compromise to choose, because must cause the reduction of reverse pressure drop when reducing forward voltage drop, also must cause the increase of forward voltage drop when improving reverse pressure drop.That is to say, on on-state performance and closed condition performance, can not accomplish to take into account comprehensively.
Summary of the invention
The present invention provides a kind of novel have low forward voltage drop and the simple junction barrier type of technology schottky device.
A kind of semiconductor device comprises:
(a) substrate layer is N conduction type semi-conducting material, is used to reduce the conducting resistance of semiconductor device;
(b) resilient coating is positioned on the substrate layer, is the semi-conducting material of N conduction type, is used to reduce the conducting resistance of semiconductor device and the size of control semiconductor device reverse voltage;
(c) drift layer is positioned on the resilient coating, is the semi-conducting material of N conduction type, is used to control the size of semiconductor device reverse voltage;
(d) lightly-doped layer is positioned on the drift layer, is the semi-conducting material of N conduction type, is used for when device adds reverse bias and falls, and in this layer, forms the large tracts of land depleted region;
(e) heavily doped layer is positioned on the lightly-doped layer, is the semi-conducting material of N conduction type, is used to reduce the forward voltage drop of semiconductor device;
(f) inhibition zone; Semi-conducting material for the P conduction type; Several inhibition zones that are separated from each other are arranged in lightly-doped layer and heavily doped layer, are used for when described semiconductor device adds reverse biased, and expansion forms the large tracts of land depleted region in the lightly-doped layer semi-conducting material;
(g) schottky barrier layer is positioned on the heavily doped layer, forms the Schottky barrier junction characteristic;
Be provided with Schottky barrier edge P type diffusing protection ring in the light depletion layer of below, described schottky barrier layer edge and the heavily doped layer.
The surface at described semiconductor device edge is provided with the silicon face protective layer that shields.
Described schottky barrier layer is that the N type semiconductor material alloys by film barrier metal and heavily doped layer top forms.
The diffusion impurity of described resilient coating and the diffusion impurity of substrate layer can be inequality, the diffusion impurity of the diffusion impurity of described drift layer and substrate layer can be inequality, the diffusion impurity of the diffusion impurity of described lightly-doped layer and substrate layer can be inequality, the diffusion impurity of the diffusion impurity of described heavily doped layer and substrate layer can be inequality.
The doping impurity concentration of described substrate layer is more than or equal to 1 * 10
18/ cm
3
The doping impurity concentration of described resilient coating, drift layer, lightly-doped layer and heavily doped layer is 1 * 10
14-1 * 10
18/ cm
3
The doping impurity concentration of described resilient coating is greater than the heavily doped impurity layer doping content.
The doping impurity concentration of described heavily doped layer is greater than drift layer doping impurity concentration.
The doping impurity concentration of described drift layer is greater than lightly-doped layer doping impurity concentration.
The present invention also provides a kind of junction barrier type schottky device manufacture method that has low forward voltage drop and simpler production technology simultaneously.
A kind of method of making semiconductor device is characterized in that: comprise the steps:
1) on substrate layer, forms resilient coating, drift layer, lightly-doped layer and heavily doped layer through the epitaxial growth mode;
2) carry out high annealing again through in the heavily doped layer semi-conducting material, injecting the boron ion; In lightly-doped layer and heavily doped layer, form a plurality of p type island regions that are separated from each other as the inhibition zone; In the lightly-doped layer in precalculated position and heavily doped layer, form Schottky barrier edge P type diffusing protection ring, form the silicon face protective layer on the surface at semiconductor device edge simultaneously;
3) deposit one deck barrier metal on heavily doped layer forms schottky barrier layer through low-temperature alloy in N type district, heavily doped layer surface, forms ohmic contact regions on the surface, inhibition zone.
Semiconductor device of the present invention is compared with conventional junction potential barrier type schottky device, having under the identical reverse breakdown voltage condition, has low forward voltage drop, has high devices switch speed simultaneously, and the electrical quantity characteristic of device is further optimized.
Description of drawings
Fig. 1 is the generalized section of one embodiment of the present invention;
Fig. 2 is the generalized section of the single cellular of semiconductor device of the present invention;
Fig. 3 is the generalized section of the single cellular of conventional junction potential barrier type Schottky;
Fig. 4 is single cellular of semiconductor device of the present invention and voltage and the current density curve of the single cellular of conventional junction potential barrier type Schottky when forward bias;
Fig. 5 is single cellular of semiconductor device of the present invention and voltage and the current density curve of the single cellular of conventional junction potential barrier type Schottky when reverse biased.
1, substrate layer;
2, resilient coating;
3, drift layer;
4, lightly-doped layer;
5, heavily doped layer;
6, inhibition zone;
7, schottky barrier layer;
8, ohmic contact regions;
9 Schottky barrier edge P type diffusing protection rings;
10, silicon face protective layer;
11, conventional junction potential barrier type Schottky substrate layer;
12, conventional junction potential barrier type Schottky drift layer;
13, conventional junction potential barrier type Schottky inhibition zone;
14, conventional junction potential barrier type Schottky ohmic contact regions;
15, conventional junction potential barrier type schottky barrier layer;
16, voltage and the current density curve of the single cellular of semiconductor device of the present invention when forward bias;
17, voltage and the current density curve of the single cellular of conventional junction potential barrier type Schottky when forward bias;
18, voltage and the current density curve of the single cellular of semiconductor device of the present invention when reverse biased;
19, voltage and the current density curve of the single cellular of conventional junction potential barrier type Schottky when reverse biased.
Embodiment
Fig. 1 shows the generalized section of one embodiment of the present invention, specifies semiconductor device of the present invention below in conjunction with Fig. 1.
A kind of semiconductor device comprises: substrate layer 1, for N conduction type semi-conducting material, draw negative electrode through metal at the substrate layer lower surface; Resilient coating 2 is positioned on the substrate layer 1, is the semi-conducting material of N conduction type; Drift layer 3 is positioned on the resilient coating 2, is the semi-conducting material of N conduction type; Lightly-doped layer 4 is positioned on the drift layer 3, and lightly-doped layer is the semi-conducting material of N conduction type; Heavily doped layer 5 is positioned on the lightly-doped layer 4, is the semi-conducting material of N conduction type; Inhibition zone 6, for a plurality of p type island regions are formed in lightly-doped layer and the heavily doped layer with being separated from each other, each inhibition zone 6 is the semi-conducting material of P conduction type, and width is 2～6um, and the each interval distance is 2～10um; Heavily doped layer top N type semiconductor material and metal Ni low-temperature alloy form schottky barrier layer 7, and inhibition zone 6 forms ohmic contact regions 8 with metal Ni low-temperature alloy; On schottky barrier layer 7 and ohmic contact regions 8, cover the anode that one deck conducting metal Al draws device; Schottky barrier edge P type diffusing protection ring 9 is positioned at schottky barrier layer 7 edges and is used to safeguard the device reversed bias voltage; Silicon face protective layer 10 is positioned at the surface of semiconductor device edge, is semiconductor passivation layers such as conductor oxidate or nitride.
On substrate layer 1, form resilient coating 2, drift layer 3, lightly-doped layer 4 and heavily doped layer 5 through the epitaxial growth mode, phosphorus impurities concentration for example is set at 3 * 10 in the resilient coating 2
16Atom/CM
3, phosphorus impurities concentration for example is set at 1 * 10 in the drift layer 3
15Atom/CM
3, phosphorus impurities concentration for example is set at 5 * 10 in the lightly-doped layer 4
14Atom/CM
3, phosphorus impurities concentration for example is set at 5 * 10 in the heavily doped layer 5
15Atom/CM
3, for example be set at 1 * 10 for the concentration of mixing phosphorus atoms in the substrate layer 1
19Atom/CM
3, resilient coating 2, drift layer 3, lightly-doped layer 4 and heavily doped layer 5 can form in an epitaxial growth, realize through in the extension deposition process, regulating the concentration of mixing phosphorus impurities.Carry out high annealing again through injecting the boron ion after the photoetching process; In the semi-conducting material of lightly-doped layer 4 and heavily doped layer 5, introduce a plurality of p type island regions that are separated from each other, meanwhile also introduced Schottky barrier edge P type diffusing protection ring 9 and silicon face protective layer 10 as inhibition zone 6.
Then on this basis, deposit one deck barrier metal Ni on device surface forms schottky barrier layer 7 through low-temperature alloy on heavily doped layer 5 surfaces, and inhibition zone 6 forms ohmic contact regions 8 with metal Ni low-temperature alloy simultaneously.
As stated; When device adds forward bias; Resilient coating 2 has high impurity concentration with heavily doped layer 5, thereby the conducting resistance of the device that has reduced reduces the forward voltage drop of device, and wherein heavily doped layer 5 has also reduced schottky barrier layer 7 barrier heights because of having chosen high phosphorus atoms doping content; As long as and the doping content of choosing phosphorus atoms is reasonable, can not cause the obvious increase of the reverse leakage current of device; When device adds reversed bias voltage; Because of lightly-doped layer 4 has low impurity concentration; Therefore so the depleted region that inhibition zone 6 forms spreads overlapping fast, obtained the pinch-off voltage at the end, because device has obtained low pinch-off voltage when adding reversed bias voltage in lightly-doped layer 4; Can suitably increase the spacing of inhibition zone separated from one another 6; Schottky area area occupied ratio in the device can be increased like this,, the forward voltage drop and the switching speed that improves device of device can be reduced through improving shared this example of integral device area of schottky area; Because of low doping content is arranged in the lightly-doped layer 4, improve the reverse pressure drop of device simultaneously, recovered the change of the reverse pressure drop increase of device through the spacing of suitable increase inhibition zone 6 separated from one another.On the other hand, because of the forward conduction resistance of lightly-doped layer 4 meetings increasing device,, choose the one-tenth-value thickness 1/10 of suitable compromise so want controlled doping layer 4 thickness.
In conjunction with the foregoing description, use ISE-TCAD device simulation software verification semiconductor device of the present invention to compare and have low forward voltage drop with traditional junction barrier type Schottky.Shown in Figure 2ly be the generalized section of the single cellular of semiconductor device of the present invention, shown in Figure 3 is the generalized section of the single cellular of conventional junction potential barrier type Schottky, specifies below in conjunction with Fig. 2 and Fig. 3.
Shown in Figure 2 is the single cellular generalized section of semiconductor device of the present invention, wherein: substrate layer 1, be N conduction type semi-conducting material, draw negative electrode at substrate layer 1 lower surface through metal, the doping content of phosphorus is 1E19 atom/CM in the substrate layer 1
3, the thickness degree is set at 10um; Resilient coating 2 is positioned on the substrate layer 1, is the semi-conducting material of N conduction type, and the doping content of resilient coating 2 phosphorus is 3E16 atom/CM
3, thickness is 4um; Drift layer 3 is positioned on the resilient coating 2, is the semi-conducting material of N conduction type, and the doping content of phosphorus is 1E15 atom/CM in the drift layer 3
3, thickness is 12um; Lightly-doped layer 4 is positioned on the drift layer 3, and lightly-doped layer is the semi-conducting material of N conduction type, and the doping content of phosphorus is 5E14 atom/CM in the lightly-doped layer 4
3, thickness is 2um; Heavily doped layer 5 is positioned on the lightly-doped layer 4, is the semi-conducting material of N conduction type, and the doping content of phosphorus is 5E15 atom/CM in the heavily doped layer 5
3, thickness is 2um; Inhibition zone 6 is that two half of p type island regions are formed in lightly-doped layer 4 and the heavily doped layer 5 with being separated from each other, and each inhibition zone 6 is the semi-conducting material of P conduction type, and wherein the implantation dosage of boron is 6E14 atom/CM
2, about the overall width of two half of inhibition zones be 5um, the each interval distance is 7um; Heavily doped layer 5 top semiconductor materials and work function form schottky barrier layer 7 for the 4.9eV metal, and inhibition zone 6 forms ohmic contact regions 8 with metal; On schottky barrier layer 7 and ohmic contact regions 8, cover the anode that one deck conducting metal Al draws device.
Shown in Figure 3 is the generalized section of the single cellular of conventional junction potential barrier type Schottky; Wherein: conventional junction potential barrier type Schottky substrate layer 11; Be N conduction type semi-conducting material; Draw negative electrode at conventional junction potential barrier type Schottky substrate layer 11 lower surfaces through metal, the doping content of phosphorus is 1E19 atom/CM in the conventional junction potential barrier type Schottky substrate layer 11
3, thickness setting is 10um; Conventional junction potential barrier type Schottky drift layer 12 is positioned on the conventional junction potential barrier type Schottky substrate layer 11, is the semi-conducting material of N conduction type, and the doping content of phosphorus is 1E15 atom/CM in the conventional junction potential barrier type Schottky drift layer 12
3, thickness is 20um; Conventional junction potential barrier type Schottky inhibition zone 13; Be that two half of p type island regions are formed in the conventional junction potential barrier type Schottky drift layer 12 with being separated from each other; Each conventional junction potential barrier type Schottky inhibition zone 13 is the semi-conducting material of P conduction type, and wherein the implantation dosage of boron is 6E14 atom/CM
2, about the overall width of two half of conventional junction potential barrier type Schottky inhibition zones 13 be 5um, the each interval distance is 5um; Conventional junction potential barrier type Schottky drift layer 12 top semiconductor materials and work function form conventional junction potential barrier type schottky barrier layer 15 for the 4.9eV metal, and conventional junction potential barrier type Schottky inhibition zone 13 forms conventional junction potential barrier type Schottky ohmic contact regions 14 with metal; On conventional junction potential barrier type schottky barrier layer 15 and conventional junction potential barrier type Schottky ohmic contact regions 14, cover the anode that one deck conducting metal Al draws device.
Use ISE-TCAD device simulation software that two cellulars among Fig. 2 and Fig. 3 are carried out the emulation of forward and reverse I-V characteristic curve, wherein Fig. 4 shows single cellular of semiconductor device of the present invention and voltage and the current density curve of the single cellular of conventional junction potential barrier type Schottky when forward bias; Wherein Fig. 5 shows single cellular of semiconductor device of the present invention and voltage and the current density curve of the single cellular of conventional junction potential barrier type Schottky when reverse biased.At voltage and the current density curve 18 of the single cellular of semiconductor device of the present invention during in reverse biased with the single cellular of conventional junction potential barrier type Schottky under the voltage and current density curve 19 close conditions during in reverse biased; Voltage during in forward bias and current density curve 17 have verified fully that to this semiconductor device of the present invention compares with traditional junction barrier type Schottky and have low forward voltage drop with the single cellular of conventional junction potential barrier type Schottky through voltage and the current density curve 16 of the single cellular of semiconductor device of the present invention when the forward bias.
Set forth the present invention through the foregoing description, also can adopt other embodiment to realize the present invention simultaneously.The present invention is not limited to above-mentioned specific embodiment, so the present invention is limited the accompanying claims scope.
Claims (11)
1. semiconductor device is characterized in that: comprising:
(a) substrate layer is N conduction type semi-conducting material;
(b) resilient coating is positioned on the substrate layer, is the semi-conducting material of N conduction type;
(c) drift layer is positioned on the resilient coating, is the semi-conducting material of N conduction type;
(d) lightly-doped layer is positioned on the drift layer, is the semi-conducting material of N conduction type;
(e) heavily doped layer is positioned on the lightly-doped layer, is the semi-conducting material of N conduction type;
(f) inhibition zone is the semi-conducting material of P conduction type, and several inhibition zones that are separated from each other are arranged in low doped layer and heavily doped layer;
(g) schottky barrier layer is positioned on the heavily doped layer, forms the Schottky barrier junction characteristic.
2. semiconductor device as claimed in claim 1 is characterized in that: be provided with Schottky barrier edge P type diffusing protection ring in the light depletion layer of below, described schottky barrier layer edge and the heavily doped layer.
3. semiconductor device as claimed in claim 1 is characterized in that: the surface at described semiconductor device edge is provided with the silicon face protective layer that shields.
4. semiconductor device as claimed in claim 1 is characterized in that: described schottky barrier layer is that the N type semiconductor material alloys by film barrier metal and heavily doped layer top forms.
5. semiconductor device as claimed in claim 1 is characterized in that: the diffusion impurity of described resilient coating and the diffusion impurity of substrate layer is inequality, the diffusion impurity of the diffusion impurity of described drift layer and substrate layer is inequality, the diffusion impurity of the diffusion impurity of described lightly-doped layer and substrate layer is inequality, the diffusion impurity of the diffusion impurity of described heavily doped layer and substrate layer is inequality.
6. semiconductor device as claimed in claim 1 is characterized in that: the doping impurity concentration of described substrate layer is more than or equal to 1 * 10
18/ cm
3
7. semiconductor device as claimed in claim 1 is characterized in that: the doping impurity concentration of described resilient coating, drift layer, lightly-doped layer and heavily doped layer is 1 * 10
14-1 * 10
18/ cm
3
8. semiconductor device as claimed in claim 1 is characterized in that: the doping impurity concentration of described resilient coating is greater than the heavily doped impurity layer doping content.
9. semiconductor device as claimed in claim 1 is characterized in that: the doping impurity concentration of described heavily doped layer is greater than drift layer doping impurity concentration.
10. semiconductor device as claimed in claim 1 is characterized in that: the doping impurity concentration of described drift layer is greater than lightly-doped layer doping impurity concentration.
11. a method of making semiconductor device is characterized in that: comprise the steps:
1) on substrate layer, forms resilient coating, drift layer, lightly-doped layer and heavily doped layer through the epitaxial growth mode;
2) carry out high annealing again through in the heavily doped layer semi-conducting material, injecting the boron ion; In lightly-doped layer and heavily doped layer, form a plurality of p type island regions that are separated from each other as the inhibition zone; In the lightly-doped layer in precalculated position and heavily doped layer, form Schottky barrier edge P type diffusing protection ring, form the silicon face protective layer on the surface at semiconductor device edge simultaneously;
3) deposit one deck barrier metal on heavily doped layer forms schottky barrier layer through low-temperature alloy in N type district, heavily doped layer surface, forms ohmic contact regions on the surface, inhibition zone.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105023953A (en) * | 2015-07-10 | 2015-11-04 | 淄博汉林半导体有限公司 | Vertical field effect diode and manufacture method thereof |
| CN105206681A (en) * | 2014-06-20 | 2015-12-30 | 意法半导体股份有限公司 | Wide Bandgap High-Density Semiconductor Switching Device And Manufacturing Process Thereof |
| WO2018068301A1 (en) * | 2016-10-14 | 2018-04-19 | 苏州晶湛半导体有限公司 | Diode and manufacturing method thereof |
| CN109860273A (en) * | 2018-12-29 | 2019-06-07 | 厦门芯光润泽科技有限公司 | MPS diode component and preparation method thereof |
| CN109888024A (en) * | 2018-12-29 | 2019-06-14 | 厦门芯光润泽科技有限公司 | MPS diode component and preparation method thereof |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08148699A (en) * | 1994-11-21 | 1996-06-07 | Shindengen Electric Mfg Co Ltd | Rectifier diode |
| CN1337747A (en) * | 2000-08-04 | 2002-02-27 | 北京普罗强生半导体有限公司 | New type of metal-semiconductor contact for producing schottky diode |
| US20040211974A1 (en) * | 2003-04-24 | 2004-10-28 | Chip Integration Tech. Co., Ltd. | Two mask shottky barrier diode with locos structure |
| CN101221989A (en) * | 2007-01-11 | 2008-07-16 | 株式会社东芝 | SiC schottky barrier semiconductor device |
| EP2154726A2 (en) * | 2008-08-14 | 2010-02-17 | Acreo AB | A method for producing a JBS diode |
| CN101656272A (en) * | 2009-07-22 | 2010-02-24 | 上海宏力半导体制造有限公司 | Schottky diode and fabricating method thereof |
| CN101740641A (en) * | 2009-12-24 | 2010-06-16 | 杭州立昂电子有限公司 | Semiconductor device |
-
2010
- 2010-08-24 CN CN2010102631630A patent/CN102376777A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08148699A (en) * | 1994-11-21 | 1996-06-07 | Shindengen Electric Mfg Co Ltd | Rectifier diode |
| CN1337747A (en) * | 2000-08-04 | 2002-02-27 | 北京普罗强生半导体有限公司 | New type of metal-semiconductor contact for producing schottky diode |
| US20040211974A1 (en) * | 2003-04-24 | 2004-10-28 | Chip Integration Tech. Co., Ltd. | Two mask shottky barrier diode with locos structure |
| CN101221989A (en) * | 2007-01-11 | 2008-07-16 | 株式会社东芝 | SiC schottky barrier semiconductor device |
| EP2154726A2 (en) * | 2008-08-14 | 2010-02-17 | Acreo AB | A method for producing a JBS diode |
| CN101656272A (en) * | 2009-07-22 | 2010-02-24 | 上海宏力半导体制造有限公司 | Schottky diode and fabricating method thereof |
| CN101740641A (en) * | 2009-12-24 | 2010-06-16 | 杭州立昂电子有限公司 | Semiconductor device |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105206681A (en) * | 2014-06-20 | 2015-12-30 | 意法半导体股份有限公司 | Wide Bandgap High-Density Semiconductor Switching Device And Manufacturing Process Thereof |
| CN105023953A (en) * | 2015-07-10 | 2015-11-04 | 淄博汉林半导体有限公司 | Vertical field effect diode and manufacture method thereof |
| WO2018068301A1 (en) * | 2016-10-14 | 2018-04-19 | 苏州晶湛半导体有限公司 | Diode and manufacturing method thereof |
| CN109860273A (en) * | 2018-12-29 | 2019-06-07 | 厦门芯光润泽科技有限公司 | MPS diode component and preparation method thereof |
| CN109888024A (en) * | 2018-12-29 | 2019-06-14 | 厦门芯光润泽科技有限公司 | MPS diode component and preparation method thereof |
| CN109888024B (en) * | 2018-12-29 | 2024-04-02 | 厦门芯光润泽科技有限公司 | MPS diode device and preparation method thereof |
| CN109860273B (en) * | 2018-12-29 | 2024-04-02 | 厦门芯光润泽科技有限公司 | MPS diode device and preparation method thereof |
| CN110010692A (en) * | 2019-04-28 | 2019-07-12 | 电子科技大学 | A kind of power semiconductor and its manufacturing method |
| CN111640781A (en) * | 2020-04-20 | 2020-09-08 | 北京天岳京成电子科技有限公司 | Composite Pin Schottky diode with plasma diffusion layer |
| CN111640781B (en) * | 2020-04-20 | 2022-11-11 | 元山(济南)电子科技有限公司 | Composite Pin Schottky diode with plasma diffusion layer |
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