CN102456570A - Manufacturing method of Schottky diode - Google Patents
Manufacturing method of Schottky diode Download PDFInfo
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- CN102456570A CN102456570A CN2010105174459A CN201010517445A CN102456570A CN 102456570 A CN102456570 A CN 102456570A CN 2010105174459 A CN2010105174459 A CN 2010105174459A CN 201010517445 A CN201010517445 A CN 201010517445A CN 102456570 A CN102456570 A CN 102456570A
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Abstract
The invention discloses a manufacturing method of a Schottky diode, which is characterized in that impurities on a substrate layer are diffused into an epitaxial layer at high temperature through a high-temperature diffusion process, so that a buffer layer with continuously reduced impurity concentration is formed on the interface of the substrate layer and the epitaxial layer. The semiconductor device manufactured by the manufacturing method of the Schottky diode has low forward voltage drop, and the electrical parameter characteristics of the device are further optimized.
Description
Technical field
The present invention relates to a kind of manufacturing approach of Schottky diode.
Background technology
Schottky diode is that a kind of metal contacts the device that forms with semiconductor, has lower forward voltage drop and high switching speed, but the application in the unfavorable properties influence device certain limit that reverse leakage current is big and reverse voltage is not high.
Fig. 2 illustrates the generalized section of conventional schottky; Specify the classical production process of Schottky diode below in conjunction with Fig. 2; Comprise: on substrate layer 1, form epitaxial loayer, carry out oxidation technology, form oxide layer in epi-layer surface through the epitaxial growth mode; Behind photoetching corrosion; Carry out high annealing again through in ad-hoc location epitaxial loayer 3 semi-conducting materials, injecting the boron ion; In drift layer 3, form P conduction type silicon semiconductor material guard ring 6, meanwhile also introduced oxide layer 5 on terminal oxide layer 4 and the guard ring;
Then on this basis; On device surface, pass through evaporation of metal technology deposit one deck barrier metal NiPt; Form schottky barrier layer 7 through low-temperature alloy on drift layer 3 surface, form ohmic contact regions 8 with metal NiPt low-temperature alloy on the P conduction type silicon semiconductor material on the guard ring 6 simultaneously.
Logical at last back evaporation of metal technology at device upper surface depositing metal TiNiAg, forms anode metal layer 9; At device lower surface depositing metal TiNiAg, form cathodic metal layer 10, thereby draw the negative electrode and the anode of device;
Schottky diode, what forward voltage drop and reverse blocking pressure drop need be compromised chooses, because must cause the reduction of reverse blocking pressure drop when reducing forward voltage drop, also must cause the increase of forward voltage drop when improving the reverse blocking pressure drop.That is to say, on on-state performance and closed condition performance, can not accomplish to take into account comprehensively.
Summary of the invention
The present invention provides a kind of manufacturing approach with low forward voltage drop and the simple Schottky diode of technology.
1, a kind of Schottky diode; Substrate layer is a N conduction type silicon semiconductor material, is N conduction type silicon epitaxy layer on the substrate layer, is schottky barrier layer on the epitaxial loayer; There is the guard ring of P-type material at the schottky barrier layer edge, and its manufacturing approach is characterised in that: comprise the steps:
1) on substrate layer, forms epitaxial loayer through epitaxial growth;
2) carry out initial oxidation, form passivation layer on the silicon materials surface;
3) carry out High temperature diffusion technology, the impurity through this technology substrate layer gets in the epitaxial loayer through High temperature diffusion, thereby forms the impurity concentration resilient coating of reduction continuously in substrate layer and epitaxial layer interface;
4) behind photoetching corrosion, inject p type impurity annealing, form the guard ring at schottky barrier layer edge;
5) secondary photoetching corrosion, the deposit barrier metal, low-temperature sintering forms schottky barrier layer;
6) carry out the front metal metallization processes, upper surface forms metal level, forms the anode of device;
7) third photo etching corrosion anti-carves the front metal layer;
8) back side metallization technology, lower surface forms metal level, forms the negative electrode of device.
2, the manufacturing approach of Schottky diode as claimed in claim 1 is characterized in that: the doping impurity of described epitaxial loayer forms evenly doping through the epitaxial growth mode in epitaxial loayer.
3, the manufacturing approach of Schottky diode as claimed in claim 1 is characterized in that: the temperature of described High temperature diffusion technology is higher than the technological temperature of initial oxidation.
4, the manufacturing approach of Schottky diode as claimed in claim 1 is characterized in that: the p type impurity of described injection is a boron.
5, the manufacturing approach of Schottky diode as claimed in claim 1 is characterized in that: described deposit barrier metal is the alloy that contains two kinds of barrier metals.
6, the manufacturing approach of Schottky diode as claimed in claim 1 is characterized in that: described front metal layer is that multiple layer metal constitutes.
7, the manufacturing approach of Schottky diode as claimed in claim 1 is characterized in that: described metal layer on back is that multiple layer metal constitutes.
Use Schottky diode manufacturing approach of the present invention and make Schottky diode, under the almost constant situation of reverse pressure drop, have low forward voltage drop.
Description of drawings
Fig. 1 is the Schottky diode generalized section that Schottky diode manufacturing approach of the present invention forms;
Fig. 2 is the generalized section of conventional schottky.
1, substrate layer;
2, resilient coating;
3, epitaxial loayer;
4, terminal oxide layer;
5, oxide layer on the guard ring;
6, guard ring;
7, schottky barrier layer;
8, ohmic contact regions;
9, anode metal layer;
10, cathodic metal layer;
Embodiment
Fig. 1 shows the Schottky diode generalized section that Schottky diode manufacturing approach of the present invention forms, and specifies the present invention below in conjunction with Fig. 1.
A kind of Schottky diode comprises: substrate layer 1, be N conduction type semi-conducting material, and draw negative electrode at the substrate layer lower surface through cathodic metal layer 10TiNiAg; Resilient coating 2 is positioned on the substrate layer 1, is the semi-conducting material of N conduction type; Epitaxial loayer 3 is positioned on the resilient coating 2, is the semi-conducting material of N conduction type, and the impurity concentration of this layer semi-conducting material is along with reducing gradually away from substrate layer; Guard ring 6 is positioned at schottky barrier layer 7 edges, and guard ring 6 is a P conduction type silicon semiconductor material, and guard ring is arranged in drift layer 3, and guard ring 6 width are 10～60um; Epitaxial loayer 3 top N type semiconductor materials and metal NiPt low-temperature sintering form schottky barrier layer 7, and schottky barrier layer 7 is positioned on the epitaxial loayer 3, is used to form the Schottky barrier junction characteristic; Guard ring 6 forms ohmic contact regions 8 with metal NiPt low-temperature sintering; On schottky barrier layer 7 and ohmic contact regions 8, covering one deck conducting metal TiNiAg is anode metal layer 9, draws the anode of device; Oxide layer 5 on the guard ring, are positioned at the surface of guard ring 6, are the conductor oxidate passivation layers; Terminal oxide layer 4 is positioned at the surface of semiconductor device edge, is semiconductor passivation layers such as conductor oxidate or nitride.
On substrate layer 1, form epitaxial loayer through the epitaxial growth mode, substrate layer 1 phosphorus impurities concentration is set at 3 * 10
19Atom/CM
3, phosphorus impurities concentration is set at 5 * 10 in the epitaxial loayer
15Atom/CM
3, carry out oxidation technology, form oxide layer in epi-layer surface; Carry out 1100 degree diffusion technologys again; Impurity through this technology substrate layer gets in the epitaxial loayer through High temperature diffusion; Thereby form the resilient coating 2 that impurity concentration reduces continuously in substrate layer and epitaxial layer interface, in the resilient coating 2 phosphorus impurities concentration along with away from the direction of substrate layer 1 from 3 * 10
19Atom/CM
3Step-down to 5 * 10 gradually
15Atom/CM
3Behind photoetching corrosion; Carry out 1000 degree high annealings again through in ad-hoc location drift layer 3 semi-conducting materials, injecting the boron ion, in epitaxial loayer 3, form P conduction type silicon semiconductor material guard ring 6, meanwhile also introduced oxide layer 5 on terminal oxide layer 4 and the guard ring;
Then on this basis; On device surface, pass through evaporation of metal technology deposit one deck barrier metal NiPt; Form schottky barrier layer 7 through low-temperature sintering on epitaxial loayer 3 surface, form ohmic contact regions 8 with metal NiPt low-temperature sintering on the P conduction type silicon semiconductor material on the guard ring 6 simultaneously.
Logical at last back evaporation of metal technology at device upper surface depositing metal TiNiAg, forms anode metal layer 9; At device lower surface depositing metal TiNiAg, form cathodic metal layer 10, thereby draw the negative electrode and the anode of device;
As stated, when device added forward bias, resilient coating 2 had high impurity concentration with epitaxial loayer 3 lower parts, thereby the conducting resistance of the device that has reduced reduces the forward voltage drop of device; When device adds reversed bias voltage; Do not considering that device edge influences under the situation; As long as it is reasonable to form resilient coating 2 selected diffusion technologys, can not cause the obvious change of the reverse characteristic of device, conventional schottky adds reverse biased; Form the electric field strength in the epitaxial loayer; When bearing reverse blocking voltage along with resilient coating that is reduced in Schottky diode of the present invention away from schottky barrier layer 7 gradually 2 and epitaxial loayer 3, this can slow down or change the decline of electric field strength mutually with conventional schottky, does not change near the maximum local situation the schottky barrier layer 7 that still is of electric field strength in the entire device depletion layer simultaneously; Therefore it is reasonable to form resilient coating 2 selected diffusion technologys, can not cause the reduction and the anti-increase of leakage current partially time of the reverse blocking voltage of device.
Set forth the present invention through the foregoing description, also can adopt other embodiment to realize the present invention simultaneously.The present invention is not limited to above-mentioned specific embodiment, so the present invention is limited the accompanying claims scope.
Claims (7)
1. Schottky diode; Substrate layer is a N conduction type silicon semiconductor material, and the N conduction type silicon epitaxy layer for mixing on the substrate layer is schottky barrier layer on the epitaxial loayer; There is the P-type material guard ring at the schottky barrier layer edge, and its manufacturing approach is characterised in that: comprise the steps:
1) on substrate layer, forms epitaxial loayer through epitaxial growth;
2) carry out initial oxidation, form passivation layer on the silicon materials surface;
3) carry out High temperature diffusion technology;
4) behind photoetching corrosion, inject p type impurity annealing;
5) secondary photoetching corrosion, deposit barrier metal, low-temperature sintering;
6) carry out the front metal metallization processes, upper surface forms metal level;
7) third photo etching corrosion anti-carves the front metal layer;
8) back side metallization technology, lower surface forms metal level.
2. the manufacturing approach of Schottky diode as claimed in claim 1 is characterized in that: the doping impurity of described epitaxial loayer forms in epitaxial loayer evenly through the epitaxial growth mode and to mix.
3. the manufacturing approach of Schottky diode as claimed in claim 1, it is characterized in that: the temperature of described High temperature diffusion technology is higher than the technological temperature of initial oxidation.
4. the manufacturing approach of Schottky diode as claimed in claim 1, it is characterized in that: the p type impurity of described injection is a boron.
5. the manufacturing approach of Schottky diode as claimed in claim 1, it is characterized in that: the barrier metal of described deposit is the alloy that contains two kinds of barrier metals.
6. the manufacturing approach of Schottky diode as claimed in claim 1 is characterized in that: described front metal layer is that multiple layer metal constitutes.
7. the manufacturing approach of Schottky diode as claimed in claim 1 is characterized in that: described metal layer on back is that multiple layer metal constitutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105174459A CN102456570A (en) | 2010-10-22 | 2010-10-22 | Manufacturing method of Schottky diode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105174459A CN102456570A (en) | 2010-10-22 | 2010-10-22 | Manufacturing method of Schottky diode |
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| CN102456570A true CN102456570A (en) | 2012-05-16 |
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| CN2010105174459A Pending CN102456570A (en) | 2010-10-22 | 2010-10-22 | Manufacturing method of Schottky diode |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105552119A (en) * | 2015-12-17 | 2016-05-04 | 扬州国宇电子有限公司 | Planar Schottky barrier diode |
| CN106409828A (en) * | 2016-11-30 | 2017-02-15 | 上海芯石微电子有限公司 | Half-bridge rectification Schottky device suitable for miniaturization packaging and manufacturing method thereof |
| CN108447786A (en) * | 2018-04-04 | 2018-08-24 | 华越微电子有限公司 | A Processing Technology Can Reduce the Forward Voltage Drop Value of Schottky Diode |
| CN111354642A (en) * | 2020-05-13 | 2020-06-30 | 电子科技大学 | Manufacturing method of low-on-resistance low-voltage groove gate MOS device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5737886A (en) * | 1980-08-20 | 1982-03-02 | Hitachi Ltd | Semiconductor device |
| US20020098632A1 (en) * | 2000-09-28 | 2002-07-25 | Buchanan Walter R. | High voltage device and method |
| CN1407632A (en) * | 2001-08-30 | 2003-04-02 | 三洋电机株式会社 | Shottky barrier diode and its manufacture |
| CN101015059A (en) * | 2004-07-15 | 2007-08-08 | 飞兆半导体公司 | Schottky diode structure to reduce capacitance and switching losses and method of making same |
| CN101621080A (en) * | 2008-10-14 | 2010-01-06 | 常州星海电子有限公司 | High anti-static Schottky diode |
-
2010
- 2010-10-22 CN CN2010105174459A patent/CN102456570A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5737886A (en) * | 1980-08-20 | 1982-03-02 | Hitachi Ltd | Semiconductor device |
| US20020098632A1 (en) * | 2000-09-28 | 2002-07-25 | Buchanan Walter R. | High voltage device and method |
| CN1407632A (en) * | 2001-08-30 | 2003-04-02 | 三洋电机株式会社 | Shottky barrier diode and its manufacture |
| CN101015059A (en) * | 2004-07-15 | 2007-08-08 | 飞兆半导体公司 | Schottky diode structure to reduce capacitance and switching losses and method of making same |
| CN101621080A (en) * | 2008-10-14 | 2010-01-06 | 常州星海电子有限公司 | High anti-static Schottky diode |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105552119A (en) * | 2015-12-17 | 2016-05-04 | 扬州国宇电子有限公司 | Planar Schottky barrier diode |
| CN106409828A (en) * | 2016-11-30 | 2017-02-15 | 上海芯石微电子有限公司 | Half-bridge rectification Schottky device suitable for miniaturization packaging and manufacturing method thereof |
| CN106409828B (en) * | 2016-11-30 | 2023-06-02 | 上海芯石微电子有限公司 | A half-bridge rectifier Schottky device suitable for miniaturization packaging and its manufacturing method |
| CN108447786A (en) * | 2018-04-04 | 2018-08-24 | 华越微电子有限公司 | A Processing Technology Can Reduce the Forward Voltage Drop Value of Schottky Diode |
| CN111354642A (en) * | 2020-05-13 | 2020-06-30 | 电子科技大学 | Manufacturing method of low-on-resistance low-voltage groove gate MOS device |
| CN111354642B (en) * | 2020-05-13 | 2021-09-14 | 电子科技大学 | Manufacturing method of low-on-resistance low-voltage groove gate MOS device |
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Application publication date: 20120516 |