CN111354642A - Manufacturing method of low-on-resistance low-voltage groove gate MOS device - Google Patents
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Abstract
The invention provides a manufacturing method of a low-voltage groove gate MOS device with low on-resistance, which diffuses impurities in an epitaxial wafer substrate into an epitaxial layer through a thermal diffusion process of an epitaxial wafer, so that the impurities at the bottom of the epitaxial layer are changed into linear or quasi-linear graded distribution, and the on-resistance of the epitaxial layer is greatly reduced while certain withstand voltage capability of the epitaxial layer is maintained. Compared with the traditional method, the manufacturing method provided by the invention has the following advantages: firstly, the groove gate MOS device manufactured by the manufacturing method provided by the invention has lower on-resistance; secondly, for the same voltage-resistant grade, the scheme can adopt the epitaxial layer thickness larger than that of the traditional method, so that the requirement on the control of the epitaxial thickness is lower, and the yield of the device can be improved; thirdly, the requirement on the distribution control of the impurities of the epitaxial layer is lower, and the yield of the device can be improved; fourthly, the performance of the groove gate MOS device manufactured by the manufacturing method provided by the invention is less influenced by the back-expansion of the substrate.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and mainly relates to a manufacturing method of a low-on-resistance low-voltage groove gate MOS device.
Background
The groove grid power MOS device has the characteristics of high integration level, low on-resistance, high switching speed and small switching loss, is widely applied to various power supply management and switching conversion, and has wide development and application prospects. For trench power MOS, especially for applications in the field of power management, the reduction of device on-resistance has been a continuous pursuit of engineers.
For low voltage trench-gate MOS devices, engineers often use very thin epitaxial materials to fabricate the devices in order to reduce the on-resistance of the devices as much as possible. However, for thin epitaxial materials, the uniformity of epitaxial thickness and the uniformity of epitaxial impurity distribution are extremely difficult to control, so that the schemes commonly used in the field for reducing the on-resistance of the device, such as linear epitaxy, super junction structures and the like, are difficult to realize in the thin epitaxial materials, and in addition, the phenomenon of impurity diffusion into the epitaxial layer (substrate back-diffusion) in the substrate caused by the thermal process in the device manufacturing process has a greater influence in the thin epitaxy (when the epitaxial thickness is thinned, the proportion of the epitaxial thickness influenced by the substrate back-diffusion in the total epitaxial thickness becomes greater), and the manufacturing difficulty and manufacturing cost of the low-on-resistance low-voltage trench gate MOS device are always high.
Disclosure of Invention
In order to solve the problems, the invention provides a manufacturing method of a low-voltage groove gate MOS device with low on-resistance, which is characterized in that impurities in an epitaxial wafer substrate are diffused into an epitaxial layer by applying a thermal diffusion process with certain temperature and time to the epitaxial wafer, so that the impurities at the bottom of the epitaxial layer are changed into linear or quasi-linear slowly-varying distribution, and the on-resistance of the epitaxial layer is greatly reduced while certain voltage-resisting capacity of the epitaxial layer is maintained.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a manufacturing method of a low-on-resistance low-voltage groove gate MOS device comprises the following steps:
step 1, selecting an epitaxial wafer consisting of a heavily doped first conductive type substrate 01 and a lightly doped first conductive type epitaxial layer 02;
step 2, forming a masking layer 11 on the back of the epitaxial wafer, thermally growing or depositing a dielectric layer 12 formed by a silicon dioxide film on the surface of the first conductive type epitaxial layer 02 to be used as a masking layer for thermal diffusion and a mask for groove etching, wherein the thickness of the dielectric layer 12 is determined by the groove etching depth;
step 3, setting time and temperature according to withstand voltage requirements and the thickness and doping concentration of the first conductive type epitaxial layer 02, and performing thermal diffusion on the silicon wafer to diffuse impurities in the first conductive type substrate 01 into the first conductive type epitaxial layer 02, so that linear or quasi-linear impurity distribution is formed at the bottom of the first conductive type epitaxial layer 02;
step 4, etching a U-shaped groove on the surface of the first conductive type epitaxial layer 02, and forming a gate oxide layer 06 and a gate polysilicon 07 in the groove;
step 5, forming a second conductive type well region 03 on the surface of the first conductive type epitaxial layer 02 through one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region 03 is higher than the bottom of the gate polysilicon 07 or is flush with the bottom of the gate polysilicon 07;
step 6, forming a heavily doped first conductive type source region 04 on the surface of the first conductive type epitaxial layer 02 through one or more times of first conductive type impurity ion implantation, wherein the bottom of the first conductive type source region 04 is lower than the top of the gate polysilicon 07;
step 7, forming a dielectric layer and a contact hole by deposition, photoetching and etching processes, taking the dielectric layer as a mask, and forming a heavily doped second conductive type well region contact region 05 on the surface of the first conductive type epitaxial layer 02 by one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region contact region 05 is flush with the bottom of the first conductive type source region 04; the implantation dosage of the second conductive type well region contact region 05 is less than that of the first conductive type source region 04;
and 8, metalizing the surface, forming source metal 20 through a photoetching process, thinning the substrate, and metalizing the back to form drain metal 10.
Preferably, the temperature of the silicon wafer subjected to thermal diffusion in the step 3 is between 1000 and 1200 ℃.
Preferably, the time required for the thermal diffusion of the silicon wafer in the step 3 is between 30min and 240 min.
The invention also provides a manufacturing method of the low-on-resistance low-voltage groove gate MOS device, which comprises the following steps:
step 1, selecting an epitaxial wafer consisting of a heavily doped first conductive type substrate 01 and a lightly doped first conductive type epitaxial layer 02;
step 2, forming a second conductive type well region 03 on the top of the first conductive type epitaxial layer 02 through one or more times of second conductive type ion implantation;
step 3, forming a masking layer 11 on the back of the epitaxial wafer, thermally growing or depositing a dielectric layer 12 formed by a silicon dioxide film on the surface of the first conductive type epitaxial layer 02 to be used as a masking layer for thermal diffusion and a mask for groove etching, wherein the thickness of the dielectric layer 12 is determined by the groove etching depth;
step 4, setting time and temperature according to withstand voltage requirements and the thickness and doping concentration of the first conductive type epitaxial layer 02, and performing thermal diffusion on the silicon wafer to diffuse impurities in the first conductive type substrate 01 into the first conductive type epitaxial layer 02, so that linear or quasi-linear impurity distribution is formed at the bottom of the first conductive type epitaxial layer 02;
step 5, etching a U-shaped groove on the surface of the epitaxial layer 02, and forming a gate oxide layer 06 and a gate polysilicon 07 in the groove;
step 6, forming a heavily doped first conductive type source region 04 on the surface of the first conductive type epitaxial layer 02 through one or more times of first conductive type impurity ion implantation, wherein the bottom of the first conductive type source region 04 is lower than the top of the gate polysilicon 07;
step 7, forming a dielectric layer and a contact hole by deposition, photoetching and etching processes, taking the dielectric layer as a mask, and forming a heavily doped second conductive type well region contact region 05 on the surface of the first conductive type epitaxial layer 02 by one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region contact region 05 is flush with the bottom of the first conductive type source region 04; the implantation dosage of the second conductive type well region contact region 05 is less than that of the first conductive type source region 04;
and 8, metalizing the surface, forming source metal 20 through a photoetching process, thinning the substrate, and metalizing the back to form drain metal 10.
The invention also provides a manufacturing method of the low-on-resistance low-voltage groove gate MOS device, which comprises the following steps:
step 1, selecting an epitaxial wafer consisting of a heavily doped first conductive type substrate 01 and a lightly doped first conductive type epitaxial layer 02;
step 2, forming a masking layer 11 on the back of the epitaxial wafer, and depositing the masking layer on the surface of the first conduction type epitaxial layer 02;
step 3, setting time and temperature according to withstand voltage requirements and the thickness and doping concentration of the first conductive type epitaxial layer 02, and performing thermal diffusion on the silicon wafer to diffuse impurities in the first conductive type substrate 01 into the first conductive type epitaxial layer 02, so that linear or quasi-linear impurity distribution is formed at the bottom of the first conductive type epitaxial layer 02;
step 4, removing the masking layer on the surface of the epitaxial layer 02, and forming a second conductive type well region 03 on the surface of the first conductive type epitaxial layer 02 through one or more times of second conductive type impurity ion implantation;
step 5, thermally growing or depositing a silicon dioxide film on the surface of the first conductive type epitaxial layer 02 to form a dielectric layer 12 serving as a mask for groove etching, wherein the thickness of the dielectric layer 12 is determined by the groove etching depth;
step 6, etching a U-shaped groove on the surface of the first conductive type epitaxial layer 02, and forming a gate oxide layer 06 and a gate polysilicon 07 in the groove, wherein the bottom of the gate polysilicon 07 is lower than the bottom of the second conductive type well region 03;
step 7, forming a heavily doped first conductive type source region 04 on the surface of the first conductive type epitaxial layer 02 through one or more times of first conductive type impurity ion implantation, wherein the bottom of the first conductive type source region 04 is lower than the top of the gate polysilicon 07;
step 8, forming a dielectric layer and a contact hole by deposition, photoetching and etching processes, taking the dielectric layer as a mask, and forming a heavily doped second conductive type well region contact region 05 on the surface of the first conductive type epitaxial layer 02 by one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region contact region 05 is flush with the bottom of the first conductive type source region 04; the implantation dosage of the second conductive type well region contact region 05 is less than that of the first conductive type source region 04;
and 9, metalizing the surface, forming source metal 20 through a photoetching process, thinning the substrate, and metalizing the back to form drain metal 10.
The invention also provides a manufacturing method of the low-on-resistance low-voltage groove gate MOS device, which comprises the following steps:
step 1, selecting an epitaxial wafer consisting of a heavily doped first conductive type substrate 01 and a lightly doped first conductive type epitaxial layer 02;
step 2, forming a masking layer 11 on the back of the epitaxial wafer, and depositing the masking layer on the surface of the first conduction type epitaxial layer 02;
step 3, setting time and temperature according to withstand voltage requirements and the thickness and doping concentration of the first conductive type epitaxial layer 02, and performing thermal diffusion on the silicon wafer to diffuse impurities in the first conductive type substrate 01 into the first conductive type epitaxial layer 02, so that linear or quasi-linear impurity distribution is formed at the bottom of the first conductive type epitaxial layer 02;
step 4, removing the masking layer on the surface of the epitaxial layer 02, and forming a second conductive type well region 03 on the surface of the first conductive type epitaxial layer 02 through one or more times of second conductive type impurity ion implantation;
step 5, forming a heavily doped first conduction type source region 04 on the surface of the first conduction type epitaxial layer 02 through one or more times of first conduction type impurity ion implantation;
step 6, thermally growing or depositing a silicon dioxide film on the surface of the first conductive type epitaxial layer 02 to form a dielectric layer 12 serving as a mask for groove etching, wherein the thickness of the dielectric layer 12 is determined by the groove etching depth;
step 7, etching a U-shaped groove on the surface of the first conductive type epitaxial layer 02, and forming a gate oxide layer 06 and a gate polysilicon 07 in the groove; the top of the gate polysilicon 07 is higher than the bottom of the first conductive type source region 04, and the bottom of the gate polysilicon 07 is lower than the bottom of the second conductive type well region 03;
step 8, forming a dielectric layer and a contact hole by deposition, photoetching and etching processes, taking the dielectric layer as a mask, and forming a heavily doped second conductive type well region contact region 05 on the surface of the first conductive type epitaxial layer 02 by one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region contact region 05 is flush with the bottom of the first conductive type source region 04; the implantation dosage of the second conductive type well region contact region 05 is less than that of the first conductive type source region 04;
and 9, metalizing the surface, forming source metal 20 through a photoetching process, thinning the substrate, and metalizing the back to form drain metal 10.
The invention has the beneficial effects that: firstly, the groove gate MOS device manufactured by the manufacturing method provided by the invention has lower on-resistance; secondly, for the same voltage-resistant grade, the scheme can adopt the epitaxial layer thickness larger than that of the traditional method, so that the requirement on the control of the epitaxial thickness is lower, and the yield of the device can be improved; thirdly, compared with the traditional scheme, the method has lower requirement on the distribution control of the impurities of the epitaxial layer, and can improve the yield of devices; fourth, the performance of the trench gate MOS device manufactured by the manufacturing method proposed by the present invention is less affected by the substrate back-diffusion compared to the conventional scheme.
Drawings
Fig. 1 is a structural view of a trench gate MOS device.
Fig. 2 is a manufacturing flowchart of a method for manufacturing a low on-resistance trench gate MOS device according to embodiment 1 of the present invention.
FIG. 3a is a cross-sectional view of step 1 of example 1 and the distribution of impurity concentration at the position of the dotted line in the figure.
FIG. 3b is a cross-sectional view of step 2 of example 1 and the distribution of impurity concentration at the position of the dotted line in the figure.
FIG. 3c is a cross-sectional view of step 3 of example 1 and the distribution of impurity concentration at the position of the dotted line in the figure.
FIG. 3d is a cross-sectional view of example 1 after step 4 and the distribution of impurity concentration at the position of the dotted line in the figure.
FIG. 3e is a cross-sectional view of example 1 after completion of the fabrication and the distribution of impurity concentration at the position of the dotted line in the figure.
Fig. 4 is a manufacturing flowchart of embodiment 2 of the method for manufacturing a low on-resistance trench gate MOS device according to the present invention.
Fig. 5 is a manufacturing flowchart of embodiment 3 of the method for manufacturing a low on-resistance trench gate MOS device according to the present invention.
Fig. 6 is a manufacturing flowchart of a method for manufacturing a low on-resistance trench gate MOS device according to embodiment 4 of the present invention.
The structure comprises a substrate 01 of a first conductivity type, an epitaxial layer 02 of the first conductivity type, a well 03 of a second conductivity type, a source region 04 of the first conductivity type, a well contact region 05 of the second conductivity type, a gate oxide layer 06, a gate polysilicon layer 07, a drain metal 10, a masking layer 11, a dielectric layer 12 and a source metal 20.
Detailed Description
Example 1
The method for manufacturing a low on-resistance trench gate MOS device according to the present invention is specifically described by taking a manufacturing process of a 20V withstand voltage low on-resistance trench gate MOS device as an example, and mainly includes the following steps:
step 1, selecting an epitaxial wafer consisting of a heavily doped first conductive type substrate 01 and a lightly doped first conductive type epitaxial layer 02;
step 2, forming a masking layer 11 on the back of the epitaxial wafer, thermally growing or depositing a dielectric layer 12 formed by a silicon dioxide film on the surface of the first conductive type epitaxial layer 02 to be used as a masking layer for thermal diffusion and a mask for groove etching, wherein the thickness of the dielectric layer 12 is determined by the groove etching depth;
step 3, setting time and temperature according to withstand voltage requirements and the thickness and doping concentration of the first conductive type epitaxial layer 02, and performing thermal diffusion on the silicon wafer to diffuse impurities in the first conductive type substrate 01 into the first conductive type epitaxial layer 02, so that linear or quasi-linear impurity distribution is formed at the bottom of the first conductive type epitaxial layer 02; the temperature of thermal diffusion is between 1000 ℃ and 1200 ℃, and the time required by thermal diffusion is between 30min and 240 min.
Step 4, etching a U-shaped groove on the surface of the first conductive type epitaxial layer 02, and forming a gate oxide layer 06 and a gate polysilicon 07 in the groove;
step 5, forming a second conductive type well region 03 on the surface of the first conductive type epitaxial layer 02 through one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region 03 is higher than the bottom of the gate polysilicon 07 or is flush with the bottom of the gate polysilicon 07;
step 6, forming a heavily doped first conductive type source region 04 on the surface of the first conductive type epitaxial layer 02 through one or more times of first conductive type impurity ion implantation, wherein the bottom of the first conductive type source region 04 is lower than the top of the gate polysilicon 07;
step 7, forming a dielectric layer and a contact hole by deposition, photoetching and etching processes, taking the dielectric layer as a mask, and forming a heavily doped second conductive type well region contact region 05 on the surface of the first conductive type epitaxial layer 02 by one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region contact region 05 is flush with the bottom of the first conductive type source region 04; the implantation dosage of the second conductive type well region contact region 05 is less than that of the first conductive type source region 04;
and 8, metalizing the surface, forming source metal 20 through a photoetching process, thinning the substrate, and metalizing the back to form drain metal 10.
When the manufacturing method of the embodiment is adopted to manufacture the trench gate MOS device with the drain-source breakdown voltage of 20V, the epitaxial wafer with the substrate resistivity of 0.0011 omega cm, the epitaxial thickness of 3.0um and the epitaxial resistivity of 0.2 omega cm is adopted, and the push-up menu of 1150 ℃ and 30min is adopted in the thermal diffusion process. The specific on-resistance of the finally obtained groove gate MOS device is 0.99m omega mm2. For conventional fabrication schemes, to reach a drain-source breakdown voltage level of 20V,an epitaxial layer with a thickness of 2.3um and a specific on-resistance of 1.11m omega mm is required2. The embodiment shows that the manufacturing method provided by the invention not only can manufacture a device with lower on-resistance, but also can reduce the requirement on epitaxial materials and reduce the influence of the substrate back-diffusion phenomenon on the performance of the device. Therefore, the scheme provided by the invention can not only reduce the on-resistance of the device, but also improve the yield of the device and reduce the cost of the device.
Example 2
A manufacturing method of a low-on-resistance low-voltage groove gate MOS device comprises the following steps:
step 1, selecting an epitaxial wafer consisting of a heavily doped first conductive type substrate 01 and a lightly doped first conductive type epitaxial layer 02;
step 2, forming a second conductive type well region 03 on the top of the first conductive type epitaxial layer 02 through one or more times of second conductive type ion implantation;
step 3, forming a masking layer 11 on the back of the epitaxial wafer, thermally growing or depositing a dielectric layer 12 formed by a silicon dioxide film on the surface of the first conductive type epitaxial layer 02 to be used as a masking layer for thermal diffusion and a mask for groove etching, wherein the thickness of the dielectric layer 12 is determined by the groove etching depth;
step 4, setting time and temperature according to withstand voltage requirements and the thickness and doping concentration of the first conductive type epitaxial layer 02, and performing thermal diffusion on the silicon wafer to diffuse impurities in the first conductive type substrate 01 into the first conductive type epitaxial layer 02, so that linear or quasi-linear impurity distribution is formed at the bottom of the first conductive type epitaxial layer 02;
step 5, etching a U-shaped groove on the surface of the epitaxial layer 02, and forming a gate oxide layer 06 and a gate polysilicon 07 in the groove;
step 6, forming a heavily doped first conductive type source region 04 on the surface of the first conductive type epitaxial layer 02 through one or more times of first conductive type impurity ion implantation, wherein the bottom of the first conductive type source region 04 is lower than the top of the gate polysilicon 07;
step 7, forming a dielectric layer and a contact hole by deposition, photoetching and etching processes, taking the dielectric layer as a mask, and forming a heavily doped second conductive type well region contact region 05 on the surface of the first conductive type epitaxial layer 02 by one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region contact region 05 is flush with the bottom of the first conductive type source region 04; the implantation dosage of the second conductive type well region contact region 05 is less than that of the first conductive type source region 04;
and 8, metalizing the surface, forming source metal 20 through a photoetching process, thinning the substrate, and metalizing the back to form drain metal 10.
Example 3
A manufacturing method of a low-on-resistance low-voltage groove gate MOS device comprises the following steps:
step 1, selecting an epitaxial wafer consisting of a heavily doped first conductive type substrate 01 and a lightly doped first conductive type epitaxial layer 02;
step 2, forming a masking layer 11 on the back of the epitaxial wafer, and depositing the masking layer on the surface of the first conduction type epitaxial layer 02;
step 3, setting time and temperature according to withstand voltage requirements and the thickness and doping concentration of the first conductive type epitaxial layer 02, and performing thermal diffusion on the silicon wafer to diffuse impurities in the first conductive type substrate 01 into the first conductive type epitaxial layer 02, so that linear or quasi-linear impurity distribution is formed at the bottom of the first conductive type epitaxial layer 02;
step 4, removing the masking layer on the surface of the epitaxial layer 02, and forming a second conductive type well region 03 on the surface of the first conductive type epitaxial layer 02 through one or more times of second conductive type impurity ion implantation;
step 5, thermally growing or depositing a silicon dioxide film on the surface of the first conductive type epitaxial layer 02 to form a dielectric layer 12 serving as a mask for groove etching, wherein the thickness of the dielectric layer 12 is determined by the groove etching depth;
step 6, etching a U-shaped groove on the surface of the first conductive type epitaxial layer 02, and forming a gate oxide layer 06 and a gate polysilicon 07 in the groove, wherein the bottom of the gate polysilicon 07 is lower than the bottom of the second conductive type well region 03;
step 7, forming a heavily doped first conductive type source region 04 on the surface of the first conductive type epitaxial layer 02 through one or more times of first conductive type impurity ion implantation, wherein the bottom of the first conductive type source region 04 is lower than the top of the gate polysilicon 07;
step 8, forming a dielectric layer and a contact hole by deposition, photoetching and etching processes, taking the dielectric layer as a mask, and forming a heavily doped second conductive type well region contact region 05 on the surface of the first conductive type epitaxial layer 02 by one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region contact region 05 is flush with the bottom of the first conductive type source region 04; the implantation dosage of the second conductive type well region contact region 05 is less than that of the first conductive type source region 04;
and 9, metalizing the surface, forming source metal 20 through a photoetching process, thinning the substrate, and metalizing the back to form drain metal 10.
Example 4
A manufacturing method of a low-on-resistance low-voltage groove gate MOS device comprises the following steps:
step 1, selecting an epitaxial wafer consisting of a heavily doped first conductive type substrate 01 and a lightly doped first conductive type epitaxial layer 02;
step 2, forming a masking layer 11 on the back of the epitaxial wafer, and depositing the masking layer on the surface of the first conduction type epitaxial layer 02;
step 3, setting time and temperature according to withstand voltage requirements and the thickness and doping concentration of the first conductive type epitaxial layer 02, and performing thermal diffusion on the silicon wafer to diffuse impurities in the first conductive type substrate 01 into the first conductive type epitaxial layer 02, so that linear or quasi-linear impurity distribution is formed at the bottom of the first conductive type epitaxial layer 02;
step 4, removing the masking layer on the surface of the epitaxial layer 02, and forming a second conductive type well region 03 on the surface of the first conductive type epitaxial layer 02 through one or more times of second conductive type impurity ion implantation;
step 5, forming a heavily doped first conduction type source region 04 on the surface of the first conduction type epitaxial layer 02 through one or more times of first conduction type impurity ion implantation;
step 6, thermally growing or depositing a silicon dioxide film on the surface of the first conductive type epitaxial layer 02 to form a dielectric layer 12 serving as a mask for groove etching, wherein the thickness of the dielectric layer 12 is determined by the groove etching depth;
step 7, etching a U-shaped groove on the surface of the first conductive type epitaxial layer 02, and forming a gate oxide layer 06 and a gate polysilicon 07 in the groove; the top of the gate polysilicon 07 is higher than the bottom of the first conductive type source region 04, and the bottom of the gate polysilicon 07 is lower than the bottom of the second conductive type well region 03;
step 8, forming a dielectric layer and a contact hole by deposition, photoetching and etching processes, taking the dielectric layer as a mask, and forming a heavily doped second conductive type well region contact region 05 on the surface of the first conductive type epitaxial layer 02 by one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region contact region 05 is flush with the bottom of the first conductive type source region 04; the implantation dosage of the second conductive type well region contact region 05 is less than that of the first conductive type source region 04;
and 9, metalizing the surface, forming source metal 20 through a photoetching process, thinning the substrate, and metalizing the back to form drain metal 10.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (6)
1. A manufacturing method of a low-on-resistance low-voltage groove gate MOS device is characterized by comprising the following steps:
step 1, selecting an epitaxial wafer consisting of a heavily doped first conductive type substrate (01) and a lightly doped first conductive type epitaxial layer (02);
step 2, forming a masking layer (11) on the back of the epitaxial wafer, thermally growing or depositing a dielectric layer (12) formed by a silicon dioxide film on the surface of the first conductive type epitaxial layer (02) to be used as a masking layer for thermal diffusion and a mask for groove etching, wherein the thickness of the dielectric layer (12) is determined by the groove etching depth;
step 3, setting time and temperature according to withstand voltage requirements and the thickness and doping concentration of the first conductive type epitaxial layer (02), and performing thermal diffusion on the silicon wafer to diffuse impurities in the first conductive type substrate (01) into the first conductive type epitaxial layer (02), so that linear or quasi-linear impurity distribution is formed at the bottom of the first conductive type epitaxial layer (02);
step 4, etching a U-shaped groove on the surface of the first conductive type epitaxial layer (02), and forming a gate oxide layer (06) and gate polysilicon (07) in the groove;
step 5, forming a second conductive type well region (03) on the surface of the first conductive type epitaxial layer (02) through one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region (03) is higher than the bottom of the grid polysilicon (07) or is flush with the bottom of the grid polysilicon (07);
step 6, forming a heavily doped first conductive type source region (04) on the surface of the first conductive type epitaxial layer (02) through one or more times of first conductive type impurity ion implantation, wherein the bottom of the first conductive type source region (04) is lower than the top of the grid polysilicon (07);
step 7, forming a dielectric layer and a contact hole by deposition, photoetching and etching processes, taking the dielectric layer as a mask, and forming a heavily doped second conductive type well region contact region (05) on the surface of the first conductive type epitaxial layer (02) by one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region contact region (05) is flush with the bottom of the first conductive type source region (04); the implantation dosage of the second conduction type well region contact region (05) is less than that of the first conduction type source region (04);
and 8, metalizing the surface, forming source metal (20) through a photoetching process, thinning the substrate, and metalizing the back to form drain metal (10).
2. The manufacturing method of low on-resistance low-voltage trench gate MOS device as claimed in claim 1, wherein: the process of claim 1 wherein step 3 is carried out at a temperature of between 1000 ℃ and 1200 ℃ while thermally diffusing the silicon wafer.
3. The manufacturing method of low on-resistance low-voltage groove gate MOS device as claimed in claim 1, wherein the time required for thermal diffusion of the silicon wafer in step 3 in claim 1 is between 30min and 240 min.
4. A manufacturing method of a low-on-resistance low-voltage groove gate MOS device is characterized by comprising the following steps:
step 1, selecting an epitaxial wafer consisting of a heavily doped first conductive type substrate (01) and a lightly doped first conductive type epitaxial layer (02);
step 2, forming a second conductive type well region (03) on the top of the first conductive type epitaxial layer (02) through one or more times of second conductive type ion implantation;
step 3, forming a masking layer (11) on the back of the epitaxial wafer, thermally growing or depositing a dielectric layer (12) formed by a silicon dioxide film on the surface of the first conductive type epitaxial layer (02) to be used as a masking layer for thermal diffusion and a mask for groove etching, wherein the thickness of the dielectric layer (12) is determined by the groove etching depth;
step 4, setting time and temperature according to withstand voltage requirements and the thickness and doping concentration of the first conductive type epitaxial layer (02), and performing thermal diffusion on the silicon wafer to diffuse impurities in the first conductive type substrate (01) into the first conductive type epitaxial layer (02), so that linear or quasi-linear impurity distribution is formed at the bottom of the first conductive type epitaxial layer (02);
step 5, etching a U-shaped groove on the surface of the epitaxial layer (02), and forming a gate oxide layer (06) and gate polysilicon (07) in the groove;
step 6, forming a heavily doped first conductive type source region (04) on the surface of the first conductive type epitaxial layer (02) through one or more times of first conductive type impurity ion implantation, wherein the bottom of the first conductive type source region (04) is lower than the top of the grid polysilicon (07);
step 7, forming a dielectric layer and a contact hole by deposition, photoetching and etching processes, taking the dielectric layer as a mask, and forming a heavily doped second conductive type well region contact region (05) on the surface of the first conductive type epitaxial layer (02) by one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region contact region (05) is flush with the bottom of the first conductive type source region (04); the implantation dosage of the second conduction type well region contact region (05) is less than that of the first conduction type source region (04);
and 8, metalizing the surface, forming source metal (20) through a photoetching process, thinning the substrate, and metalizing the back to form drain metal (10).
5. A manufacturing method of a low-on-resistance low-voltage groove gate MOS device is characterized by comprising the following steps:
step 1, selecting an epitaxial wafer consisting of a heavily doped first conductive type substrate (01) and a lightly doped first conductive type epitaxial layer (02);
step 2, forming a masking layer (11) on the back surface of the epitaxial wafer, and depositing the masking layer on the surface of the first conduction type epitaxial layer (02);
step 3, setting time and temperature according to withstand voltage requirements and the thickness and doping concentration of the first conductive type epitaxial layer (02), and performing thermal diffusion on the silicon wafer to diffuse impurities in the first conductive type substrate (01) into the first conductive type epitaxial layer (02), so that linear or quasi-linear impurity distribution is formed at the bottom of the first conductive type epitaxial layer (02);
step 4, removing the masking layer on the surface of the epitaxial layer (02), and forming a second conductive type well region (03) on the surface of the first conductive type epitaxial layer (02) through one or more times of second conductive type impurity ion implantation;
step 5, thermally growing or depositing a dielectric layer (12) formed by a silicon dioxide film on the surface of the first conductive type epitaxial layer (02) to be used as a mask for groove etching, wherein the thickness of the dielectric layer (12) is determined by the groove etching depth;
step 6, etching a U-shaped groove on the surface of the first conductive type epitaxial layer (02), and forming a gate oxide layer (06) and gate polysilicon (07) in the groove, wherein the bottom of the gate polysilicon (07) is lower than that of the second conductive type well region (03);
step 7, forming a heavily doped first conductive type source region (04) on the surface of the first conductive type epitaxial layer (02) through one or more times of first conductive type impurity ion implantation, wherein the bottom of the first conductive type source region (04) is lower than the top of the grid polysilicon (07);
step 8, forming a dielectric layer and a contact hole by deposition, photoetching and etching processes, taking the dielectric layer as a mask, and forming a heavily doped second conductive type well region contact region (05) on the surface of the first conductive type epitaxial layer (02) by one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region contact region (05) is flush with the bottom of the first conductive type source region (04); the implantation dosage of the second conduction type well region contact region (05) is less than that of the first conduction type source region (04);
and 9, metalizing the surface, forming source metal (20) through a photoetching process, thinning the substrate, and metalizing the back to form drain metal (10).
6. A manufacturing method of a low-on-resistance low-voltage groove gate MOS device is characterized by comprising the following steps:
step 1, selecting an epitaxial wafer consisting of a heavily doped first conductive type substrate (01) and a lightly doped first conductive type epitaxial layer (02);
step 2, forming a masking layer (11) on the back surface of the epitaxial wafer, and depositing the masking layer on the surface of the first conduction type epitaxial layer (02);
step 3, setting time and temperature according to withstand voltage requirements and the thickness and doping concentration of the first conductive type epitaxial layer (02), and performing thermal diffusion on the silicon wafer to diffuse impurities in the first conductive type substrate (01) into the first conductive type epitaxial layer (02), so that linear or quasi-linear impurity distribution is formed at the bottom of the first conductive type epitaxial layer (02);
step 4, removing the masking layer on the surface of the epitaxial layer (02), and forming a second conductive type well region (03) on the surface of the first conductive type epitaxial layer (02) through one or more times of second conductive type impurity ion implantation;
step 5, forming a heavily doped first conductive type source region (04) on the surface of the first conductive type epitaxial layer (02) through one or more times of first conductive type impurity ion implantation;
step 6, thermally growing or depositing a dielectric layer (12) formed by a silicon dioxide film on the surface of the first conductive type epitaxial layer (02) to be used as a mask for groove etching, wherein the thickness of the dielectric layer (12) is determined by the groove etching depth;
step 7, etching a U-shaped groove on the surface of the first conductive type epitaxial layer (02), and forming a gate oxide layer (06) and gate polysilicon (07) in the groove; the top of the grid polysilicon (07) is higher than the bottom of the first conductive type source region (04), and the bottom of the grid polysilicon (07) is lower than the bottom of the second conductive type well region (03);
step 8, forming a dielectric layer and a contact hole by deposition, photoetching and etching processes, taking the dielectric layer as a mask, and forming a heavily doped second conductive type well region contact region (05) on the surface of the first conductive type epitaxial layer (02) by one or more times of second conductive type impurity ion implantation, wherein the bottom of the second conductive type well region contact region (05) is flush with the bottom of the first conductive type source region (04); the implantation dosage of the second conduction type well region contact region (05) is less than that of the first conduction type source region (04);
and 9, metalizing the surface, forming source metal (20) through a photoetching process, thinning the substrate, and metalizing the back to form drain metal (10).
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