TWI806418B - Double-epitaxy metal oxide half-field-effect transistor manufacturing method - Google Patents

Abstract

The present invention provides a double-epitaxy method for manufacturing a metal-oxygen half-field-effect transistor. The steps include: (A) providing a silicon carbide wafer substrate; (B) depositing a drift region epitaxy on the silicon carbide wafer substrate. layer; (C) deposit a buffer layer on the epitaxial layer in the drift region; (D) implant the same type of ion implantation doping as the epitaxial layer in the drift region and the buffer layer in the region of the junction field effect transistor to To form the current diffusion layer region, the present invention enables the electric field of the gate oxide layer to have a smaller electric field when it withstands high voltage by using epitaxial processes with two layers of different concentrations.

Description

Double epitaxial metal oxide half field effect transistor manufacturing method

The invention relates to a method for manufacturing a double-epitaxy metal-oxygen half-field-effect transistor, in particular to a method for manufacturing a high-power metal-oxygen half-field-effect transistor with a novel buffer layer structure design.

In the conventional technology, please refer to the first figure for the production process of the conventional 1200V high-power metal-oxide half-field effect transistor (Power MOSFET), and the junction field-effect transistor (Junction MOSFET) in the vertical high-power metal-oxide half-field effect transistor (Power MOSFET) Field Effect Transistor, JFET) region, implanted with a current spreading layer 3 (Current Spreading Layer, CSL). Due to the implantation of the current spreading layer 3 (CSL), in the case of the same junction field effect transistor width, the electric field of the gate oxide layer is relatively large, so the characteristic on-resistance (R _on,sp ) value drops within a limited range.

With the vigorous development of the electric vehicle industry, the global demand for high-power electronic components is also increasing. Many semiconductor-related scholars and wafer foundries have also devoted their efforts to silicon carbide transistors. The 1200V high-power metal oxide half field effect transistor Today, it has become a standardized product on the market, and most designs can already meet the demand for breakdown voltage. Therefore, how to reduce the characteristic on-resistance of components is a major demand in the future.

To sum up, the current vertical high-power metal oxide half field effect transistor still has defects. Therefore, the applicant of this case researched and developed a double epitaxial metal oxide half field effect transistor manufacturing method, which effectively solves the problem of junction field effect. In the case of the same transistor width, the electric field of the gate oxide layer is relatively large, resulting in a limited range of drop in the characteristic on-resistance (R _on,sp ).

In view of the shortcomings of the above-mentioned known technologies, the main purpose of the present invention is to provide a method for manufacturing a double-epitaxy metal oxide half field effect transistor, which uses a double-layer epitaxy process with different concentrations to increase the doping concentration of the epitaxy layer in the drift region, and Deposit a lightly doped buffer layer (N-buffer) epitaxy on it, and the implanted area of the current diffusion layer is maintained in the area of the junction field effect transistor, so that the electric field of the gate oxide layer can be brought under high voltage. There is a small electric field.

In order to achieve the above object, according to a solution proposed by the present invention, a method for manufacturing a double-epitaxy metal oxide half field effect transistor is provided. The steps include: (A) providing a silicon carbide wafer substrate; On the round substrate, deposit the drift region epitaxial layer; (C) deposit the buffer layer on the drift region epitaxial layer; (D) implant and drift region epitaxial layer in the junction field effect transistor area Ion implantation doping with the same type as the buffer layer to form the current diffusion layer region.

Preferably, the epitaxial doping concentration of the buffer layer can be smaller than that of the epitaxial layer of the drift region.

Preferably, the epitaxial doping concentration of the buffer layer may be 3E15cm ^-3 -6E15cm ^-3 .

Preferably, the concentration of the epitaxial layer in the drift region may be 8E15cm ^-3 -1E16cm ^-3 .

Preferably, the epitaxial thickness of the buffer layer may be smaller than the maximum ion implantation depth of the current diffusion layer.

Preferably, the buffer layer has a thickness of 0.1 to 0.9 microns.

Preferably, the thickness of the buffer layer may be 0.5 microns.

Preferably, the epitaxial doping concentration of the buffer layer may be 1E15cm ^-3 -9E15cm ^-3 .

Preferably, the concentration of the epitaxial layer in the drift region can be 1E16cm ^-3 .

Preferably, the maximum depth of ion implantation in the current diffusion layer may be 1 μm.

The above overview, the following detailed description and the accompanying drawings are all for further explaining the ways, means and effects of the present invention to achieve the intended purpose. Other purposes and advantages of the present invention will be described in the subsequent description and drawings.

1: Silicon carbide wafer substrate

2: Epitaxy layer in the drift region

3: Current spreading layer

4: P-type well

5: buffer layer

The first figure is a production flow chart of a conventional 1200V high-power metal-oxide-semiconductor field-effect transistor (Power MOSFET).

The second figure is a flow chart of the fabrication of a double epitaxial metal oxide half field effect transistor of the present invention.

The implementation of the present invention is described below through specific examples, and those skilled in the art can easily understand the advantages and effects of this creation from the content disclosed in this specification.

Please refer to the second figure. The second figure is a flow chart of the fabrication of a double epitaxial metal oxide half field effect transistor of the present invention. The present invention is to provide a double epitaxial metal oxide half field effect transistor manufacturing method, the steps include: first provide a silicon carbide wafer substrate 1, and then deposit a drift region (Drift region) on the silicon carbide wafer substrate 1 The epitaxial layer 2, then depositing a buffer layer 5 on the epitaxial layer 2 in the drift region, and then implanting the same type of ion implantation as the epitaxial layer 2 in the drift region and the buffer layer 5 in the region of the junction field effect transistor Doping to form the current diffusion layer 3 region, but not limited to N-type or P-type semiconductors, the structure proposed by the present invention is not limited to 1200V power metal oxide semiconductor field effect transistors, transistors with similar structures but different withstand voltages are also applicable.

In this embodiment, the epitaxial doping concentration of the buffer layer 5 may be lower than the epitaxial doping concentration of the drift region epitaxial layer 2 . The epitaxial doping concentration of the buffer layer 5 can be 3E15cm ^-3 ~6E15cm ^-3 , and the concentration of the drift region epitaxial layer 2 can be 8E15cm ^-3 ~1E16cm ^-3 . Preferably, the epitaxial doping concentration of the buffer layer 5 can be 1E15cm ⁻³ to 9E15cm ⁻³ , and the concentration of the epitaxial layer 2 in the drift region can be 1E16cm ⁻³ .

As mentioned above, the present invention reduces the characteristic on-resistance by using a higher concentration of the epitaxial layer 2 in the drift region, so that the transistor can have better current performance in the switching operation, and the conversion efficiency of the device in the integrated circuit can be improved.

In this embodiment, the epitaxial thickness of the buffer layer 5 can be smaller than that of the electrode The maximum depth of ion implantation in the flow diffusion layer 3 . If the maximum ion implantation depth of the current diffusion layer 3 is 1 μm, the thickness of the buffer layer 5 can be 0.1 to 0.9 μm, preferably, the thickness of the buffer layer can be 0.5 μm.

As mentioned above, the present invention creates a buffer layer 5 with an epitaxial thickness smaller than the maximum ion implantation depth of the current diffusion layer 3, so as to avoid the channel (Channel) area in the P-type well 4 region due to excessive N-type epitaxial The concentration is converted into an N-type region, so that the transistor itself forms a Normally-on element, and loses the control ability of the structure over the gate.

More specifically, the present invention uses a double-layer silicon carbide epitaxy process, which is expected to reduce the characteristic on-resistance of the 1200V high-power metal-oxide-semiconductor field effect transistor. The present invention uses a higher concentration (8E15cm ^-3 ~1E16cm ^-3 ) drift zone epitaxial layer 2, and then deposits a lower concentration (3E15cm ^-3 ~6E15cm ^-3 ) epitaxial layer on it with a thickness of 0.5 microns, To prevent the channel region in region 4 of the P-type well from being converted into an N-type region due to an excessively high N-type epitaxial concentration, so that the transistor itself forms a Normally-on element and loses the control ability of the structure over the gate. Using a lower concentration of epitaxy on the upper layer, in addition to maintaining the P-type channel region, at the same time, the junction field effect transistor (JFET) region under the gate is also reduced in carrier concentration, so that the electric field of the gate oxide layer can withstand High voltage has a small electric field. In addition, the higher epitaxy concentration of the lower layer also means that the drift region occupying most of the device structure has a higher number of carriers, so it can reduce the characteristic on-resistance and make the device operate at the same drain voltage (V _drain ) can have better current performance.

Taking a high-power metal-oxide-semiconductor field-effect transistor with a withstand voltage of 1200V as an example, the simulation data results are shown in the table below. This proposal uses a higher concentration of the drift region epitaxial layer 2 (N-drift Epi), although the breakdown voltage is reduced by about 250V, but it can greatly reduce the characteristic on-resistance (R _on,sp ) by about 0.27mΩ*cm ² , and after adding the N-buffer layer 5, it can also slightly reduce the oxide field.

In summary, the double epitaxial metal oxide semiconductor field effect transistor manufacturing method of the present invention reduces the electric field of the oxide layer, improves the reliability of the device, and maintains the gate control ability, and also uses a higher concentration of the drift region to make the characteristic The on-resistance is reduced, so that the transistor can have better current performance in the switching operation, and the conversion efficiency of the element in the integrated circuit is improved.

In various large-scale electromechanical systems, power components that can operate stably under high pressure and high temperature are required, including the booming electric vehicle industry, and the demand for components with high energy conversion efficiency and low power loss is gradually increasing. Today's transistors are designed to be able to carry higher voltages, and their on-resistance inevitably increases, thereby increasing their losses, and it is quite fatal for electric vehicles that require high efficiency, light weight, and power generation endurance.

Therefore the present invention is in the 1200V class high In terms of power transistor design, an effective high-power transistor structure is proposed, which can achieve lower on-resistance without affecting its withstand voltage capability, and the peak value of the electric field of the oxide layer can be reduced, which can effectively improve reliability and finally enable Provide the low energy loss and high stability required by the electric vehicle industry. This structure is of great help to the future development of the electric vehicle industry.

The above-mentioned embodiments are only illustrative to illustrate the characteristics and functions of the invention, and are not intended to limit the scope of the essential technical content of the invention. Any person familiar with the art can modify and change the above-mentioned embodiments without departing from the spirit and scope of creation. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of the patent application described later.

1: Silicon carbide wafer substrate

2: Epitaxy layer in the drift region

3: Current spreading layer

4: P-type well

5: buffer layer

Claims (9)

A double-epitaxy metal oxide half-field-effect transistor manufacturing method, the steps comprising: (A) providing a silicon carbide wafer substrate; (B) depositing a drift region epitaxial layer on the silicon carbide wafer substrate (C) depositing a buffer layer on the epitaxial layer in the drift region; (D) implanting an ion distribution of the same type as the epitaxial layer in the drift region and the buffer layer in a region of a junction field effect transistor Implanting doping to form a current diffusion layer region, wherein the epitaxial doping concentration of the buffer layer is smaller than that of the drift region epitaxial layer. The double epitaxial metal oxide half-field-effect transistor manufacturing method described in item 1 of the scope of the patent application, wherein the epitaxial doping concentration of the buffer layer is 3E15 cm ^-3 ~6E15 cm ^-3 . The double epitaxial metal oxide half-field-effect transistor manufacturing method described in item 2 of the scope of the patent application, wherein the concentration of the epitaxial layer in the drift region is 8E15 cm ^-3 to 1E16 cm ^-3 . The double epitaxial metal oxide semiconductor field-effect transistor manufacturing method described in item 1 of the scope of the patent application, wherein the epitaxial thickness of the buffer layer is smaller than the maximum ion implantation depth of the current diffusion layer. The method for manufacturing a double epitaxial metal oxide half field effect transistor as described in item 4 of the scope of the patent application, wherein the thickness of the buffer layer is 0.1 to 0.9 microns. The method for manufacturing double epitaxial metal oxide half-field-effect transistors as described in item 5 of the scope of the patent application, wherein the thickness of the buffer layer is 0.5 microns. The double epitaxial metal oxide semiconductor field-effect transistor manufacturing method described in item 2 of the scope of the patent application, wherein the epitaxial doping concentration of the buffer layer is 1E15 cm ^-3 ~9E15 cm ^-3 . The double epitaxial metal oxide half-field-effect transistor manufacturing method described in item 3 of the scope of the patent application, wherein the concentration of the epitaxial layer in the drift region is 1E16 cm ^-3 . The method for manufacturing a double epitaxial metal oxide half-field effect transistor as described in item 4 of the scope of the patent application, wherein the maximum depth of ion implantation in the current diffusion layer is 1 μm.

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