CN102013392A - Forming method of diffusion zone - Google Patents
Forming method of diffusion zone Download PDFInfo
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- CN102013392A CN102013392A CN2009101952190A CN200910195219A CN102013392A CN 102013392 A CN102013392 A CN 102013392A CN 2009101952190 A CN2009101952190 A CN 2009101952190A CN 200910195219 A CN200910195219 A CN 200910195219A CN 102013392 A CN102013392 A CN 102013392A
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Abstract
The invention relates to a forming method of a diffusion zone, comprising the following steps of: forming a pre-doping layer on the surface of a semiconductor substrate, wherein doping ions are contained in the pre-doping layer; forming a protecting layer on the pre-doping layer; annealing the semiconductor substrate; and diffusing the doping ions in the pre-doping layer into the semiconductor substrate. In the invention, by replacing the traditional mode of injecting ions to dope the diffusion zone with a furnace tube thermal diffusion technology, the damage to the surface of the semiconductor substrate by ionic bombardment is avoided, foreign ions are ensured to be more evenly distributed in the diffusion zone, a surface lattice structure is improved and a subsequent technology is benefited. In the process, the technological flow is slightly regulated, the complexity is not obviously increased, the production cost is not obviously increased, and the productivity is increased to a certain extent.
Description
Technical field
The present invention relates to field of semiconductor technology, the formation method of diffusion region in particularly a kind of semiconductor device.
Background technology
In present semiconductor technology, often need to form various types of diffusion regions, for example source region, drain region, trap, buried regions etc.For RAM (random access memory) device, in present 130nm technology, word line (word line) is normally served as by the n type buried layer in the Semiconductor substrate.So-called n type buried layer mixes and realizes that its effect is in order to reduce the volume resistance of doped region by carry out the N type to Semiconductor substrate.
Technically, Semiconductor substrate is mixed mainly by ion implantation doping.Ion implantation doping is that the foreign ion of ionization is bombarded substrate surface and enters substrate interior after electric field quickens, and it can be by measuring the strict control of ion flow dosage, thus the controlled doping concentration and the degree of depth.Although ion implantation technique has consequence in doping process, also there are some shortcomings in it: at first, after energetic ion entered Semiconductor substrate, meeting and lattice atoms bumped, and many lattice atoms are subjected to displacement, and cause the damage of lattice; Secondly, the existence at injection inclination angle makes in groove structure place ion injection rate inhomogeneous; Once more, be in certain interval, be difficult to realize shallow or dark excessively injection owing to inject energy of ions; In addition, the production of ion implantor is one chip, and production capacity is restricted; Moreover costing an arm and a leg of ion implantor increased production cost.
In the existing diffusion region formation method, be example with the n type buried layer, referring to Fig. 1 a～Fig. 1 e, mainly comprise following processing step: with reference to Fig. 1 a, prepare lightly doped P type silicon as Semiconductor substrate 100, selecting resistivity for use at this is the substrate of 8～11.5 Ω cm; Described Semiconductor substrate 100 is cleaned; With reference to Fig. 1 b, on described Semiconductor substrate 100, form the pre-doped layer 110 of one deck, the mode of employing is the boiler tube thermal oxidation, thickness is
Form Semiconductor substrate 100 ' after the thermal oxidation; With reference to Fig. 1 c, graphical pre-doped layer 110, by photoetching process definition buried regions area, the pre-doped layer 110 that etching should the zone forms pre-doped layer figure 110 ' then, the mask that injects as follow-up ion; With reference to Fig. 1 d, be that mask carries out the injection of N type ion with pre-doped layer figure 110 ', ionic type has phosphorus, arsenic, antimony etc., selects arsenic for use at this, and the injection energy is 75keV, and dosage is 1.8E15/cm
2With reference to Fig. 1 e, diffuse to form n type buried layer 120 by annealing activator impurity and propelling, after n type buried layer 120 forms, the pre-doped layer figure 110 ' of wet etching; After this, need go up in described Semiconductor substrate 100 ' and form one deck doped with P type epitaxial loayer (not shown), semiconductor device mainly is formed on this epitaxial loayer.
Because epitaxial loayer film quality quality has considerable influence to device performance, therefore the lattice structure of n type buried layer is had relatively high expectations.Under the situation of carrying out ion implantation doping, although have the annealing forward step to eliminate lattice damage, and activate the foreign ion that injects, from actual effect, the lattice damage that injection causes can't be eliminated fully, thereby can cause negative effect to the quality of epitaxial loayer.
Based on foregoing, in the diffusion region forming process, in the n type buried layer forming process of for example above-mentioned RAM device, for the reparation of Semiconductor substrate lattice damage and to avoid be an important problem.A kind of method of heat-treating (i.e. annealing) by original position or strange land that publication number is 20080258220 U.S. Patent Application Publication is avoided or alleviates being injected side effects such as the silicon substrate amorphization that causes or lattice relaxation by ion.And for example, publication number is that 20080057684 U.S. Patent application is to eliminate the defective of silicon substrate in several minutes to the high-temperature annealing process of a few hours by increasing time also.These methods are all repaired by follow-up remedial measure because ion injects the blemish cause, fail fundamentally to prevent the generation of implant damage.
Therefore, for the formation of semiconductor device diffusion region, need a kind of method that can prevent effectively that implant damage from producing of exploitation.
Summary of the invention
The problem that the present invention solves provides a kind of method that forms the diffusion region, can effectively alleviate the surface damage of diffusion region.
For addressing the above problem, the invention provides a kind of formation method of diffusion region, comprising: form pre-doped layer at semiconductor substrate surface, have dopant ion in the described pre-doped layer; On described pre-doped layer, form protective layer; Described Semiconductor substrate is annealed, the dopant ion in the described pre-doped layer is diffused in the described Semiconductor substrate.
Dopant ion in the described pre-doped layer mixes when forming pre-doped layer.
The number of times that forms described pre-doped layer and described Semiconductor substrate is annealed is 1～3 time.
Dopant ion in the described pre-doped layer is an arsenic, and the reactant that forms described pre-doped layer is a tetraethoxysilane, and the impurity source in the described pre-doped layer is the arsenic triethyl acid esters.
Described annealing way is boiler tube mode or rapid thermal annealing mode.
The temperature of described annealing is 1050～1150 ℃.
The time of adopting the boiler tube mode to anneal is 10～60 minutes.
The time of adopting the rapid thermal annealing mode to anneal is 10～180 seconds.
Dopant ion in the described pre-doped layer is to inject by ion to form.
Described protective layer and pre-doped layer are silica, silicon nitride or silicon oxynitride.
Compared with prior art, such scheme has the following advantages: substitute former ion injection the carrying out doping of diffusion region by the boiler tube thermal diffusion process, avoided ion bombardment to damage that semiconductor substrate surface caused, it is more even that foreign ion is distributed, improve lattice structure, helped the carrying out of subsequent technique.In this process, technological process is slightly adjusted, but not obviously increase of complexity, production cost does not have obvious raising, to improving production capacity certain help is arranged.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, feature and advantage will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.The drafting of accompanying drawing focuses on illustrating purport of the present invention not painstakingly according to actual ratio.In the accompanying drawings, for cheer and bright, part layer and zone are carried out amplification.
Fig. 1 a to Fig. 1 e is the cross-sectional view that prior art forms n type buried layer;
Fig. 2 is the schematic flow sheet of method of the formation n type buried layer of one embodiment of the present of invention;
Fig. 3 to Fig. 7 is the cross-sectional view of the formation n type buried layer of one embodiment of the present of invention;
Fig. 8 is the schematic flow sheet that one embodiment of the present of invention form the method for n type buried layer.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Method provided by the invention is not only applicable to the formation of n type buried layer in the RAM device, is applicable to the formation of the diffusion region in other semiconductor device yet, for example: p type buried layer, well area, source-drain area etc.This with the RAM device in n type buried layer form example.
In theory, ion injection meeting causes damage to the Semiconductor substrate lattice, because it is relatively large to inject ion energy when the bombardment substrate surface, and the company's key between the lattice surface atom is not as substrate interior densification, the easier damage that causes the substrate surface state; And the silicon epitaxy step behind the n type buried layer is higher to the surface crystal quality requirement, small blemish can cause such as various problems such as lattice mismatches, the deterioration that all can cause the epitaxial loayer film quality, because epitaxial loayer is the main region that forms active device, epitaxial loayer film deterioration will certainly influence the semiconductor device overall performance.For guaranteeing the better quality of epitaxy technique, therefore must eliminate the blemish of n type buried layer as far as possible.
From prior art, all adopt ion implantation technique basically for the doping of n type buried layer, after injection, adopt annealing process to improve impaired lattice.The existing description of some shortcomings that preamble injects for ion, wherein topmost is exactly lattice damage.Comparatively speaking, thermal diffusion is mixed and is a comparatively gentle process, and is less to the influence of lattice; In addition, consider that than the one chip production that ion injects, diffusion is normally carried out, and once can handle several and even tens silicon chips, significantly improves production capacity thus, has reduced production cost in boiler tube from the production capacity aspect.Therefore, change to the thermal diffusion doping, both made moderate progress technically if the n type buried layer doping techniques can be injected by ion, favourable to actual production again.
Fig. 2 has provided the schematic flow sheet of method of the formation n type buried layer of one embodiment of the present of invention, comprising: step S210, form pre-doped layer at semiconductor substrate surface, and have dopant ion in the described pre-doped layer; Step S220 forms protective layer on described pre-doped layer; Step S230 anneals to described Semiconductor substrate, and the dopant ion in the described pre-doped layer is diffused in the described Semiconductor substrate.
Method provided by the invention is applicable to the diffusion region that forms in the semiconductor device, for example formation of n type buried layer in the RAM device.
Fig. 3 to Fig. 7 is the cross-sectional view of the formation n type buried layer of one embodiment of the present of invention, and described schematic diagram is an example, should excessively not limit the scope of protection of the invention at this.
With reference to Fig. 3, Semiconductor substrate 300 at first is provided and it is cleaned.Described Semiconductor substrate 300 can be a monocrystalline silicon, also can be silicon-on-insulator (SOI), perhaps can also comprise other material, III-V compounds of group such as GaAs for example, and described Semiconductor substrate 300 has the lattice structure of rule.In the present embodiment, Semiconductor substrate 300 is the silicon substrate of lightly doped P type, and resistivity is 8～11.5 Ω cm, and the crystal orientation is＜100 〉.
Described Semiconductor substrate 300 is divided into buried regions district and non-buried regions district, and as shown in phantom in FIG., wherein the I district is the buried regions district, and the II district is non-buried regions district.
Then, form the pre-doped layer 310 of one deck on described Semiconductor substrate 300 surfaces, described pre-doped layer 310 can be silica, silicon nitride, silicon oxynitride, present embodiment is a silica, its formation method can be the boiler tube thermal oxidation, low-pressure chemical vapor phase deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD) technology, present embodiment adopts low-pressure chemical vapor phase deposition technology.The dopant ion type of described pre-doped layer 310 determines that by technological requirement to the n type buried layer of present embodiment, dopant ion can be selected arsenic for use at this for phosphorus, arsenic, tellurium.
The primary raw material that forms pre-doped layer 310 is TEOS, and Chinese positive silicic acid second by name is joined or tetraethoxy-silicane, and its molecular formula can be write Si (OC
2H
5)
4, low pressure thermal decomposition TEOS is the common method of the pre-doped layer of middle temperature deposit.The TEOS source is liquid at normal temperatures, with nitrogen (N
2) TEOS is pressed in the liquid source controller vaporizes, via utilidor input reaction boiler tube, reaction pressure be 13～650Pa (0.1～5.0Torr), be 80Pa (0.6Torr) in the present embodiment; Reaction temperature is 550～750 ℃, is preferably 650 ℃ at this; The TEOS flow is 5～35sccm, is preferably 20sccm.Pre-doped layer 310 thickness according to the actual requirements, can for
Select for use in the present embodiment
The TEOS branch solves an equation as follows:
Si(OC
2H
5)
4→SiO
2+C
2H
4+H
2O
Utilize TEOS to form pre-doped layer 310, have film thickness uniformity and repeatability preferably, and cost is lower than other modes, speed exists
/ minute, meet the production demand and in controlled range.TEOS forms pre-doped layer and also has step coverage preferably, and is particularly evident under the situation of mixing.When utilizing TEOS to form pre-doped layer, can mix as the phosphorus source with materials such as phosphine, trimethyl phosphate, phosphorus oxychloride, form PSG, can also add the boron source doping, form BSG, or adopt multiple material to mix formation simultaneously as BPSG.After doping, the ledge surface flatness is further improved.
As one preferred, for formation contains the pre-doped layer (ASG) 310 of arsenic, the dopant ions in the described pre-doped layer 310 mix when forming pre-doped layer.Such as, when forming pre-doped layer 310, add the arsenic source and mix.TEASAT is selected in described arsenic source for use, Chinese arsenic triethyl acid esters by name, molecular formula writing (C
2H
5O)
3For liquid, the steel cylinder temperature that stores TEASAT is 50 ℃, passes through N down for AsO, normal temperature
2Vaporization input chamber, reaction temperature is 550～750 ℃, can be 560 ℃, 580 ℃, 600 ℃, 630 ℃, 650 ℃, 680 ℃, 720 ℃, is preferably 650 ℃ at this, the TEASAT flow depends on steel cylinder temperature and N
2Flow.At this, the steel cylinder temperature is 50 ℃, N
2Flow is 20sccm.Reaction equation is as follows:
(C
2H
5O)
3AsO+O
2→As
2O
5+CO
2+H
2O
The result shows that the pre-doped layer (ASG) 310 that contains arsenic that utilizes above-mentioned low-pressure chemical vapor phase deposition technology to form has good step coverage, and technology is comparatively simple, only needs to add when the TEOS deposit doping that an amount of TEASAT can realize arsenic.In addition, the quality of mixing pre-doped layer of arsenic does not cause tangible influence.
With reference to Fig. 4, after the pre-doped layer (ASG) 310 that contains arsenic formed, full sheet need carry out graphically described pre-doped layer 310 because n type buried layer is present in the specific region of Semiconductor substrate.Specifically comprise, form the photoresist (not shown), go out the n type buried layer zone, utilize wet etching to remove the pre-doped layer 310 in non-n type buried layer zone then, form patterned pre-doped layer 310 ' by lithographic definition; Used etching solution can be selected hydrofluoric acid for use, and concentration is 2% (NH
4F: HF: H
2O=10: 2: 88).Wet etching is finished and is removed photoresist again, only has patterned pre-doped layer 310 ' above the n type buried layer zone.
With reference to Fig. 5, form pre-doped layer 310 ' after, on Semiconductor substrate 300, form layer protective layer (cap layer) 320 with TEOS, described protective layer 320 can be selected silica for use at this for silica, silicon nitride, silicon oxynitride; Described protective layer 320 covers n type buried layer zone and non-n type buried layer zone simultaneously.The formation method is selected the normal pressure chemical vapor deposition for use at this as previously mentioned, and thickness is
Select for use in one embodiment
Because As has stronger toxicity, the effect of this protective layer is to be limited in the As in the pre-doped layer 310 ' in the subsequent technique
+To diffusion into the surface, even pollute chamber, therefore forming protective layer 320 can play corresponding protective action.
With reference to Fig. 6, in boiler tube, carry out annealing process, purpose is to make the As in the pre-doped layer 310 '
+To Semiconductor substrate 300 diffusions, reach the purpose that Semiconductor substrate 300 is mixed, finally form n type buried layer 330.Annealing is carried out in inert gas or nitrogen atmosphere, and described inert gas can be selected gases such as argon gas, helium for use.In the present embodiment, select nitrogen (N for use
2).Annealing temperature is 1050～1150 ℃, can be 1050 ℃, 1080 ℃, 1100 ℃, 1130 ℃, 1150 ℃, selects 1150 ℃ for use at this.Annealing temperature is high more, As
+Diffusion depth dark more.Annealing way has boiler tube mode of heating, rapid thermal annealing (RTP) etc., selects the boiler tube mode of heating for use at this; Annealing time is 10～60 minutes, can be 10 minutes, 20 minutes, 40 minutes, 60 minutes, selects for use 10 minutes at this.For rapid thermal annealing, annealing time is 10～180 seconds.Annealing time is long more, As
+The amount of diffusion is big more.In the annealing process, the As in the pre-doped layer 310 '
+Because the concentration gradient effect is diffused in the Semiconductor substrate 300, the energy that particle obtained simultaneously can be recombinated it to the lattice structure of substrate 300, eliminates or the minimizing defective, forms the comparatively lattice of rule, helps the growth of follow-up epitaxial loayer.As a specific embodiment, annealing temperature is 1150 ℃, and annealing time is 10 minutes, and corresponding Rs result is 140 Ω/, and recording diffusion depth is 0.7 μ m.In another embodiment, annealing temperature is 1050 ℃, and annealing time is 60 minutes, and corresponding Rs result is 250 Ω/, and recording diffusion depth is 0.3 μ m.Annealing process can require to carry out 1～2 time according to resistance.
With reference to Fig. 7, after the annealing thermal diffusion process is finished, in Semiconductor substrate 300 ', formed n type buried layer 330, need to remove each layer film on the Semiconductor substrate 300 ' then, comprise protective layer 320 and patterned pre-doped layer 310 '.Described removal 320 and 310 ' method are the wet etching mode, and used etching solution can be selected hydrofluoric acid for use, and concentration is 2% (NH
4F: HF: H
2O=10: 2: 88).This process comprises certain over etching usually, and the time was controlled at 5～10 minutes, and present embodiment was selected for use 5 minutes.After wet etching is finished, form Semiconductor substrate structure as shown in Figure 7, can utilize this Semiconductor substrate 300 ' to carry out the extension of full sheet p type single crystal silicon thereafter.
For characterizing the doping situation in buried regions zone, utilize four probe method to measure the square resistance of gained n type buried layer, recording Rs result in the present embodiment is 140 Ω/, recording diffusion depth is 0.7 μ m.The above is a first embodiment of the present invention content.
Because the restriction of TEASAT saturated vapor pressure and the toxicity of this material, for security consideration, As is in below the doses in the pre-doped layer 310 ', the As content that diffuses to thus in the Semiconductor substrate 300 also is restricted, thereby cause formed n type buried layer doping rate on the low side, resistivity is higher.In this case, often need to reach corresponding resistivity requirement by repeatedly spreading.The flow process of second embodiment of the invention can contain the pre-doped layer of arsenic and carry out the doping that thermal diffusion realizes n type buried layer As higher concentration as shown in Figure 8 by twice formation.
Specifically comprise: execution in step S210, form the first pre-doped layer at semiconductor substrate surface, have dopant ion in the described first pre-doped layer; Execution in step S220 forms first protective layer on the described first pre-doped layer; Execution in step S230 anneals to described Semiconductor substrate, and the dopant ion in the described first pre-doped layer is diffused in the described Semiconductor substrate; Execution in step S240 removes the described first pre-doped layer and first protective layer; Execution in step S250, repeating said steps S210 to S230 reaches predetermined purpose until the resistivity of the buried regions that forms or the concentration of foreign ion in Semiconductor substrate.
Describedly form the first pre-doped layer, formation first protective layer and the step that described Semiconductor substrate is annealed be please refer to the associated description of the foregoing description, do not add at this and give unnecessary details at semiconductor substrate surface.
As a specific embodiment, form the first pre-doped layer that contains arsenic at semiconductor substrate surface, thickness is preferably
Graphical described pre-doped layer; Form first protective layer then on the first pre-doped layer, thickness is
The thermal diffusion process of annealing afterwards, annealing temperature is 1050 ℃, the time is 60 minutes; Then wet method is removed described first protective layer and the remaining first pre-doped layer, and the measurement square resistance is 241 Ω/.For further reducing resistivity, carry out the thermal diffusion second time, with for the first time similar, form
The second pre-doped layer; the graphical described second pre-doped layer also forms second protective layer, and the described second pre-doped layer is carried out the boiler tube annealing operation, and temperature is 1050 ℃; time is 60 minutes, and removing and recording square resistance behind described second protective layer and the remaining second pre-doped layer is 116 Ω/.
Above-mentionedly form the first pre-doped layer, form first protective layer and the described pre-doped layer of step that described Semiconductor substrate is annealed is reached the number of times that described Semiconductor substrate is annealed and be respectively twice at semiconductor substrate surface; in fact can also be by more times number; such as by 1～3 time, should too not limit protection scope of the present invention at this.
In addition, the dopant ion in the described pre-doped layer mixes for injecting by ion.Such as, the ion that described pre-doped layer is carried out arsenic injects, control the ion pair Semiconductor substrate that energy, dosage that the thickness of pre-doped layer and ion inject avoids injecting and cause damage, by pre-doped layer is annealed the ions diffusion in the pre-doped layer is gone in the Semiconductor substrate then, this method and above-mentioned method of mixing foreign ion when forming pre-doped layer are basic identical, do not repeat them here.
In the present invention, mode, the temperature and time of the thickness of pre-doped layer, the concentration of dopant ion, annealing thermal diffusion all are the key factors that influences the gained diffused layer resistance, can select flexibly according to the actual requirements.In practice, square resistance wider range of the n type buried layer that obtains, between 100～600 Ω/, corresponding diffusion depth is 0.01～10 μ m, and is suitable with the square resistance scope of prior art gained, visible the present invention can satisfy the process requirements of relative broad range.
The present invention adopts the thermal diffusion mode to replace original ion to inject and carries out the doping of diffusion region by changing technological process, has improved the lattice surface structure, can adapt to the process requirements of broad electrical resistivity range.
Though the present invention with preferred embodiment openly as above; but be not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (10)
1. the formation method of a diffusion region is characterized in that, comprising:
Form pre-doped layer at semiconductor substrate surface, have dopant ion in the described pre-doped layer;
On described pre-doped layer, form protective layer;
Described Semiconductor substrate is annealed, the dopant ion in the described pre-doped layer is diffused in the described Semiconductor substrate.
2. according to the formation method of the described diffusion region of claim 1, it is characterized in that the dopant ion in the described pre-doped layer mixes when forming pre-doped layer.
3. according to the formation method of the described diffusion region of claim 2, it is characterized in that forming described pre-doped layer and number of times that described Semiconductor substrate is annealed is 1～3 time.
4. according to the formation method of the described diffusion region of claim 3, it is characterized in that the dopant ion in the described pre-doped layer is an arsenic, the reactant that forms described pre-doped layer is a tetraethoxysilane, and the impurity source in the described pre-doped layer is the arsenic triethyl acid esters.
5. according to the formation method of the described diffusion region of claim 4, it is characterized in that described annealing way is boiler tube mode or rapid thermal annealing mode.
6. according to the formation method of the described diffusion region of claim 7, it is characterized in that the temperature of described annealing is 1050～1150 ℃.
7. according to the formation method of the described diffusion region of claim 6, it is characterized in that the time of adopting the boiler tube mode to anneal is 10～60 minutes.
8. according to the formation method of the described diffusion region of claim 5, it is characterized in that the time of adopting the rapid thermal annealing mode to anneal is 10～180 seconds.
9. according to the formation method of the described diffusion region of claim 1, it is characterized in that the dopant ion in the described pre-doped layer is to inject by ion to form.
10. according to the formation method of the described protective layer of claim 1, it is characterized in that described protective layer and pre-doped layer are silica, silicon nitride or silicon oxynitride.
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Application publication date: 20110413 |