CN103972064A - Technique for inhibiting self doping of P-type impurities in epitaxial process of silicon with P-type buried layer - Google Patents
Technique for inhibiting self doping of P-type impurities in epitaxial process of silicon with P-type buried layer Download PDFInfo
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- CN103972064A CN103972064A CN201410225224.2A CN201410225224A CN103972064A CN 103972064 A CN103972064 A CN 103972064A CN 201410225224 A CN201410225224 A CN 201410225224A CN 103972064 A CN103972064 A CN 103972064A
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 54
- 239000010703 silicon Substances 0.000 title claims abstract description 54
- 239000012535 impurity Substances 0.000 title claims abstract description 28
- 230000002401 inhibitory effect Effects 0.000 title abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 52
- 230000006837 decompression Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000000407 epitaxy Methods 0.000 claims description 33
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 31
- 229910052796 boron Inorganic materials 0.000 claims description 31
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 230000003321 amplification Effects 0.000 abstract description 5
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000005429 filling process Methods 0.000 abstract 1
- 238000009826 distribution Methods 0.000 description 8
- 238000003892 spreading Methods 0.000 description 7
- 238000005457 optimization Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000035568 catharsis Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention provides a technique for inhibiting self doping of P-type impurities in an epitaxial process of silicon with a P-type buried layer. The technique comprises the following steps: providing a silicon wafer which is used as a substrate for manufacturing a semiconductor element, forming the P-type buried layer and an N-type buried layer on the surface of the silicon wafer through a filling process, and baking the silicon wafer at low temperature and under normal pressure; etching the silicon wafer at low temperature and under normal pressure, and removing damaged parts, which are generated when the P-type buried layer and the N-type buried layer are formed before, from the surface of the silicon wafer; forming a layer of intrinsic top cover layer on the surface of the silicon wafer under normal pressure; and growing an epitaxial layer on the surface of the top cover layer in a decompression environment. The technique provided by the invention can be used for inhibiting the self doping of the P-type impurities in an N-type silicon extension process with regard to a product of which the P-type impurities in the P-type buried layer are too high in concentration, so that the amplification coefficient of an element such as a horizontal PNP (Positive-Negative-Positive) tube can be increased.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, specifically, the present invention relates to suppress in a kind of silicon epitaxy process with p type buried layer the technique of p type impurity autodoping.
Background technology
In ambipolar (Bipolar) integrated circuit technology for example; conventionally can extension (Epitaxy) front on substrate pre-buried certain density boron buried regions (claim again BP buried regions; a kind of p type buried layer), for device plays logical isolation or participates in making device.In reduced pressure epitaxy process, because boron atom (p type impurity) radius is little, very easily from BP buried regions, overflow, form serious boron autodoping effect, and then cause the amplification coefficient (amplifying β) of the lateral PNP pipe of phosphorus buried regions (claiming again BN buried regions, the is a kind of n type buried layer) top on side to be difficult to do height.
In order to suppress the autodoping of boron atom in epitaxial process, current N-type epitaxy technique is all to adopt before extension, on substrate, to increase (intrinsic) cap layer (claiming again CAP layer) that forms one deck intrinsic, cover on this BP buried regions, suppress the effusion of boron atom.
Fig. 1 is the schematic flow sheet that suppresses the epitaxy method of boron autodoping in a kind of silicon epitaxy process process with boron buried regions of the prior art.As shown in Figure 1, the technological process of current routine can be described below:
First perform step S101, silicon chip is provided, as the substrate of making semiconductor device, the surface of silicon chip is injected and is formed with BP buried regions and BN buried regions, and silicon chip is toasted under the environment of high temperature and normal pressure.This high temperature can refer to 1150 DEG C, and this normal pressure can refer to standard atmospheric pressure.
Then perform step S102, silicon chip made to etching under the environment of high temperature and normal pressure, remove silicon chip surface because of before the damage that causes while forming BP buried regions and/or BN buried regions.The concept of this high temperature and this normal pressure is identical with above-mentioned steps S101, and high temperature can refer to 1150 DEG C, and normal pressure can refer to standard atmospheric pressure.
Then perform step S103, under the environment of decompression, form the cap layer of one deck intrinsic in silicon chip surface.This decompression can refer to 45 holders (torr).
Finally perform step S104, under the environment of decompression at the superficial growth epitaxial loayer of cap layer.The concept of this decompression is identical with above-mentioned steps S103, i.e. this decompression can refer to 45 holders.
But in the time of the boron excessive concentration of BP buried regions, conventional epitaxy technique just can not suppress the autodoping of boron effectively, thereby allows boron atom gather the top of BN layer, causes device to substrate leakage.For this reason, need to develop a kind of new epitaxy technique.
Summary of the invention
Technical problem to be solved by this invention is to provide the technique that suppresses p type impurity autodoping in a kind of silicon epitaxy process with p type buried layer, for the product of p type impurity excessive concentration in p type buried layer, in the process of N-type silicon epitaxy process, suppress the autodoping problem of p type impurity, improve device as the amplification coefficient of lateral PNP pipe.
For solving the problems of the technologies described above, the invention provides the technique that suppresses p type impurity autodoping in a kind of silicon epitaxy process with p type buried layer, comprise step:
A., silicon chip is provided, and as the substrate of making semiconductor device, the surface of described silicon chip is injected and is formed with p type buried layer and n type buried layer, and described silicon chip is toasted under the environment of low temperature and normal pressure;
B. described silicon chip is made to etching under the environment of low temperature and normal pressure, the surface of removing described silicon chip because of before the damage that causes while forming described p type buried layer and described n type buried layer;
C. under the environment of normal pressure, form the cap layer of one deck intrinsic in the surface of described silicon chip; And
D. decompression environment under in the superficial growth epitaxial loayer of described cap layer.
Alternatively, in above-mentioned steps A and step B, described low temperature refers to that temperature is 1080～1120 DEG C.
Alternatively, in above-mentioned steps A, step B and step C, described normal pressure refers to that air pressure is standard atmospheric pressure.
Alternatively, in above-mentioned steps D, described decompression refers to that air pressure is 45～60 holders (torr).
Alternatively, described p type buried layer refers to boron buried regions, and described p type impurity refers to boron atom; Described n type buried layer refers to antimony buried regions.
Alternatively, described silicon chip is the doping of P type, and its resistivity is 35～40Ohmcm.
Compared with prior art, the present invention has the following advantages:
The all processing steps of the present invention can be realized in a monolithic epitaxial furnace, by reducing the temperature of silicon chip baking and etching, have effectively reduced the escaped quantity of p type impurity.In addition, the pressure pattern that forms cap layer also changes normal pressure into from decompression, strengthen the catharsis of epitaxy technique cavity to p type impurity, made to accumulate in the p type impurity discharge epitaxy technique cavity in non-p type buried layer region before epitaxial growth, thereby more effectively suppressed the autodoping of p type impurity.
The present invention is through the optimization to epitaxy technique, the amplification coefficient (amplify β) of the lateral PNP pipe of the n type buried layer top of bipolar integrated circuit product under the measuring current of 50 μ A rises to 40 left and right from 20 left and right, confirmed that the present invention is very effective.
Brief description of the drawings
The above and other features of the present invention, character and advantage are by by becoming more obvious below in conjunction with the description of drawings and Examples, wherein:
Fig. 1 is the schematic flow sheet that suppresses the epitaxy method of boron autodoping in a kind of silicon epitaxy process process with boron buried regions of the prior art;
Fig. 2 is the process flow diagram that suppresses p type impurity autodoping in the silicon epitaxy process process with p type buried layer of one embodiment of the invention;
Fig. 3 is after the epitaxy method that suppresses boron autodoping in the silicon epitaxy process process with boron buried regions of one embodiment of the invention is implemented, the analysis position schematic diagram of the spreading resistance rate distribution map (SRP) to pure epitaxial region;
Fig. 4 is after the epitaxy method that suppresses boron autodoping in the silicon epitaxy process process with boron buried regions of one embodiment of the invention is implemented, and the correlation curve figure of spreading resistance rate distribution map (SRP) between prior art.
Embodiment
Below in conjunction with specific embodiments and the drawings, the invention will be further described; set forth in the following description more details so that fully understand the present invention; but the present invention obviously can implement with the multiple alternate manner that is different from this description; those skilled in the art can do similar popularization, deduction according to practical situations without prejudice to intension of the present invention in the situation that, therefore should be with content constraints protection scope of the present invention of this specific embodiment.
Fig. 2 is the process flow diagram that suppresses p type impurity autodoping in the silicon epitaxy process process with p type buried layer of one embodiment of the invention.As shown in Figure 2, this technological process mainly comprises:
Execution step S201, provides silicon chip, as the substrate (P-type substrate) of making semiconductor device.This silicon chip is generally P type doping, its resistivity can be 35～40Ohm.cm (ohm. centimetre).Inject and be formed with p type buried layer and n type buried layer on the surface of silicon chip, this p type buried layer can be boron buried regions, and this p type impurity can be boron atom; And this n type buried layer can be antimony buried regions.Then silicon chip is toasted under the environment of low temperature and normal pressure.In the present embodiment, this low temperature refers to certain numerical value that temperature can be between 1080～1120 DEG C, for example 1080 DEG C, 1090 DEG C, 1100 DEG C, 1110 DEG C or 1120 DEG C, is preferably 1100 DEG C; This normal pressure refers to that air pressure can be standard atmospheric pressure.
Execution step S202 makes etching by silicon chip under the environment of low temperature and normal pressure, the surface of removing silicon chip because of before the damage that causes while forming p type buried layer and n type buried layer.In this step, the implication of this low temperature and this normal pressure is identical with above-mentioned steps S201, this low temperature refers to that temperature can be certain numerical value between 1080～1120 DEG C,, is preferably 1100 DEG C by for example 1080 DEG C, 1090 DEG C, 1100 DEG C, 1110 DEG C or 1120 DEG C; And this normal pressure refers to that air pressure can be standard atmospheric pressure.
Perform step S203, under the environment of normal pressure, form the cap layer (CAP layer) of one deck intrinsic in the surface of silicon chip.In this step, the implication of this normal pressure is identical with above-mentioned steps S201, S202, and this normal pressure refers to that air pressure can be standard atmospheric pressure.
Execution step S204, decompression environment under in the superficial growth epitaxial loayer (being generally N-type epitaxial loayer) of cap layer.In the present embodiment, this decompression refers to that air pressure can be certain numerical value between 45～60 holders (torr), for example 45 holders, 50 holders, 55 holders or 60 holders.
Fig. 3 is after the epitaxy method that suppresses boron (p type impurity) autodoping in the silicon epitaxy process process with boron buried regions (p type buried layer) of one embodiment of the invention is implemented, the analysis position schematic diagram of the spreading resistance rate distribution map (SRP) to pure epitaxial region.Fig. 4 is after the epitaxy method that suppresses boron (p type impurity) autodoping in the silicon epitaxy process process with boron buried regions (p type buried layer) of one embodiment of the invention is implemented, and the correlation curve figure of spreading resistance rate distribution map (SRP) between prior art.It should be noted that these accompanying drawings are all only as example, it is not to draw according to the condition of equal proportion, and should not be construed as limiting as the protection range to actual requirement of the present invention using this.
Shown in Fig. 3 and Fig. 4, after the optimization of epitaxy technique of the present invention, the spreading resistance rate distribution map (SRP of (being the region of epitaxial loayer below without BP buried regions and BN buried regions) from the pure epitaxial region to epitaxial wafer, Spreading Resistivity Profile), after optimizing effective epitaxial thickness of (the present invention) epitaxial loayer optimize before (prior art) increased approximately 2.7 microns, autodoping effect after PN junction disappears, as shown in Figure 4.
Specifically, it (is that resistivity diminishes rapidly that the spreading resistance rate distribution curve of the prior art before optimization has obvious recessed phenomenon after the position of PN joint, illustrate that conductive capability increases), this is because the boron in BP buried regions (p type impurity) is before epitaxial growth, from BP buried regions, overflow and accumulate in non-BP buried regions region, after epitaxial growth this part boron just by double team between epitaxial loayer and substrate.Because substrate (silicon chip) is generally P type (35～40 ohmcm), thereby cause the recessed of distribution curve.Along with high temperature epitaxy carries out, this part boron, to outdiffusion, further causes epitaxial loayer effective thickness to reduce (as the concave region in Fig. 4).
The present invention after optimization is because the temperature of hydrogen chloride (HCL) gas etching silicon chip reduces, make the escaped quantity of boron reduce (being difficult for running out of), add normal pressure and form the catharsis of cap layer to process cavity, make the boron that accumulates in non-BP buried regions region before extension discharge extension cavity, it is comparatively mild that thereby distribution curve becomes, and eliminated recessed phenomenon.
In sum, all processing steps of the present invention can be realized in a monolithic epitaxial furnace, by reducing the temperature of silicon chip baking and etching, have effectively reduced the escaped quantity of p type impurity.In addition, the air pressure pattern that forms cap layer also changes normal pressure into from decompression, strengthen the catharsis of epitaxy technique cavity to p type impurity, made to accumulate in the p type impurity discharge epitaxy technique cavity in non-p type buried layer region before epitaxial growth, thereby more effectively suppressed the autodoping of p type impurity.
The present invention is through the optimization to epitaxy technique, the amplification coefficient (amplify β) of the lateral PNP pipe of the n type buried layer top of bipolar integrated circuit product under the measuring current of 50 μ A rises to 40 left and right from 20 left and right, confirmed that the present invention is very effective.
Although the present invention with preferred embodiment openly as above, it is not for limiting the present invention, and any those skilled in the art without departing from the spirit and scope of the present invention, can make possible variation and amendment.Therefore, every content that does not depart from technical solution of the present invention, any amendment, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, within all falling into the protection range that the claims in the present invention define.
Claims (6)
1. there is a technique that suppresses p type impurity autodoping in the silicon epitaxy process of p type buried layer, comprise step:
A., silicon chip is provided, and as the substrate of making semiconductor device, the surface of described silicon chip is injected and is formed with p type buried layer and n type buried layer, and described silicon chip is toasted under the environment of low temperature and normal pressure;
B. described silicon chip is made to etching under the environment of low temperature and normal pressure, the surface of removing described silicon chip because of before the damage that causes while forming described p type buried layer and described n type buried layer;
C. under the environment of normal pressure, form the cap layer of one deck intrinsic in the surface of described silicon chip; And
D. decompression environment under in the superficial growth epitaxial loayer of described cap layer.
2. technique according to claim 1, is characterized in that, in above-mentioned steps A and step B, described low temperature refers to that temperature is 1080～1120 DEG C.
3. technique according to claim 2, is characterized in that, in above-mentioned steps A, step B and step C, described normal pressure refers to that air pressure is standard atmospheric pressure.
4. technique according to claim 3, is characterized in that, in above-mentioned steps D, described decompression refers to that air pressure is 45～60 holders.
5. technique according to claim 4, is characterized in that, described p type buried layer refers to boron buried regions, and described p type impurity refers to boron atom; Described n type buried layer refers to antimony buried regions.
6. technique according to claim 5, is characterized in that, described silicon chip is the doping of P type, and its resistivity is 35～40Ohm.cm.
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