CN204029812U - A kind of Semiconductor substrate with self compensation back of the body sealing - Google Patents
A kind of Semiconductor substrate with self compensation back of the body sealing Download PDFInfo
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- CN204029812U CN204029812U CN201420390642.2U CN201420390642U CN204029812U CN 204029812 U CN204029812 U CN 204029812U CN 201420390642 U CN201420390642 U CN 201420390642U CN 204029812 U CN204029812 U CN 204029812U
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- 239000000758 substrate Substances 0.000 title claims abstract description 108
- 238000007789 sealing Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 49
- 230000012010 growth Effects 0.000 abstract description 24
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 22
- 230000000694 effects Effects 0.000 abstract description 13
- 230000000873 masking effect Effects 0.000 description 21
- 239000012535 impurity Substances 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 9
- 238000000407 epitaxy Methods 0.000 description 9
- 239000007788 liquid Substances 0.000 description 7
- 230000007797 corrosion Effects 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052787 antimony Inorganic materials 0.000 description 5
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000003698 anagen phase Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004587 chromatography analysis Methods 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
The utility model discloses a kind of Semiconductor substrate with self compensation back of the body sealing.This substrate comprises: the substrate with the first conduction type of the first doping content; Be positioned at the layer of compensation on the lower surface of described substrate and sidewall with the second conduction type of the second doping content, the second conduction type is different from the first conduction type; Be positioned at the outer silicon oxide layer that covers described substrate lower surface and at least part of sidewall of described layer of compensation; With the intrinsic polysilicon layer being positioned at outside described silicon oxide layer.Solve back side autodoping effect and edge effect causes light dope extension atmosphere transoid according to Semiconductor substrate of the present utility model, thereby caused sheet inward flange or full wafer to grow into the problem of homotype extension.Adopt self compensation back of the body envelope technique of the present utility model, even with the full stove growth of normal pressure epitaxial furnace, still can ensure that extension parameter meets product requirement.
Description
Technical field
The utility model relates to semiconductor microelectronic technology field, and specifically, the utility model relates to silicon-based semiconductor devices and integrated circuit.
Background technology
Along with the development of silicon-based semiconductor technology, the kind of the semiconductor device such as discrete device, integrated circuit (IC) chip and MOS device with specific function is more and more.The requirement of the thickness of all kinds of devices to substrate and epitaxial loayer and concentration is more and more higher.For example some particular device need to be less than on the P type of 0.01 Ω cm or N-type substrate and process light dope transoid epitaxial loayer in for example resistivity of heavy doping substrate.As everyone knows, identical conduction type epitaxial loayer high in heavy doping Grown resistivity and good uniformity acquires a certain degree of difficulty, if the epitaxial loayer of growth phase opposite conduction type, its difficulty is higher.If now use conventional normal pressure extension manufacture method, high temperature when epitaxial growth can make the active foreign ion in heavy doping substrate, as boron, phosphorus, escape into lightly doped epitaxial growth atmosphere from lower surface and the sidewall of this substrate, the foreign ion of escaping out can cause the abnormal transoid of the even overall epitaxial growth atmosphere in part, also certainly will cause grown epitaxial layer quality out of control, finally cause the decline of rate of finished products and the performance of device.For example, Fig. 1 illustrates that under prior art, carrying out antimony on heavy doping P type substrate injects after buried regions, uses the SRP test curve of normal pressure epitaxy technique growth light dope N-type epitaxial loayer, affected by autodoping effect, and light dope N-type epitaxial loayer completely transoid becomes P type.
In the situation that growing light dope epitaxial loayer by normal pressure extension, if both counterweight doped substrate sheet did not do any processing, do not use again special epitaxy technique, even monolithic processing, the edge effect of above-mentioned autodoping effect and substrate will cause extension atmosphere out of control and and then cause grown epitaxial layer quality out of control.The impurity transoid that the outer time delay of growth light dope transoid even there will be extension atmosphere to be separated out by substrate, causes edges of substrate or whole substrate to grow into the situation of homotype extension.
Those skilled in the art conventionally can only adopt the substrate of torpescence dopant type or adopt complicated epitaxial growth method to solve the problems referred to above.The substrate of torpescence dopant type, N-type can be selected antimony substrate (Sb-Sub), but its resistivity is generally difficult to accomplish to be less than 0.01 Ω cm, cannot meet the requirement of part of devices to resistance substrate rate.P type impurity does not almost have selectable leeway, can only use boron (B).Because boron (B) belongs to active dopant type, in the time using boron substrate (B-Sub), extremely difficult control of above-mentioned auto-doping phenomenon.
More known complicated epitaxy methods, comprise that the method as led in advance technique and bag silicon gettering process etc. solves above-mentioned technical problem.Below taking at P type heavy doping Grown N-type light dope epitaxial loayer as example, specifically describe existing epitaxial growth method.
In the time that extension chamber of the reactor temperature reaches 1000～1150 DEG C, passing into flow is the HCl gas of 10～30L/min, and chamber and pedestal are carried out to gas attack, to reduce the concentration of gas attack impurity in epitaxial reactor.Get rid of after this gas attack reacting gas the intrinsic silicon layer of deposit 1～10 μ m on reaction chamber and pedestal.This intrinsic silicon layer is by for being absorbed in the high concentration impurities ion that epitaxial process is separated out from substrate subsequently.Subsequently by surface and marginal growth first epitaxial thin layer of P type heavy doping substrate, that this first epitaxial thin layer is intrinsic or be the high concentration epitaxial loayer consistent with the epitaxial loayer of N-type, substrate surface and edge are sealed.The growth temperature of controlling this first thin layer is that 1100～1150 DEG C, growth rate are 0.5～2 μ m/min, to reaching the desirable effect of sealing.The second epitaxial loayer of the N-type of can growing on the first epitaxial thin layer obtaining subsequently obtains light dope transoid epitaxial loayer, completes the making of epitaxial loayer.Above-mentioned process is because comprised corrosion to reaction chamber and deposition of intrinsic silicon layer and growth the first epitaxial thin layer and very complicated, and may in the structure obtaining, introduce " Spike " fleck defect, affect epitaxial quality, be difficult to realize in batches growth continuously.
Because above-mentioned reason, those skilled in the art generally abandon using normal pressure epitaxial growth method, and adopt monolithic decompression vapour epitaxial furnace to grow.In reduced pressure epitaxy growth, in order to make to become environment under low pressure in reative cell, employing utilizes the indoor gas of vacuum pump abstraction reaction of oil diffusion pump, and reduced pressure epitaxy stove once can only process a slice, thereby this method exists the problem that equipment cost is high, efficiency is low and technological parameter is restive.
Therefore, need a kind of preparation technology simple, can volume production, obtain cheaply the Semiconductor substrate of high-quality epitaxial loayer.
Utility model content
The purpose of this utility model is to provide a kind of substrate with self compensation back of the body sealing, causes light dope extension atmosphere transoid, thereby cause sheet inward flange or full wafer substrate to grow into the problem of homotype epitaxial loayer to solve substrate back autodoping effect and edge effect.
For solving the problems of the technologies described above, the utility model adopts following technical proposals:
In the substrate process segment, on substrate, before epitaxial growth epitaxial loayer, make self compensation back of the body sealing at substrate surface.
Preferably, use the process of diffusion furnace thermal oxidation thering is the heavily-doped semiconductor substrate surface of the first conduction type, comprise the oxide of front, the back side, sidewall growth uniform thickness.Those skilled in the art can be according to specific needs, selects that substrate is carried out to initial oxidation and obtain the method for oxide or utilize the oxide skin(coating) generating process buried regions district after annealing on heavy doping substrate time, and this oxide skin(coating) is using the masking layer when making layer of compensation.
Preferably, the thickness range of described oxide skin(coating) should be
Preferably, use photoresist masking just in the face of the semiconductor chip that is coated with oxide skin(coating) carries out wet etching erosion, obtain substrate upper surface and be coated with the substrate structure of oxide.
Preferably, use proportioning HF acid or BOE corrosive liquid wet method to remove the oxide layer that is positioned at substrate lower surface and sidewall.
Preferably, after corrosion step, photoresist masking layer is peeled off.
Preferably, using the oxide skin(coating) that is positioned at substrate upper surface as mask, use sidewall and the lower surface of diffusion furnace counterweight doped substrate to carry out the second conduction type doping.
Preferably, use diffusion furnace to anneal at 900～1100 DEG C to the second conductive type impurity, to form layer of compensation, the certain thickness oxide skin(coating) of simultaneously growing at sidewall and the back side.
Preferably, this layer of compensation doping content should be a little more than the doping content of heavy doping substrate, with the second conductive type impurity concentration of ensureing to separate out on a small quantity in epitaxial process higher than the first conductive type impurity concentration.Preferably, semiconductor chip is that resistivity is the heavily doped silicon chip of P type of 0.004-0.006 Ω cm, and its doping content is about 2 × 10
19cm
-3, selected N-type layer of compensation concentration should be greater than 2 × 10
19cm
-3.
Preferably, described oxide skin(coating) is used as oxide masking layer, and its thickness range is preferably
Preferably, use low-pressure chemical vapor phase deposition LPCVD technique on oxide masking layer surface, comprise the intrinsic polysilicon masking layer of upper surface, lower surface and sidewall growth uniform thickness.
Preferably, the thickness range of described intrinsic polysilicon masking layer is
Preferably, use dry plasma etch technique to remove described intrinsic polysilicon layer.
Preferably, use proportioning HF acid or BOE corrosive liquid wet method to remove the oxide skin(coating) that is positioned at upper surface.
So far, described self compensation back of the body sealing is made complete.This self compensation back of the body sealing comprises and is positioned at oxide masking layer and the intrinsic polysilicon masking layer that heavy doping substrate edge sidewall and lower surface retain.Described self compensation back of the body sealing further comprises the self compensation layer with the second conduction type that is positioned at heavy doping substrate edge and lower surface.
Preferably, use the grow light dope epitaxial loayer of the second conduction type of normal pressure epitaxial furnace on the upper surface of substrate.
Alternatively, use the grow light dope epitaxial loayer of the second conduction type of reduced pressure epitaxy stove on the upper surface of substrate.
The utility model provides a kind of Semiconductor substrate with self compensation back of the body sealing, comprising:
There is the semiconductor chip of the first conduction type of the first doping content;
Be positioned at the layer of compensation on the lower surface of described substrate and sidewall with the second conduction type of the second doping content, the second conduction type is different from the first conduction type;
Be positioned at the outer oxide skin(coating) that covers described substrate lower surface and at least part of sidewall of described layer of compensation;
Be positioned at the intrinsic polysilicon layer outside described silicon oxide layer.
Preferably, described the second doping content is greater than described the first doping content.
Preferably, the first doping content is about 2 × 10
19cm
-3, the second doping content is greater than 2 × 10
19cm
-3.
Preferably, described substrate comprises the buried regions district of the first conduction type or the second conduction type.
Preferably, the thickness of described silicon oxide layer is
Preferably, the thickness of described intrinsic polysilicon layer is
Preferably, described the first conduction type is N-type, and the second conduction type is P type; Or described the first conduction type is P type, and the second conduction type is N-type.
Preferably, described semiconductor chip is silicon chip, and described oxide is silica.
The utility model discloses a kind of make simple, can volume production, low cost, high efficiency self compensation back of the body envelope technique.The self compensation back of the body sealing substrate that adopts this process to make, even with the full stove growth of normal pressure epitaxial furnace, still can ensure that extension parameter meets product requirement.
The beneficial effects of the utility model are as follows:
Use self compensation back of the body sealing technique of the present utility model, for the semiconductor device of selecting the requirement of heavy doping substrate making specific function provides possibility, and can significantly improve quality and the efficiency of heavy doping substrate growth transoid light dope epitaxial loayer.
Through checking, adopt self compensation of the present utility model back of the body sealing technique, the resistivity of the resistivity of heavy doping substrate and the transoid light dope epitaxial loayer that obtains on this heavy doping substrate can differ 3-5 the order of magnitude.Select the heavy doping P type substrate of 0.004-0.006 Ω cm with substrate, carrying out antimony injection formation n type buried layer district is thereon example, if adopting the normal pressure epitaxy technique monolithic of prior art to make Thickness Design requirement is that 7.5 μ m, resistivity designing requirement are the light dope N-type epitaxial loayer of 5.5 Ω cm, due to autodoping effect impact, while machining, the positive complete transoid of N-type has become P type, as Fig. 1.On the contrary, adopted according to the method step of the utility model self compensation back of the body envelope technique, when the Grown concentration same is 2 × 10
19cm
-3n-type layer of compensation time, full stove processing, N-type resistivity still can easier be controlled within the scope of 5.5 ± 0.5 Ω cm, autodoping effect is effectively suppressed, electrical resistivity of epitaxy evenly, consistent, as Fig. 2.Visible, the substrate of carrying on the back sealing and comprising this back of the body sealing according to self compensation of the present utility model is for suppressing heavy doping substrate autodoping effect, and effect is very obvious.
Brief description of the drawings
Fig. 1 illustrates under prior art that light dope epitaxial loayer is by the SRP test curve of the substrat structure of transoid.
Fig. 2 illustrates the substrat structure SRP test curve of light dope N-type epitaxial loayer on the heavy doping P type substrate obtaining according to the utility model.
Fig. 3～Figure 13 illustrates the method step flow chart according to the utility model preferred embodiment.
In each accompanying drawing, mark is described as follows above:
1: intrinsic polysilicon masking layer
2: silica masking layer
3: heavy doping substrate
4: layer of compensation/self compensation layer
5: buried regions district
6: transoid light dope epitaxial loayer
7: silicon oxide layer
8: photoresist layer
Embodiment
In order to be illustrated more clearly in the utility model, below in conjunction with preferred embodiments and drawings, the utility model is described further.Parts similar in accompanying drawing represent with identical Reference numeral.It will be appreciated by those skilled in the art that specifically described content is illustrative and nonrestrictive below, should not limit protection range of the present utility model with this.
Fig. 3～13 show a kind of according to the method step flow chart at substrate process segment formation self compensation back of the body envelope substrate grown epitaxial layer of the utility model preferred embodiment.
The heavily doped silicon substrate 3 that provides the resistivity with the first conduction type to be less than 0.01 Ω cm, as shown in Figure 3.In the present embodiment, the first conduction type is P type, and impurity is boron (B), and the resistivity of this P type doped substrate is 0.004-0.006 Ω cm, and its doping content is about 2 × 10
19cm
-3.
As a preferred embodiment, can use method growth thickness on heavy doping substrate 3 of diffusion furnace thermal oxidation is for example the fine and close silicon oxide layer of 1 μ m, and this silicon oxide layer surrounds whole substrate and has uniform thickness.
As a preferred embodiment, in the time need to preparing the second conduction type be the buried regions district of N-type in silicon chip, this silica can be used as the masking layer of making buried regions district.Being formed for the opening of doping and making implantation dosage by diffusion or Implantation at the silicon oxide layer that is arranged in substrate upper surface is 5 × 10
15cm
-2antimony buried regions district 5.Subsequently the substrate that comprises antimony buried regions district obtaining is annealed.This annealing process further generates approximately on the heavy doping substrate 3 that is formed with silicon oxide layer
silicon oxide layer, obtain thus the first silicon oxide layer 7, as Fig. 4.This first silicon oxide layer 7 is using the masking layer when making subsequently self compensation layer 4.
Subsequently, the structure upper surface obtaining at Fig. 4 applies photoresist layer 8, as Fig. 5.Preferably, the thickness range of photoresist layer 8 is
those skilled in the art can be according to the thickness of the thickness choose reasonable photoresist layer of silicon oxide layer 7.Use in this example for example ultraviolet negative photoresist, its thickness is about 1 μ m.
Subsequently, use the BOE corrosive liquid that proportioning is 6:1 to carry out selective corrosion to obtained structure, the speed of this corrosive liquid corrosion oxidation silicon and photoresist is about respectively
be less than
use this corrosive liquid wet method to remove lower surface and the sidewall oxidation silicon layer without photoresist masking on substrate, obtain structure as shown in Figure 6.
Subsequently, photoresist layer 8 is peeled off, obtained structure as shown in Figure 7.
Subsequently, use sidewall and the lower surface of diffusion furnace counterweight doped substrate 3 to carry out N-type doping, obtain structure as shown in Figure 8.In this doping step, the silicon oxide layer 7 on 3 is doping masking layer, and the upper surface that makes substrate 3 is not doped and lower surface and sidewall to substrate adulterates.In this example, N-type impurity is phosphorus (P).
Subsequently, use diffusion furnace at 900～1100 DEG C, the structure shown in Fig. 8 to be annealed, to form self compensation layer 4, wherein the concentration of N-type impurity is for example 2.5 × 10
19cm
-3be greater than the doping content 2 × 10 of heavy doping substrate 3
19cm
-3, on substrate, grow simultaneously
the second silicon oxide layer 2, as Fig. 9.In this example, its thickness is about
Preferably, the second silicon oxide layer obtaining is by as silica masking layer when epitaxial growth on substrate, be arranged in the silica of substrate upper surface also using the resilient coating as subsequent etching polysilicon process, to prevent that plasma etching damage is arranged in buried regions district or the epitaxially grown substrate interface of heavy doping substrate 3 simultaneously.
Subsequently, use low-pressure chemical vapor phase deposition LPCVD on the whole surface of the silicon oxide layer 2 obtaining, comprise on upper and lower surface and sidewall and growing
intrinsic polysilicon layer 1, obtain structure as shown in figure 10.In this example, its thickness is about
Subsequently, use the process removal of dry plasma etch to be positioned at substrate upper surface polysilicon layer and a part of sidewall polycrystalline silicon layer, obtain structure as shown in figure 11.Preferably, the dry plasma etch process conditions that use make the etch rate to polysilicon and the etch rate of silica are about respectively
be less than
Preferably, the process conditions of the plasma dry etching using must possess enough etching selection ratio, with the preservation of the silica masking layer below the polysilicon masking layer that ensures to be etched.The silicon oxide layer that is now positioned at polysilicon layer below on substrate upper surface plays the effect of etching buffer memory, prevents that plasma etching damage is positioned at functional areas or the epitaxially grown interfaces such as the buried regions of heavy doping substrate 3 tops.
Subsequently, use the BOE corrosive liquid that proportioning is 6:1 to carry out selective corrosion, the speed of its corrosion oxidation silicon and polysilicon is about respectively
be less than
the polysilicon layer retaining is used as corroding masking layer.Use this corrosive liquid wet method to remove the silicon oxide layer that is positioned at substrate upper surface of sheltering without polysilicon, obtain structure as shown in figure 12.
So far the self compensation back of the body sealing substrate that, has self compensation layer 4 is made complete.This self compensation back of the body sealing outwards comprises N-type self compensation layer 4, the second silicon oxide layer 2 and intrinsic polysilicon layer 1 successively from substrate 3.Self compensation layer 4 is for to be positioned on the lower surface and sidewall of heavy doping substrate 3, and doping content is 2.5 × 10
19cm
-3n-type diffusion region.The second silicon oxide layer 2 is at lower surface and at least part of sidewall of described self compensation layer 4 outer covering substrate, and thickness is about
intrinsic polysilicon layer 1 is at lower surface and at least part of sidewall of the second silicon oxide layer 2 outer covering substrates, and thickness is about
According to method of the present utility model, within self compensation layer 4 may not be wrapped in silica masking layer 2 and intrinsic polysilicon masking layer 1 on a small quantity, as Figure 12.Experiment results proved, because being coated with the N-type self compensation layer 4 of doping content higher than Substrate Doping concentration, the N-type self compensation layer of this high concentration is separated out p type impurity ion in technical process subsequently suppresses heavy doping substrate effectively.A small amount of N-type foreign ion that may go out from self compensation chromatography in addition provides help to improving edge resistivity.
Subsequently, use the light dope epitaxial loayer 6 of normal pressure epitaxial furnace growth N-type, as Figure 13.In this example, the design parameter of this N-type light dope epitaxial loayer 6 is: doping type is N-type, and dopant species is phosphorus (P), and epitaxial thickness is that 7.5 ± 0.5 μ m, resistivity are 5.5 ± 0.5 Ω cm.Adopt the substrate obtaining according to self compensation back of the body sealing technique of the present utility model, use the full stove processing of normal pressure epitaxy method, still produce the light dope N-type epitaxial loayer that meets parameter request, in multiple substrates of this full stove growth, the resistivity of each substrate epitaxial layer and the uniformity of thickness are all greater than 90% after tested.Randomly draw a slice and do SRP test, as shown in Figure 2, on surface, to epitaxial interface, uniform resistivity is consistent for resolution chart.Therefore, can effectively suppress separating out of impurity in heavy doping substrate according to method of the present utility model, obtain meeting the chip structure of designing requirement.
It will be appreciated by those skilled in the art that, according to the utility model, the self compensation back of the body sealing forming is that device fabrication process insulation and that this self compensation back of the body sealing can be delayed is outside completely removed, and recovers heavy doping substrate 3 electric conductivity originally, can not affect follow-up test and use.
Obviously; above-described embodiment of the present utility model is only for the utility model example is clearly described; and be not the restriction to execution mode of the present utility model; to those of ordinary skill in the art; can also make other changes in different forms on the basis of the above description; here cannot give all execution modes exhaustively, everyly belong to apparent variation or the still row in protection range of the present utility model of variation that the technical solution of the utility model extends out.
Claims (8)
1. a Semiconductor substrate with self compensation back of the body sealing, is characterized in that, comprising:
There is the semiconductor chip of the first conduction type of the first doping content;
Be positioned at the layer of compensation on the lower surface of described substrate and sidewall with the second conduction type of the second doping content, the second conduction type is different from the first conduction type;
Be positioned at the outer oxide skin(coating) that covers described substrate lower surface and at least part of sidewall of described layer of compensation;
Be positioned at the intrinsic polysilicon layer outside described oxide skin(coating).
2. the Semiconductor substrate with self compensation back of the body sealing as claimed in claim 1, is characterized in that, described the second doping content is greater than described the first doping content.
3. the Semiconductor substrate with self compensation back of the body sealing as claimed in claim 1, is characterized in that, the first doping content is about 2 × 10
19cm
-3, the second doping content is greater than 2 × 10
19cm
-3.
4. the Semiconductor substrate with self compensation back of the body sealing as claimed in claim 1, is characterized in that, described substrate comprises the buried regions district of the first conduction type or the second conduction type.
5. the Semiconductor substrate as claimed in claim 1 with self compensation back of the body sealing, is characterized in that, the thickness of described oxide skin(coating) is
6. the Semiconductor substrate as claimed in claim 1 with self compensation back of the body sealing, is characterized in that, the thickness of described intrinsic polysilicon layer is
7. the Semiconductor substrate as claimed in claim 1 with self compensation back of the body sealing, is characterized in that, described semiconductor chip is silicon chip, and described oxide is silica.
8. the Semiconductor substrate as claimed in claim 1 with self compensation back of the body sealing, is characterized in that, described the first conduction type is N-type, and the second conduction type is P type; Or described the first conduction type is P type, and the second conduction type is N-type.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420390642.2U CN204029812U (en) | 2014-07-15 | 2014-07-15 | A kind of Semiconductor substrate with self compensation back of the body sealing |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420390642.2U CN204029812U (en) | 2014-07-15 | 2014-07-15 | A kind of Semiconductor substrate with self compensation back of the body sealing |
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|---|---|
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107256837A (en) * | 2017-07-19 | 2017-10-17 | 河北普兴电子科技股份有限公司 | The measuring method of the electrical resistivity of substrate is sealed based on the super back of the body |
-
2014
- 2014-07-15 CN CN201420390642.2U patent/CN204029812U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107256837A (en) * | 2017-07-19 | 2017-10-17 | 河北普兴电子科技股份有限公司 | The measuring method of the electrical resistivity of substrate is sealed based on the super back of the body |
| CN107256837B (en) * | 2017-07-19 | 2020-01-07 | 河北普兴电子科技股份有限公司 | Method for measuring resistivity of epitaxial wafer based on super back-sealed substrate |
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