CN112663137B - Preparation method of silicon anti-epitaxial wafer - Google Patents
Preparation method of silicon anti-epitaxial wafer Download PDFInfo
- Publication number
- CN112663137B CN112663137B CN202011573642.2A CN202011573642A CN112663137B CN 112663137 B CN112663137 B CN 112663137B CN 202011573642 A CN202011573642 A CN 202011573642A CN 112663137 B CN112663137 B CN 112663137B
- Authority
- CN
- China
- Prior art keywords
- setting
- reaction cavity
- silicon
- flow
- enter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 117
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 117
- 239000010703 silicon Substances 0.000 title claims abstract description 117
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims abstract description 148
- 239000007789 gas Substances 0.000 claims abstract description 85
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims abstract description 74
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910002804 graphite Inorganic materials 0.000 claims abstract description 22
- 239000010439 graphite Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 17
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims abstract description 11
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 44
- 239000001257 hydrogen Substances 0.000 claims description 44
- 229910052739 hydrogen Inorganic materials 0.000 claims description 44
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 claims description 36
- 239000005052 trichlorosilane Substances 0.000 claims description 36
- 230000035484 reaction time Effects 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 15
- 238000001816 cooling Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 7
- 239000013078 crystal Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000004857 zone melting Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to a preparation method of a silicon anti-epitaxial wafer, wherein hydrogen chloride gas is introduced into a reaction cavity; depositing a layer of undoped compact polysilicon on the surface of a straight cylinder type graphite base; a silicon substrate slice is arranged on a straight cylinder type graphite base in the reaction cavity; allowing the phosphine gas to enter the reaction cavity to fill the reaction cavity with the phosphine gas; growing a first silicon epitaxial layer on a silicon substrate; after the growth of the first silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, so that the reaction cavity is filled with the phosphine gas; growing a second silicon epitaxial layer on the first silicon epitaxial layer; after the growth of the second silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, so that the reaction cavity is filled with the phosphine gas; growing a third silicon epitaxial layer on the second silicon epitaxial layer; and obtaining the silicon reverse epitaxial wafer after the growth of the third silicon epitaxial layer is finished. The method obviously improves the doping concentration of the silicon epitaxial layer of the silicon epitaxial wafer by one order of magnitude, and the thickness of the silicon epitaxial layer reaches an ultra-thick state of 250-260 mu m.
Description
Technical Field
The invention relates to the technical field of preparation of semiconductor epitaxial materials, in particular to a preparation method of a silicon anti-epitaxial wafer.
Background
The working principle of the photodetector is the photoelectric effect, when the energy of an incident photon is larger than or equal to the band gap energy of a semiconductor, an electron on an excited valence band absorbs the energy of the photon and jumps to a conduction band, and the process generates a free electron-hole pair. The N-type semiconductor with low concentration is introduced into the middle of the PN junction of the photodiode, so that the width of a depletion region can be increased, and the aims of reducing the influence of diffusion motion and improving the response speed are fulfilled. This structure becomes a PIN photodiode because this doped layer is called an I layer because of its low doping concentration, nearly Intrinsic semiconductor. The I layer is thick and occupies almost the entire depletion region. The vast majority of incident light is absorbed within the I layer and a large number of electron-hole pairs are generated. The P-type and N-type semiconductors with high doping concentration are arranged on two sides of the I layer, the P layer and the N layer are very thin, and the proportion of absorbing incident light is very small. The drift component of the light-generating current is dominant, which greatly increases the response speed.
The PIN photodiode requires ultra-high resistivity and ultra-thick layer for silicon material, and the epitaxial process can not be realized. For a long time, the research unit of the device adopts a zone-melting silicon single crystal substrate as a base, but the performance of the device is greatly restricted due to overlarge contact resistance.
The silicon anti-epitaxial wafer and the silicon epitaxial wafer are used in the opposite way, the zone-melting silicon single crystal is used as an active region of a device, the doping concentration of the prepared epitaxial layer is high, the prepared epitaxial layer is super-thick, the potential gradient is formed, and the metal electrode and the heavily-doped epitaxial layer region form ohmic contact. Therefore, the doping concentration of the silicon epitaxial layer of the silicon anti-epitaxial wafer needs to be reached>4×1019cm-3The thickness of the silicon epitaxial layer needs to reach an ultra-thick state of 250-260 mu m, the crystal integrity of the silicon epitaxial layer is good, and the damage and the fragments of the epitaxial layer caused by defects are prevented. The conventional method for directly growing the low-defect heavily-doped epitaxial layer in the super-thick state is difficult, and the doping concentration of the silicon epitaxial layer can only reach 1 × 1018cm-3~6×1018cm-3The magnitude of (1) is lower than the target value, and the practical application of the device is seriously influenced.
Disclosure of Invention
The invention aims to solve the problem that the existing silicon epitaxial wafer is difficult to control the compatibility of heavy doping concentration and low-defect ultra-thick epitaxial growth in the conventional epitaxial growth process, and the preparation method of the silicon epitaxial wafer is obtained by designing a method for multi-stage epitaxial growth and pre-feeding high-concentration phosphine gas into a reaction cavity, so that the doping concentration of a silicon epitaxial layer of the silicon epitaxial wafer and the lattice integrity of the silicon epitaxial layer in an ultra-thick state are obviously improved, and the use requirement is met.
The technical scheme adopted by the invention is as follows: a preparation method of a silicon anti-epitaxial wafer comprises the following steps:
(1) introducing hydrogen chloride gas into the reaction cavity, setting the flow of the hydrogen chloride gas to be 34-36L/min, etching residual deposited substances on the straight-tube graphite base of the reaction cavity at high temperature, setting the etching temperature to be 1160-1180 ℃, and setting the etching time to be 3.0-3.5 min;
(2) setting the hydrogen flow to be 300-305L/min, carrying gaseous trichlorosilane to enter a reaction cavity, setting the trichlorosilane flow to be 36.0-37.0L/min, setting the reaction time to be 55-60 sec, and depositing a layer of undoped dense polycrystalline silicon on the surface of the straight-tube graphite base;
(3) loading a silicon substrate slice on the straight-barrel type graphite base in the reaction cavity, wherein the diameter of the silicon substrate slice is 150-200 mm, and then heating the reaction cavity to 1130-1160 ℃;
(4) allowing the phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 800-820 sccm, and the entering time is set to be 2-3 min, so that the phosphine gas is filled in the reaction cavity;
(5) growing a first silicon epitaxial layer on a silicon substrate, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 300-305L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35-36L/min, setting the reaction time to be 17-21 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 800-820 sccm;
(6) after the growth of the first silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 800-820 sccm, and the entering time is set to be 2-3 min, so that the phosphine gas is filled in the reaction cavity;
(7) growing a second silicon epitaxial layer on the first silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 300-305L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35-36L/min, setting the reaction time to be 17-21 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 800-820 sccm;
(8) after the growth of the second silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 800-820 sccm, and the entering time is set to be 2-3 min, so that the phosphine gas is filled in the reaction cavity;
(9) growing a third silicon epitaxial layer on the second silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 300-305L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35-36L/min, setting the reaction time to be 9-11 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 800-820 sccm;
(10) and after the growth of the third silicon epitaxial layer is finished, obtaining a silicon reverse epitaxial wafer, cooling, and taking out the silicon reverse epitaxial wafer from the straight-barrel graphite base after the temperature of the silicon reverse epitaxial wafer is reduced to 60 ℃.
The invention has the advantages that the problem that the existing silicon reverse epitaxial wafer is difficult to be compatible with the heavy doping concentration and the low defect ultra-thick epitaxial growth in the conventional epitaxial growth process is solved, the preparation method of the silicon reverse epitaxial wafer with high doping concentration and ultra-thick state and low defect is provided by designing the method of the multi-stage epitaxial growth and the pre-entering of the high concentration phosphine gas into the reaction cavity before the growth, and the doping concentration of the silicon epitaxial wafer is realized>4×1019cm-3Compared with the conventional epitaxial process, the doping concentration of the silicon epitaxial layer of the silicon epitaxial wafer can be obviously improved by one order of magnitude, and meanwhile, the thickness of the silicon epitaxial layer can reach an ultra-thick state of 250-260 mu m and a good control level without crystal defects.
Detailed Description
The diameter of the silicon substrate sheet used in the invention is 150-200 mm, the resistivity is 1000-1500 omega cm, and the thickness and the doping concentration of the prepared silicon reverse epitaxial wafer are obtained by testing the central point of the silicon reverse epitaxial wafer.
Example 1
(1) Introducing hydrogen chloride gas into the reaction cavity, setting the flow of the hydrogen chloride gas at 35L/min, etching residual deposited substances on the straight-barrel graphite pedestal of the reaction cavity at high temperature, setting the etching temperature at 1170 ℃, and setting the etching time at 3.2 min;
(2) setting the hydrogen flow rate to be 302L/min, carrying gaseous trichlorosilane to enter a reaction cavity, setting the trichlorosilane flow rate to be 36.5L/min, setting the reaction time to be 58 sec, and depositing a layer of undoped dense polycrystalline silicon on the surface of the straight-tube graphite base;
(3) loading a silicon substrate slice with the diameter of 150mm on a straight cylinder type graphite base in a reaction cavity, and then heating the reaction cavity to 1140 ℃;
(4) allowing the phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 810sccm, and the entering time is set to be 2.5min, so that the phosphine gas is filled in the reaction cavity;
(5) growing a silicon epitaxial layer on a silicon substrate, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 50 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;
(6) and after the growth of the silicon epitaxial layer is finished, obtaining a silicon anti-epitaxial wafer, starting cooling, and taking out the silicon anti-epitaxial wafer from the straight-barrel graphite base after the temperature of the silicon anti-epitaxial wafer is reduced to 60 ℃.
The silicon epitaxial wafer obtained in example 1 had a silicon epitaxial layer doping concentration of only 2X 1018cm-3The thickness of the silicon epitaxial layer reaches 255 mu m, and the surface defect density is high, so that the single-step epitaxial growth cannot meet the use requirement of the device.
Example 2
(1) Introducing hydrogen chloride gas into the reaction cavity, setting the flow of the hydrogen chloride gas at 35L/min, etching residual deposited substances on the graphite base of the reaction cavity at a high temperature, setting the etching temperature at 1170 ℃, and setting the etching time at 3.2 min;
(2) setting the hydrogen flow rate to be 302L/min, allowing gaseous trichlorosilane to enter a reaction cavity, setting the trichlorosilane flow rate to be 36.5L/min, setting the reaction time to be 58 sec, and depositing a layer of undoped dense polycrystalline silicon on the surface of the straight-tube graphite base;
(3) loading a silicon substrate slice with the diameter of 150mm on a straight-barrel type graphite base in a reaction cavity, and then heating the reaction cavity to 1140 ℃;
(4) allowing the phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 600sccm, and the entering time is set to be 2.5min, so that the phosphine gas is filled in the reaction cavity;
(5) growing a first silicon epitaxial layer on a silicon substrate, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 20min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;
(6) after the growth of the first silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to 600sccm, and the entering time is set to 2.5min, so that the phosphine gas is filled in the reaction cavity;
(7) growing a second silicon epitaxial layer on the first silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 20min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;
(8) allowing the phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 600sccm, and the entering time is set to be 2.5min, so that the phosphine gas is filled in the reaction cavity;
(9) growing a third silicon epitaxial layer on the second silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 10min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;
(10) and (3) finishing the growth of the third silicon epitaxial layer to obtain a silicon reverse epitaxial wafer, starting cooling, and taking out the silicon reverse epitaxial wafer from the straight-barrel graphite base after the temperature of the silicon reverse epitaxial wafer is reduced to 60 ℃.
The doping concentration of the silicon epitaxial layer of the silicon anti-epitaxial wafer prepared in the example 2 is only 6 multiplied by 1018cm3The thickness of the silicon epitaxial layer reaches 255 mu m, and the surface defect density is higher, so that the surface quality and the doping concentration of the silicon reverse epitaxial wafer can not meet the use requirements of devices only by adopting two-step epitaxial growth.
Example 3
(1) Introducing hydrogen chloride gas into the reaction cavity, setting the flow of the hydrogen chloride gas at 35L/min, etching residual deposited substances on the straight-tube graphite base of the reaction cavity at a high temperature, setting the etching temperature at 1170 ℃, and setting the etching time at 3.2 min;
(2) setting the hydrogen flow rate to be 302L/min, carrying gaseous trichlorosilane to enter a reaction cavity, setting the trichlorosilane flow rate to be 36.5L/min, setting the reaction time to be 58 sec, and depositing a layer of undoped dense polycrystalline silicon on the surface of the straight-tube graphite base;
(3) loading a silicon substrate slice with the diameter of 150mm on a straight-barrel type graphite base in a reaction cavity, and then heating the reaction cavity to 1140 ℃;
(4) allowing the phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 810sccm, and the entering time is set to be 2.5min, so that the phosphine gas is filled in the reaction cavity;
(5) growing a first silicon epitaxial layer on a silicon substrate, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 20min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;
(6) after the growth of the first silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to 810sccm, and the entering time is set to 2.5min, so that the phosphine gas is filled in the reaction cavity;
(7) growing a second silicon epitaxial layer on the first silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 20min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;
(8) after the growth of the second silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to 810sccm, and the entering time is set to 2.5min, so that the phosphine gas is filled in the reaction cavity;
(9) growing a third silicon epitaxial layer on the second silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the hydrogen flow of one path to be 302L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the trichlorosilane flow to be 35.5L/min, setting the reaction time to be 10min, setting the hydrogen flow of the other path to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the phosphine gas flow to be 810 sccm;
(10) and after the growth of the third silicon epitaxial layer is finished, obtaining a silicon reverse epitaxial wafer, cooling, and taking out the silicon reverse epitaxial wafer from the straight-barrel graphite base after the temperature of the silicon reverse epitaxial wafer is reduced to 60 ℃.
The doping concentration of the silicon epitaxial layer prepared in example 3 reached 6 × 1019cm-3The thickness of the silicon epitaxial layer reaches 255 mu m, and the surface is free of defects.
Compared with the embodiment 1 and the embodiment 2, under the corresponding process conditions, the embodiment 3 adopts three-step silicon epitaxial layer growth, and before each step of silicon epitaxial layer growth, a mode of introducing phosphine gas into a reaction cavity and filling the cavity is adopted in advance, so that the silicon epitaxial layer doping concentration of the prepared silicon anti-epitaxial wafer is highest, the crystal quality is best under an ultra-thick state, and the use requirement of a device can be met, therefore, the embodiment 3 is the best embodiment of the invention.
It is apparent that those skilled in the art can make various changes and modifications to the preparation method of the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (1)
1. A preparation method of a silicon reverse epitaxial wafer is characterized by comprising the following steps:
(1) introducing hydrogen chloride gas into the reaction cavity, setting the flow of the hydrogen chloride gas to be 34-36L/min, etching residual deposited substances on the straight-tube graphite base of the reaction cavity at high temperature, setting the etching temperature to be 1160-1180 ℃, and setting the etching time to be 3.0-3.5 min;
(2) setting the hydrogen flow to be 300-305L/min, carrying gaseous trichlorosilane to enter a reaction cavity, setting the trichlorosilane flow to be 36.0-37.0L/min, setting the reaction time to be 55-60 sec, and depositing a layer of undoped dense polycrystalline silicon on the surface of the straight-tube graphite base;
(3) loading a silicon substrate slice on the straight-barrel type graphite base in the reaction cavity, wherein the diameter of the silicon substrate slice is 150-200 mm, and then heating the reaction cavity to 1130-1160 ℃;
(4) allowing the phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 810sccm, and the entering time is set to be 2.5min, so that the phosphine gas is filled in the reaction cavity;
(5) growing a first silicon epitaxial layer on a silicon substrate, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 300-305L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35-36L/min, setting the reaction time to be 20min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;
(6) after the growth of the first silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to 810sccm, and the entering time is set to 2.5min, so that the phosphine gas is filled in the reaction cavity;
(7) growing a second silicon epitaxial layer on the first silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 300-305L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35-36L/min, setting the reaction time to be 20min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;
(8) after the growth of the second silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to 810sccm, and the entering time is set to 2.5min, so that the phosphine gas is filled in the reaction cavity;
(9) growing a third silicon epitaxial layer on the second silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 300-305L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35-36L/min, setting the reaction time to be 10min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;
(10) after the growth of the third silicon epitaxial layer is finished, obtaining a silicon reverse epitaxial wafer, cooling, and taking out the silicon reverse epitaxial wafer from the straight-barrel graphite base after the temperature of the silicon reverse epitaxial wafer is reduced to 60 ℃;
the resistivity of the silicon substrate sheet is 1000-1500 omega cm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011573642.2A CN112663137B (en) | 2020-12-28 | 2020-12-28 | Preparation method of silicon anti-epitaxial wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011573642.2A CN112663137B (en) | 2020-12-28 | 2020-12-28 | Preparation method of silicon anti-epitaxial wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112663137A CN112663137A (en) | 2021-04-16 |
| CN112663137B true CN112663137B (en) | 2022-07-05 |
Family
ID=75410199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011573642.2A Active CN112663137B (en) | 2020-12-28 | 2020-12-28 | Preparation method of silicon anti-epitaxial wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112663137B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118127623A (en) * | 2024-05-07 | 2024-06-04 | 中电晶华(天津)半导体材料有限公司 | Heavily doped substrate N-type silicon epitaxial wafer for VDMOS device and preparation method and application thereof |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5863138A (en) * | 1981-10-12 | 1983-04-14 | Nec Corp | Semiconductor device and manufacture thereof |
| CN100382243C (en) * | 2006-06-09 | 2008-04-16 | 河北工业大学 | Control method for raising consistence of silicon epitaxial resistivity |
| CN102280502B (en) * | 2011-08-26 | 2013-04-17 | 上海师范大学 | Gradient doped silicon-based heterojunction solar cell and preparation method thereof |
| CN102290337B (en) * | 2011-09-26 | 2013-04-03 | 南京国盛电子有限公司 | Manufacturing method for silicon epitaxial wafer of low-voltage TVS (transient voltage suppressor) |
| CN103160912B (en) * | 2011-12-08 | 2015-11-11 | 有研半导体材料有限公司 | A kind of preparation technology of the zone melting single-crystal that adulterates |
| CN103820849B (en) * | 2012-11-16 | 2016-04-06 | 有研半导体材料有限公司 | A kind of technique of the production 12 cun of silicon single crystal epitaxial wafers that reduce pressure |
| CN105895754B (en) * | 2016-05-03 | 2018-08-31 | 武汉光安伦光电技术有限公司 | A kind of production method of two pole piece piece of InGaAsP materials buried waveguide structure superradiation light-emitting |
| KR101951838B1 (en) * | 2016-12-23 | 2019-02-26 | 주식회사 포스코 | method for fabricating Silicon carbide epitaxial wafer |
| CN111463116B (en) * | 2020-04-27 | 2022-04-12 | 中国电子科技集团公司第四十六研究所 | Preparation method of double-layer epitaxy for MOS device structure |
| CN111463115B (en) * | 2020-04-27 | 2022-05-13 | 中国电子科技集团公司第四十六研究所 | Preparation method of silicon epitaxial wafer for Schottky device |
-
2020
- 2020-12-28 CN CN202011573642.2A patent/CN112663137B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN112663137A (en) | 2021-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8124502B2 (en) | Semiconductor device manufacturing method, semiconductor device and semiconductor device manufacturing installation | |
| JP2012506629A (en) | Semiconductor device manufacturing method, semiconductor device, and semiconductor device manufacturing facility | |
| CN103337506B (en) | A kind of preparation technology of silicon epitaxial wafer for CCD device | |
| CN112663137B (en) | Preparation method of silicon anti-epitaxial wafer | |
| CN104409345A (en) | Manufacturing method of silicon epitaxial wafer of large-power PIN device | |
| US9012769B2 (en) | Photoelectric conversion device | |
| CN113903833A (en) | TOPCon battery LPCVD (low pressure chemical vapor deposition) process | |
| US8871555B2 (en) | Photoelectric conversion device and manufacturing method thereof | |
| JP6109107B2 (en) | Solar cell and method for manufacturing the same | |
| WO2015114921A1 (en) | Photoelectric conversion device | |
| JP5745653B2 (en) | Photovoltaic device, manufacturing method thereof, and photovoltaic module | |
| AU2023375286A1 (en) | Solar cell, manufacturing method therefor and battery assembly | |
| CN112768549A (en) | HJT battery with high photoelectric conversion efficiency and preparation method thereof | |
| JP2011009754A (en) | Method of manufacturing solar cell | |
| CN108336170B (en) | Method for manufacturing solar cell | |
| Zhang et al. | Improvement of passivation quality by post-crystallization treatments with different methods for high quality tunnel oxide passivated contact c-Si solar cells | |
| JPS5936836B2 (en) | Amorphous thin film solar cell | |
| JPS6132416A (en) | Manufacture of semiconductor device | |
| JPH04290274A (en) | Photoelectric transducer | |
| CN112382670B (en) | Avalanche diode based on high-purity intrinsic monocrystalline diamond and preparation method | |
| JP5398772B2 (en) | Photovoltaic device, manufacturing method thereof, and photovoltaic module | |
| KR20170057388A (en) | Solar cell fabricated by simplified deposition process | |
| JP2005191024A (en) | Photovoltaic power device and its manufacturing method | |
| KR101599193B1 (en) | Nano wire solar cell and method of fabricating therof | |
| JPH0376018B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A preparation method for silicon anti epitaxial wafers Granted publication date: 20220705 Pledgee: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO.46 Research Institute Pledgor: CLP Jinghua (Tianjin) semiconductor materials Co.,Ltd. Registration number: Y2024120000028 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right |