CN113903833A - TOPCon battery LPCVD (low pressure chemical vapor deposition) process - Google Patents

TOPCon battery LPCVD (low pressure chemical vapor deposition) process Download PDF

Info

Publication number
CN113903833A
CN113903833A CN202111029186.XA CN202111029186A CN113903833A CN 113903833 A CN113903833 A CN 113903833A CN 202111029186 A CN202111029186 A CN 202111029186A CN 113903833 A CN113903833 A CN 113903833A
Authority
CN
China
Prior art keywords
amorphous silicon
layer
oxide layer
topcon
lpcvd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111029186.XA
Other languages
Chinese (zh)
Inventor
欧文凯
董思敏
向亮睿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pule New Energy Technology Taixing Co ltd
Original Assignee
Pule New Energy Technology Xuzhou Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pule New Energy Technology Xuzhou Co ltd filed Critical Pule New Energy Technology Xuzhou Co ltd
Priority to CN202111029186.XA priority Critical patent/CN113903833A/en
Publication of CN113903833A publication Critical patent/CN113903833A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0376—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors
    • H01L31/03762—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors including only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H01L31/03921—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate including only elements of Group IV of the Periodic System
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention provides a TOPCon cell LPCVD process, amorphous silicon layers with different densities are formed on a tunneling oxide layer, when high-temperature phosphorus diffusion is carried out in the subsequent process, a first layer of ultra-compact amorphous silicon layer is slower in speed, more compact in phase and less in dangling bonds in the preparation process, is converted into smaller-phase grains and simultaneously has more crystal boundaries, a second layer of amorphous silicon layer is converted into larger grains and simultaneously has less crystal boundaries, high-concentration phosphorus atoms on the surface are diffused in an inward gradient manner in the phosphorus atom diffusion process, the speed of phosphorus atom diffusion to the tunneling oxide layer is reduced by utilizing the gap/displacement diffusion which is smaller than the speed of phosphorus atom absorption by the crystal boundaries, the TOPCon structure formed by the doped amorphous silicon and the tunneling oxide layer greatly improves the carrier selection effect, the tunnel oxide layer is far away from a substrate, the field passivation is enhanced, the tunnel phosphorus atom penetration through the tunneling oxide layer is effectively reduced, the tunneling layer penetration effect is ensured, the TOPCon structure formed by the doped amorphous silicon and the tunneling oxide layer greatly improves the carrier selection effect, the efficiency of the solar cell is improved.

Description

TOPCon battery LPCVD (low pressure chemical vapor deposition) process
Technical Field
The invention relates to the field of solar cell production and manufacturing, in particular to an excellent TOPCon cell LPCVD process.
Background
With the increasing and developing of photovoltaic technology, various high-efficiency batteries are also developed, wherein a TOPCon battery is provided with an ultrathin tunneling oxide layer and a highly doped polysilicon thin layer on the back surface, the ultrathin tunneling oxide layer and the highly doped polysilicon thin layer form a passivation contact structure together, the structure provides good surface passivation for the back surface of a silicon wafer, the ultrathin oxide layer can enable multi-electron tunneling to enter the polysilicon layer and simultaneously block minority hole recombination, and then electrons are laterally transmitted in the polysilicon layer and collected by metal, so that the metal contact recombination current is greatly reduced, and the open-circuit voltage and the short-circuit current of the battery are improved.
However, in the existing process of preparing and matching phosphorus doping, high-concentration phosphorus doping: when phosphorus atoms penetrate through the tunneling oxide layer, the integrity of the tunneling oxide layer is damaged, and the carrier selection capability of the TOPCon structure is weakened; low-concentration phosphorus doping: the doping concentration reaching the tunneling oxide layer is light, the field passivation effect of an N/N + structure is difficult to form, and the two points restrict the improvement of the conversion efficiency of the TOPCon technology.
Disclosure of Invention
In order to solve the technical problems, the technical scheme provided by the invention is as follows: a TOPCon battery LPCVD process comprises the following steps:
the method comprises the following steps: selecting an N-type silicon wafer as a substrate material, and cleaning and texturing to generate a pyramid-shaped surface structure on the surface of the silicon wafer;
step two: carrying out boron diffusion on the front surface of the silicon wafer;
step three: carrying out BSG etching and back polishing on the silicon wafer;
step four: forming a tunneling oxide layer on the back of the silicon wafer;
step five: forming amorphous silicon on the tunneling oxide layer on the back surface of the silicon wafer;
step six: phosphorus doping is carried out on the amorphous silicon layer on the back surface, so that the doped amorphous silicon layer and the tunneling oxide layer form a TOPCon structure after crystallization;
preferably, the method for forming the tunneling oxide layer in the fourth step includes: nitric acid oxidation method, thermal oxidation method or LPCVD preparation method, and the thickness of the tunneling oxide layer is 1-2 nm.
Preferably, in the fifth step, amorphous silicon layers with different densities are formed on the tunneling oxide layer, that is, a first amorphous silicon layer and a second amorphous silicon layer are sequentially formed on the tunneling oxide layer.
Preferably, the first amorphous silicon layer is an ultra-dense amorphous silicon layer.
Preferably, the first amorphous silicon layer has a smaller crystallized grain size than the second amorphous silicon layer.
Preferably, in the fifth step, two amorphous silicon layers are formed on the tunneling oxide layer, and the method specifically includes the following steps:
s1: putting a silicon wafer into an LPCVD furnace tube, wherein the process temperature is 560-620 ℃;
s2: the silicon chip is vacuumized, leak-proof and nitrogen purged in the furnace tube and can be stabilized within a preset required pressure range in the nitrogen atmosphere;
s3: the pressure in the silicon chip process is controlled to be 160mTor-240 mTor;
s4: in the silicon chip process, gas is introduced into a furnace mouth and a furnace in two ways, wherein the flow ratio of SiH4 is 90: 180 sccm-140: 280 sccm;
s5: in the silicon chip process, the thickness of a first layer of ultra-compact amorphous silicon layer is 30-50nm through first deposition;
s6: after a first layer of amorphous silicon of the silicon wafer is prepared, nitrogen purging and pressure and temperature adjustment are carried out;
s7: in the silicon chip process, the thickness of the second layer of amorphous silicon layer is 70-90nm through the second deposition, and the sum of the thicknesses of the two layers of amorphous silicon layers is 140 nm;
preferably, in the first deposition in step S5, the preparation process temperature is controlled to be 560-590 ℃, and the process pressure is controlled to be 170-200 mTor; the flow of SiH4 through the furnace was controlled at 90: 180 sccm-110: 220sccm for 10-15min to obtain a first dense and uniform amorphous silicon layer under the conditions of low pressure and low temperature;
preferably, the adjusting of step S6 includes: stopping introducing special gas into the tube, evacuating, stabilizing pressure by using nitrogen, and heating at the temperature of 590-620 ℃;
preferably, in the step S7 of the second deposition, the preparation process temperature is controlled to be 590-620 ℃; the process pressure is controlled to be 200mTor-230 mTor; the flow of SiH4 into the furnace was controlled at 120: 240 sccm-140: 280sccm for 10-15min to obtain a second amorphous silicon layer under low pressure and low temperature conditions.
Preferably, after step S6 is completed, the introduction of the specialty gas into the tube is stopped, and evacuation purge is performed.
After the scheme is adopted, the invention has the following advantages: in the invention, amorphous silicon layers with different densities are formed on the tunneling oxide layer, namely a first ultra-compact amorphous silicon layer and a second amorphous silicon layer are formed on the tunneling oxide layer, and when high-temperature phosphorus diffusion is carried out in the subsequent process, the two amorphous silicon layers with different densities appear: the first layer of the ultra-compact amorphous silicon layer has slower speed and is more compact in the preparation process, fewer dangling bonds are formed, the first layer of the ultra-compact amorphous silicon layer is transformed into larger crystal grains and is accompanied by fewer crystal boundaries, the second layer of the ultra-compact amorphous silicon layer is transformed into more small crystal grains and is accompanied by more crystal boundaries, in the process of phosphorus atom diffusion, high-concentration phosphorus atoms on the surface are diffused to the inner part in a gradient way, the speed of phosphorus atom absorption by utilizing clearance/displacement diffusion is less than that of the phosphorus atom absorption by a crystal boundary, so that the diffusion rate of phosphorus atoms to the tunneling oxide layer is reduced, and the tunneling oxide layer far from the substrate has high-concentration phosphorus doping amount, thereby enhancing field passivation, meanwhile, phosphorus atoms penetrating through the tunneling oxide layer are effectively reduced, the function of the tunneling layer is guaranteed, the TOPCon structure formed by the doped amorphous silicon and the tunneling oxide layer greatly improves the function of selecting carriers, and the improvement of the efficiency of the solar cell is facilitated.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a back side structure of an LPCVD process of the present invention;
FIG. 2 is a back side structure of the phosphorus diffusion process of the present invention;
the figures in the drawings represent: 1. an N-type silicon wafer substrate; 2. tunneling through the oxide layer; 3. a first ultra-dense amorphous silicon layer; 4. a second amorphous silicon layer; 5. An N-type silicon wafer substrate; 6. tunneling through the oxide layer; 7. doping the first ultra-compact crystalline silicon layer; 8. and doping the second layer of crystalline silicon layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
An excellent TOPCon battery LPCVD process mainly comprises the following steps:
the method comprises the following steps: an N-type silicon wafer is used as a substrate material, and a pyramid-shaped surface structure is generated on the surface of the silicon wafer through cleaning and texturing;
step two: carrying out boron diffusion on the front surface of the silicon wafer;
step three: carrying out BSG etching and back polishing on the silicon wafer;
step four: forming a tunneling oxide layer with the thickness of 1-2nm on the back of the silicon wafer;
step five: forming amorphous silicon layers with different densities on the tunneling oxide layer on the back surface of the silicon wafer, namely forming a first ultra-compact amorphous silicon layer and a second amorphous silicon layer on the tunneling oxide layer:
s1: putting the silicon wafer into an LPCVD furnace tube, wherein the process temperature is 560 ℃;
s2: vacuumizing, leakage detection and nitrogen purging are carried out in the furnace tube, and the furnace tube can be stabilized within a preset required pressure range in a nitrogen atmosphere;
s3: first deposition: the pressure was controlled at 170mTor, and the flow of SiH4 into the furnace was controlled at 90: 180sccm for 15min, and obtaining a first dense and uniform amorphous silicon layer with the thickness falling between 30 nm and 50nm under the conditions of low pressure and low temperature;
s4: stopping introducing special gas in the tube, evacuating, stabilizing pressure with nitrogen gas, and heating at 590 deg.C;
s5: and (3) second deposition: the temperature is stabilized at 590 ℃, the pressure is controlled at 200mTor, and the flow of SiH4 fed into the furnace is controlled at 120: 240sccm for 15min to obtain a second amorphous silicon layer with a thickness of 70-90nm under low pressure and low temperature;
s6: stopping introducing special gas in the tube, evacuating and purging, and discharging the silicon wafer tube to obtain a back structure shown in figure 1;
step six: and (2) carrying out phosphorus doping on the back amorphous silicon layer, so that the doped amorphous silicon layer and the tunneling oxide layer form a TOPCon structure after being crystallized, and due to the difference of the crystallization degrees of the two amorphous silicon layers and the number of crystal boundaries, the outer layer crystalline silicon layer has high phosphorus atom concentration, and the inner layer crystalline silicon layer has certain phosphorus concentration and simultaneously reduces the number of phosphorus atoms penetrating through the tunneling oxide layer, thereby obtaining the back structure shown in figure 2.
Example two
An excellent TOPCon battery LPCVD process mainly comprises the following steps:
the method comprises the following steps: an N-type silicon wafer is used as a substrate material, and a pyramid-shaped surface structure is generated on the surface of the silicon wafer through cleaning and texturing;
step two: carrying out boron diffusion on the front surface of the silicon wafer;
step three: carrying out BSG etching and back polishing on the silicon wafer;
step four: forming a tunneling oxide layer with the thickness of 1-2nm on the back of the silicon wafer;
step five: forming amorphous silicon layers with different densities on the tunneling oxide layer on the back surface of the silicon wafer, namely forming a first ultra-compact amorphous silicon layer and a second amorphous silicon layer on the tunneling oxide layer:
s1: putting the silicon wafer into an LPCVD furnace tube, wherein the process temperature is 590 ℃;
s2: vacuumizing, leakage detection and nitrogen purging are carried out in the furnace tube, and the furnace tube can be stabilized within a preset required pressure range in a nitrogen atmosphere;
s3: first deposition: the pressure was controlled at 200mTor, and the flow of SiH4 into the furnace was controlled at 110: 220sccm for 10min to obtain a first dense and uniform amorphous silicon layer with the thickness of 30-50nm under the conditions of low pressure and low temperature;
s4: stopping introducing special gas into the tube, evacuating, stabilizing pressure with nitrogen gas, and heating at 620 deg.C;
s5: and (3) second deposition: the temperature is stabilized at 620 ℃, the pressure is controlled at 230mTor, and the flow of SiH4 fed into the furnace is controlled at 140: 280sccm for 10min to obtain a second amorphous silicon layer with a thickness of 70-90nm under low pressure and low temperature;
s6: stopping introducing special gas in the tube, evacuating and purging, and discharging the silicon wafer tube to obtain a back structure shown in figure 1;
step six: and (2) carrying out phosphorus doping on the back amorphous silicon layer, so that the doped amorphous silicon layer and the tunneling oxide layer form a TOPCon structure after being crystallized, and due to the difference of the crystallization degrees of the two amorphous silicon layers and the number of crystal boundaries, the outer layer crystalline silicon layer has high phosphorus atom concentration, and the inner layer crystalline silicon layer has certain phosphorus concentration and simultaneously reduces the number of phosphorus atoms penetrating through the tunneling oxide layer, thereby obtaining the back structure shown in figure 2.
EXAMPLE III
An excellent TOPCon battery LPCVD process mainly comprises the following steps:
the method comprises the following steps: an N-type silicon wafer is used as a substrate material, and a pyramid-shaped surface structure is generated on the surface of the silicon wafer through cleaning and texturing;
step two: carrying out boron diffusion on the front surface of the silicon wafer;
step three: carrying out BSG etching and back polishing on the silicon wafer;
step four: forming a tunneling oxide layer with the thickness of 1-2nm on the back of the silicon wafer;
step five: forming amorphous silicon layers with different densities on the tunneling oxide layer on the back surface of the silicon wafer, namely forming a first ultra-compact amorphous silicon layer and a second amorphous silicon layer on the tunneling oxide layer:
s1: putting the silicon wafer into an LPCVD furnace tube, wherein the process temperature is 580 ℃;
s2: vacuumizing, leakage detection and nitrogen purging are carried out in the furnace tube, and the furnace tube can be stabilized within a preset required pressure range in a nitrogen atmosphere;
s3: first deposition: the pressure was controlled at 185mTor, and the flow of SiH4 through the furnace was controlled at 100: 200sccm for 12min to obtain a first dense and uniform amorphous silicon layer with a thickness of 30-50nm under low pressure and low temperature;
s4: stopping introducing special gas into the tube, evacuating, stabilizing pressure with nitrogen gas, and heating at 600 deg.C;
s5: and (3) second deposition: the temperature is stabilized at 600 ℃, the pressure is controlled at 220mTor, and the flow of SiH4 fed into the furnace is controlled at 130: 260sccm for 12min to obtain a second amorphous silicon layer with a thickness of 70-90nm under low pressure and low temperature;
s6: stopping introducing special gas in the tube, evacuating and purging, and discharging the silicon wafer tube to obtain a back structure shown in figure 1;
step six: and (2) carrying out phosphorus doping on the back amorphous silicon layer, so that the doped amorphous silicon layer and the tunneling oxide layer form a TOPCon structure after being crystallized, and due to the difference of the crystallization degrees of the two amorphous silicon layers and the number of crystal boundaries, the outer layer crystalline silicon layer has high phosphorus atom concentration, and the inner layer crystalline silicon layer has certain phosphorus concentration and simultaneously reduces the number of phosphorus atoms penetrating through the tunneling oxide layer, thereby obtaining the back structure shown in figure 2.
The present invention and its embodiments have been described above, and the description is not intended to be limiting, and the drawings are only one embodiment of the present invention, and the actual structure is not limited thereto. In summary, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A TOPCon battery LPCVD process is characterized by comprising the following steps:
the method comprises the following steps: selecting an N-type silicon wafer as a substrate material, and cleaning and texturing to generate a pyramid-shaped surface structure on the surface of the silicon wafer;
step two: carrying out boron diffusion on the front surface of the silicon wafer;
step three: carrying out BSG etching and back polishing on the silicon wafer;
step four: forming a tunneling oxide layer on the back of the silicon wafer;
step five: forming amorphous silicon on the tunneling oxide layer on the back surface of the silicon wafer;
step six: and carrying out phosphorus doping on the amorphous silicon layer on the back surface, so that the doped amorphous silicon layer and the tunneling oxide layer form a TOPCon structure after crystallization.
2. The LPCVD process for TOPCon cell as claimed in claim 1, wherein the formation of the tunnel oxide layer in step four includes: nitric acid oxidation method, thermal oxidation method or LPCVD preparation method, and the thickness of the tunneling oxide layer is 1-2 nm.
3. The LPCVD process for TOPCon cell as claimed in claim 1, wherein in step five, amorphous silicon layers with different densities are formed on the tunnel oxide layer, i.e. a first amorphous silicon layer and a second amorphous silicon layer are formed in sequence from the tunnel oxide layer.
4. A TOPCon cell LPCVD process according to claim 3, characterized in that the first amorphous silicon layer is an ultra-dense amorphous silicon layer.
5. A TOPCon cell LPCVD process according to claim 3, wherein the first amorphous silicon layer has a smaller crystalline grain size than the two amorphous silicon layers.
6. The LPCVD process for TOPCon cell as claimed in claim 1, wherein in step five, two amorphous silicon layers are formed on the tunnel oxide layer, including the following steps:
s1: putting a silicon wafer into an LPCVD furnace tube, wherein the process temperature is 560-620 ℃;
s2: the silicon chip is vacuumized, leak-proof and nitrogen purged in the furnace tube and can be stabilized within a preset required pressure range in the nitrogen atmosphere;
s3: the pressure in the silicon chip process is controlled to be 160mTor-240 mTor;
s4: in the silicon chip process, gas is introduced into a furnace mouth and a furnace in two ways, wherein the flow ratio of SiH4 is 90: 180 sccm-140: 280 sccm;
s5: in the silicon chip process, the thickness of a first layer of ultra-compact amorphous silicon layer is 30-50nm through first deposition;
s6: after a first layer of amorphous silicon of the silicon wafer is prepared, nitrogen purging and pressure and temperature adjustment are carried out;
s7: in the silicon chip process, the thickness of the second amorphous silicon layer is 70-90nm and the sum of the thicknesses of the two amorphous silicon layers is 100-140nm through the second deposition.
7. A TOPCon cell LPCVD process according to claim 6, characterized in that in the first deposition in step S5, the preparation process temperature is controlled between 560 ℃ and 590 ℃, and the process pressure is controlled between 170mTor and 200 mTor; the flow of SiH4 through the furnace was controlled at 90: 180 sccm-110: 220sccm for 10-15min to obtain a first dense and uniform amorphous silicon layer under the conditions of low pressure and low temperature.
8. A TOPCon cell LPCVD process according to claim 6, characterized in that the adjustment of step S6 includes: the introduction of special gas in the tube is stopped, after evacuation, nitrogen is used for pressure stabilization, and the temperature is set to be 590-620 ℃ for temperature rise.
9. A TOPCon cell LPCVD process according to claim 6, characterized in that in the second deposition of step S7, the preparation process temperature is controlled at 590 ℃ -620 ℃; the process pressure is controlled to be 200mTor-230 mTor; the flow of SiH4 into the furnace was controlled at 120: 240 sccm-140: 280sccm for 10-15min to obtain a second amorphous silicon layer under low pressure and low temperature conditions.
10. The LPCVD process for TOPCon battery as claimed in claim 6, wherein after completion of step S6, the tube is purged by evacuating and stopping the introduction of special gas.
CN202111029186.XA 2021-09-01 2021-09-01 TOPCon battery LPCVD (low pressure chemical vapor deposition) process Pending CN113903833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111029186.XA CN113903833A (en) 2021-09-01 2021-09-01 TOPCon battery LPCVD (low pressure chemical vapor deposition) process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111029186.XA CN113903833A (en) 2021-09-01 2021-09-01 TOPCon battery LPCVD (low pressure chemical vapor deposition) process

Publications (1)

Publication Number Publication Date
CN113903833A true CN113903833A (en) 2022-01-07

Family

ID=79188603

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111029186.XA Pending CN113903833A (en) 2021-09-01 2021-09-01 TOPCon battery LPCVD (low pressure chemical vapor deposition) process

Country Status (1)

Country Link
CN (1) CN113903833A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114649425A (en) * 2022-05-20 2022-06-21 正泰新能科技有限公司 TopCon crystalline silicon solar cell and preparation method thereof
CN115207160A (en) * 2022-07-14 2022-10-18 常州时创能源股份有限公司 Preparation method of tunneling oxide layer passivation contact structure
US11848397B1 (en) 2022-06-15 2023-12-19 Zhejiang Jinko Solar Co., Ltd. Method for preparing solar cell and solar cell, photovoltaic module

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098835A (en) * 2016-08-19 2016-11-09 山东新华联新能源科技有限公司 Heterojunction solar battery and preparation method thereof
US20200075789A1 (en) * 2016-12-12 2020-03-05 Ecole polytechnique fédérale de Lausanne (EPFL) Silicon heterojunction solar cells and methods of manufacture
CN111628050A (en) * 2020-06-11 2020-09-04 常州时创能源股份有限公司 Method for realizing electronic local passivation contact, crystalline silicon solar cell and preparation method thereof
CN111668345A (en) * 2020-06-29 2020-09-15 浙江晶科能源有限公司 Solar cell and preparation method thereof
CN112349816A (en) * 2020-11-19 2021-02-09 江苏大学 Preparation method of high-efficiency low-cost N-type TOPCon battery based on PECVD technology
DE102019122637A1 (en) * 2019-08-22 2021-02-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Process for the production of a metallic contact structure of a photovoltaic solar cell
CN112420881A (en) * 2020-11-19 2021-02-26 常州大学 Preparation method of silicon oxide and doped amorphous silicon film layer in TOPCon battery
CN113035969A (en) * 2021-02-04 2021-06-25 江苏杰太光电技术有限公司 TOPCon battery gradient doped amorphous silicon passivation structure and preparation method thereof
CN113224202A (en) * 2021-03-15 2021-08-06 浙江爱旭太阳能科技有限公司 POLO-IBC solar cell and preparation method thereof

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098835A (en) * 2016-08-19 2016-11-09 山东新华联新能源科技有限公司 Heterojunction solar battery and preparation method thereof
US20200075789A1 (en) * 2016-12-12 2020-03-05 Ecole polytechnique fédérale de Lausanne (EPFL) Silicon heterojunction solar cells and methods of manufacture
DE102019122637A1 (en) * 2019-08-22 2021-02-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Process for the production of a metallic contact structure of a photovoltaic solar cell
CN111628050A (en) * 2020-06-11 2020-09-04 常州时创能源股份有限公司 Method for realizing electronic local passivation contact, crystalline silicon solar cell and preparation method thereof
CN111668345A (en) * 2020-06-29 2020-09-15 浙江晶科能源有限公司 Solar cell and preparation method thereof
CN112349816A (en) * 2020-11-19 2021-02-09 江苏大学 Preparation method of high-efficiency low-cost N-type TOPCon battery based on PECVD technology
CN112420881A (en) * 2020-11-19 2021-02-26 常州大学 Preparation method of silicon oxide and doped amorphous silicon film layer in TOPCon battery
CN113035969A (en) * 2021-02-04 2021-06-25 江苏杰太光电技术有限公司 TOPCon battery gradient doped amorphous silicon passivation structure and preparation method thereof
CN113224202A (en) * 2021-03-15 2021-08-06 浙江爱旭太阳能科技有限公司 POLO-IBC solar cell and preparation method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114649425A (en) * 2022-05-20 2022-06-21 正泰新能科技有限公司 TopCon crystalline silicon solar cell and preparation method thereof
US11848397B1 (en) 2022-06-15 2023-12-19 Zhejiang Jinko Solar Co., Ltd. Method for preparing solar cell and solar cell, photovoltaic module
CN115207160A (en) * 2022-07-14 2022-10-18 常州时创能源股份有限公司 Preparation method of tunneling oxide layer passivation contact structure
CN115207160B (en) * 2022-07-14 2024-04-26 常州时创能源股份有限公司 Preparation method of tunneling oxide passivation contact structure

Similar Documents

Publication Publication Date Title
KR102100909B1 (en) Solar cell having an emitter region with wide bandgap semiconductor material
CN113903833A (en) TOPCon battery LPCVD (low pressure chemical vapor deposition) process
US10304972B2 (en) Solar cell with silicon oxynitride dielectric layer
JP4812147B2 (en) Manufacturing method of solar cell
Chistiakova et al. Low-temperature atomic layer deposited magnesium oxide as a passivating electron contact for c-Si-based solar cells
Tao et al. 730 mV implied Voc enabled by tunnel oxide passivated contact with PECVD grown and crystallized n+ polycrystalline Si
JP2012506629A (en) Semiconductor device manufacturing method, semiconductor device, and semiconductor device manufacturing facility
CN116666493A (en) Solar cell manufacturing method and solar cell
AU2022397987A1 (en) Method for preparing tunnel oxide layer and amorphous silicon thin film, and topcon cell
CN113488547B (en) Tunnel oxide passivation structure and manufacturing method and application thereof
CN112447867A (en) Solar cell structure and manufacturing method thereof
CN114267753A (en) TOPCon solar cell, preparation method thereof and photovoltaic module
JP2011009754A (en) Method of manufacturing solar cell
CN113808927A (en) TOPCon battery phosphorus diffusion technology
CN115692545A (en) Method for improving doping concentration of polycrystalline silicon active phosphorus of N-type TOPCon battery in PECVD route
Zhang et al. Improvement of passivation quality by post-crystallization treatments with different methods for high quality tunnel oxide passivated contact c-Si solar cells
CN113809203A (en) Preparation method of TOPCon battery structure with passivated front surface
EP4162534A1 (en) Methodology for efficient hole transport layer using transition metal oxides
JP5172993B2 (en) Method for forming texture structure and method for manufacturing solar cell
US7629236B2 (en) Method for passivating crystal silicon surfaces
CN114497245A (en) Boron-doped selective emitter, preparation method and N-type solar cell
TWI717930B (en) Silicon-based solar cell and method of manufacturing the same
Yao et al. Poly‐SiOx Passivating Contacts with Plasma‐Assisted N2O Oxidation of Silicon (PANO‐SiOx)
CN117410386B (en) Preparation method of laminated passivation structure with light trapping structure
CN114613881B (en) Solar cell, preparation method thereof and photovoltaic module

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20230113

Address after: 518000 Room 103, Building 3, Shekou Lanyuan, Nanshan District, Shenzhen, Guangdong Province

Applicant after: Ou Wenkai

Address before: 221000 Tongchuang Road West and Wuhuan Road North, high tech Zone, Xuzhou City, Jiangsu Province

Applicant before: Pule new energy technology (Xuzhou) Co.,Ltd.

TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20231207

Address after: No. 168, West Side of Kechuang Road, High-tech Industrial Development Zone, Taixing City, Taizhou City, Jiangsu Province, 225400

Applicant after: Pule New Energy Technology (Taixing) Co.,Ltd.

Address before: 518000 Room 103, Building 3, Shekou Lanyuan, Nanshan District, Shenzhen, Guangdong Province

Applicant before: Ou Wenkai