CN103972064B - Technique for inhibiting self doping of P-type impurities in epitaxial process of silicon with P-type buried layer - Google Patents
Technique for inhibiting self doping of P-type impurities in epitaxial process of silicon with P-type buried layer Download PDFInfo
- Publication number
- CN103972064B CN103972064B CN201410225224.2A CN201410225224A CN103972064B CN 103972064 B CN103972064 B CN 103972064B CN 201410225224 A CN201410225224 A CN 201410225224A CN 103972064 B CN103972064 B CN 103972064B
- Authority
- CN
- China
- Prior art keywords
- type
- buried layer
- layer
- type buried
- silicon chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 54
- 239000010703 silicon Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000012535 impurity Substances 0.000 title claims abstract description 28
- 230000008569 process Effects 0.000 title abstract description 16
- 230000002401 inhibitory effect Effects 0.000 title abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 52
- 230000006837 decompression Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 31
- 229910052796 boron Inorganic materials 0.000 claims description 31
- 238000000407 epitaxy Methods 0.000 claims description 31
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 230000003321 amplification Effects 0.000 abstract description 5
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000005429 filling process Methods 0.000 abstract 1
- 238000005457 optimization Methods 0.000 description 6
- 238000003892 spreading Methods 0.000 description 6
- 230000007480 spreading Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000000746 purification Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Thyristors (AREA)
Abstract
The invention provides a technique for inhibiting self doping of P-type impurities in an epitaxial process of silicon with a P-type buried layer. The technique comprises the following steps: providing a silicon wafer which is used as a substrate for manufacturing a semiconductor element, forming the P-type buried layer and an N-type buried layer on the surface of the silicon wafer through a filling process, and baking the silicon wafer at low temperature and under normal pressure; etching the silicon wafer at low temperature and under normal pressure, and removing damaged parts, which are generated when the P-type buried layer and the N-type buried layer are formed before, from the surface of the silicon wafer; forming a layer of intrinsic top cover layer on the surface of the silicon wafer under normal pressure; and growing an epitaxial layer on the surface of the top cover layer in a decompression environment. The technique provided by the invention can be used for inhibiting the self doping of the P-type impurities in an N-type silicon extension process with regard to a product of which the P-type impurities in the P-type buried layer are too high in concentration, so that the amplification coefficient of an element such as a horizontal PNP (Positive-Negative-Positive) tube can be increased.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, in particular it relates to one has p type buried layer
Silicon epitaxy during suppress p type impurity auto-dope technique.
Background technology
In the most ambipolar (Bipolar) integrated circuit technology, it will usually front in lining in extension (Epitaxy)
, pre-buried certain density boron buried regions (also known as BP buried regions, be a kind of p type buried layer), plays logical for device at the end
Isolation or participation making devices.During reduced pressure epitaxy, owing to boron atom (p type impurity) radius is little, easily
Escape from BP buried regions, form serious boron autodoping effect, and then cause the phosphorus buried regions on side (also known as BN
Buried regions, is a kind of n type buried layer) amplification coefficient (amplifying β) of the Semi-active suspension of top is difficult to do height.
In order to suppress the auto-dope during extension of the boron atom, outside current N-type epitaxy technique is all utilized in
On substrate, increase (intrinsic) cap layer (also known as CAP layer) forming one layer of intrinsic before prolonging, cover at this
On BP buried regions, suppress the effusion of boron atom.
Fig. 1 is to suppress outside boron auto-dope during a kind of silicon epitaxy process with boron buried regions of the prior art
Prolong the schematic flow sheet of method.As it is shown in figure 1, current conventional technological process can be described as follows:
Step S101 is first carried out, it is provided that silicon chip, as the substrate of making semiconductor device, the surface note of silicon chip
Enter to be formed with BP buried regions and BN buried regions, silicon chip is toasted in the environment of high temperature and normal pressure.This high temperature is permissible
Referring to 1150 DEG C, this normal pressure may refer to normal atmosphere.
Then perform step S102, silicon chip is etched in the environment of high temperature and normal pressure, removal silicon chip surface because of
The damage caused when before forming BP buried regions and/or BN buried regions.The concept of this high temperature and this normal pressure and above-mentioned step
Suddenly identical in S101, i.e. high temperature may refer to 1150 DEG C, and normal pressure may refer to normal atmosphere.
Then perform step S103, in the environment of decompression, form the cap layer of one layer of intrinsic in silicon chip surface.Should
Decompression may refer to 45 torr (torr).
Finally perform step S104, at the superficial growth epitaxial layer of cap layer in the environment of decompression.This decompression
Concept is identical with above-mentioned steps S103, i.e. this decompression may refer to 45 torr.
But when the boron excessive concentration of BP buried regions, conventional epitaxy technique cannot suppress certainly mixing of boron effectively
Miscellaneous, thus allow boron atom gather the top of BN layer, cause device to substrate leakage.For this reason, it may be necessary to exploitation
Plant new epitaxy technique.
Summary of the invention
The technical problem to be solved suppresses P during being to provide a kind of silicon epitaxy with p type buried layer
The technique of type impurity auto-dope, for the product of p type impurity excessive concentration in p type buried layer, in N-type silicon epitaxy
During technique, the auto-dope problem of suppression p type impurity, improves the amplification coefficient of device such as Semi-active suspension.
For solving above-mentioned technical problem, the present invention suppresses P during providing a kind of silicon epitaxy with p type buried layer
The technique of type impurity auto-dope, including step:
A. providing silicon chip, as the substrate of making semiconductor device, the surface of described silicon chip is injected and is formed with P
Type buried regions and n type buried layer, toast described silicon chip in the environment of low temperature and normal pressure；
B. described silicon chip is etched in the environment of low temperature and normal pressure, remove the surface of described silicon chip because of shape before
The damage caused when becoming described p type buried layer and described n type buried layer；
C. in the environment of normal pressure, the cap layer of one layer of intrinsic is formed in the surface of described silicon chip；And
D. in the superficial growth epitaxial layer of described cap layer in the environment of decompression.
Alternatively, in above-mentioned steps A and step B, described low temperature refers to that temperature is 1080～1120 DEG C.
Alternatively, in above-mentioned steps A, step B and step C, described normal pressure refers to that air pressure is standard atmosphere
Pressure.
Alternatively, in above-mentioned steps D, described decompression refers to that air pressure is 45～60 torr (torr).
Alternatively, described p type buried layer refers to that boron buried regions, described p type impurity refer to boron atom；Described N-type is buried
Layer refers to antimony buried regions.
Alternatively, described silicon chip is p-type doping, and its resistivity is 35～40Ohm cm.
Compared with prior art, the invention have the advantages that
The all of processing step of the present invention can realize in a monolithic epitaxial furnace, by reduce silicon chip baking and
The temperature of etching, significantly reduces the escaped quantity of p type impurity.It addition, form the pressure pattern of cap layer also
Change normal pressure into from decompression, enhance the epitaxy technique cavity purification to p type impurity so that before epitaxial growth
The p type impurity accumulating in non-p type buried layer region discharges epitaxy technique cavity, thus more effectively inhibits p-type
The auto-dope of impurity.
The present invention through optimization to epitaxy technique, horizontal above the n type buried layer of bipolar integrated circuit product
PNP pipe amplification coefficient (amplifying β) under the test electric current of 50 μ A rises to about 40 from about 20, card
The real present invention is very effective.
Accompanying drawing explanation
The above and other features of the present invention, character and advantage will be by below in conjunction with the accompanying drawings and embodiment
Description and become readily apparent from, wherein:
Fig. 1 is to suppress outside boron auto-dope during a kind of silicon epitaxy process with boron buried regions of the prior art
Prolong the schematic flow sheet of method；
Fig. 2 be one embodiment of the invention the silicon epitaxy process with p type buried layer during suppress p type impurity
The process flow diagram of auto-dope；
Fig. 3 be one embodiment of the invention the silicon epitaxy process with boron buried regions during suppress boron auto-dope
After epitaxy method is implemented, the analysis position schematic diagram to spreading resistance rate scattergram (SRP) of pure epitaxial region；
Fig. 4 be one embodiment of the invention the silicon epitaxy process with boron buried regions during suppress boron auto-dope
After epitaxy method is implemented, and the correlation curve figure of spreading resistance rate scattergram (SRP) between prior art.
Detailed description of the invention
Below in conjunction with specific embodiments and the drawings, the invention will be further described, elaborates in the following description
More details so that fully understanding the present invention, but the present invention obviously can be different from that this describes with multiple its
Its mode is implemented, those skilled in the art can in the case of intension of the present invention according to reality application feelings
Condition is made similar popularization, is deduced, the most should be with content constraints protection scope of the present invention of this specific embodiment.
Fig. 2 be one embodiment of the invention the silicon epitaxy process with p type buried layer during suppress p type impurity
The process flow diagram of auto-dope.As in figure 2 it is shown, this technological process specifically includes that
Perform step S201, it is provided that silicon chip, as the substrate (P-type substrate) making semiconductor device.This silicon
Sheet is generally p-type doping, its resistivity can be 35～40Ohm.cm (ohm. centimetre).Table at silicon chip
Face is injected and is formed with p type buried layer and n type buried layer, and this p type buried layer can be boron buried regions, and this p type impurity is permissible
It it is boron atom；And this n type buried layer can be antimony buried regions.Then silicon chip is dried in the environment of low temperature and normal pressure
Roasting.In the present embodiment, this low temperature refers to that temperature may be located at certain numerical value between 1080～1120 DEG C, example
Such as 1080 DEG C, 1090 DEG C, 1100 DEG C, 1110 DEG C or 1120 DEG C, preferably 1100 DEG C；This normal pressure refers to gas
Pressure can be normal atmosphere.
Perform step S202, silicon chip is etched in the environment of low temperature and normal pressure, remove the surface of silicon chip therefore
The damage caused when front formation p type buried layer and n type buried layer.In this step, the containing of this low temperature and this normal pressure
Justice is identical with above-mentioned steps S201, i.e. this low temperature refers to that temperature can be certain number between 1080～1120 DEG C
Value, such as 1080 DEG C, 1090 DEG C, 1100 DEG C, 1110 DEG C or 1120 DEG C, preferably 1100 DEG C；And this is normal
Pressure refers to that air pressure can be normal atmosphere.
Perform step S203, in the environment of normal pressure, form the cap layer (CAP of one layer of intrinsic in the surface of silicon chip
Layer).In this step, the implication of this normal pressure is identical with above-mentioned steps S201, S202, i.e. this normal pressure refers to
Air pressure can be normal atmosphere.
Perform step S204, in the environment of decompression in the superficial growth epitaxial layer of cap layer (generally outside N-type
Prolong layer).In the present embodiment, this decompression refers to that air pressure can be certain numerical value between 45～60 torr (torr),
Such as 45 torr, 50 torr, 55 torr or 60 torr.
Fig. 3 be one embodiment of the invention the silicon epitaxy process with boron buried regions (p type buried layer) during suppress
After the epitaxy method of boron (p type impurity) auto-dope is implemented, spreading resistance rate scattergram (SRP) to pure epitaxial region
Analysis position schematic diagram.Fig. 4 is the silicon epitaxy with boron buried regions (p type buried layer) of one embodiment of the invention
After the epitaxy method suppressing boron (p type impurity) auto-dope in technical process is implemented, and the expansion between prior art
The correlation curve figure of exhibition resistivity scattergram (SRP).It should be noted that these accompanying drawings are all only used as example,
It is not to draw according to the condition of equal proportion, and should be in this, as the protection to actual requirement of the present invention
Scope is construed as limiting.
Incorporated by reference to shown in Fig. 3 and Fig. 4, after the optimization of the epitaxy technique of the present invention, pure to epitaxial wafer
The spreading resistance rate scattergram of epitaxial region (i.e. without BP buried regions and the region of BN buried regions below epitaxial layer) (SRP,
Spreading Resistivity Profile) from the point of view of, after optimization, effective epitaxial thickness of (present invention) epitaxial layer is more excellent
Before change, (prior art) adds about 2.7 microns, and the autodoping effect after PN junction has disappeared, such as Fig. 4 institute
Show.
Specifically, the spreading resistance rate distribution curve of the prior art before optimization has bright after the position that PN saves
Aobvious recessed phenomenon (i.e. resistivity diminishes rapidly, illustrates that conductive capability increases), this is due in BP buried regions
Boron (p type impurity), before epitaxial growth, escapes from BP buried regions and accumulates in non-BP buried region, extension
After growth, this part of boron is just sandwiched between epitaxial layer and substrate.Owing to substrate (silicon chip) is generally p-type (35
～40 ohmcms), thus result in the recessed of distribution curve.Along with high temperature epitaxy is carried out, this part of boron to
External diffusion, further results in epitaxial layer effective thickness and reduces (concave region as in Fig. 4).
The temperature that due to the fact that hydrogen chloride (HCL) gas etching silicon chip after optimization reduces, and makes the effusion of boron
Amount reduces (being difficult to run out of), adds normal pressure and forms the cap layer purification to process cavity, makes extension foreset
Gather the boron in non-BP buried region and discharge extension cavity, thus distribution curve becomes more mild, eliminates recessed
Phenomenon.
In sum, all of processing step of the present invention can realize in a monolithic epitaxial furnace, by reducing
Silicon chip baking and the temperature of etching, significantly reduce the escaped quantity of p type impurity.It addition, form cap layer
Gas pressure pattern also changes normal pressure into from decompression, enhances the epitaxy technique cavity purification to p type impurity so that
The p type impurity accumulating in non-p type buried layer region before epitaxial growth discharges epitaxy technique cavity, thus more effectively
Inhibit the auto-dope of p type impurity.
The present invention through optimization to epitaxy technique, horizontal above the n type buried layer of bipolar integrated circuit product
PNP pipe amplification coefficient (amplifying β) under the test electric current of 50 μ A rises to about 40 from about 20, card
The real present invention is very effective.
Although the present invention is open as above with preferred embodiment, but it is not for limiting the present invention, any ability
Field technique personnel without departing from the spirit and scope of the present invention, can make possible variation and amendment.Therefore,
Every content without departing from technical solution of the present invention, according to appointing that above example is made by the technical spirit of the present invention
What amendment, equivalent variations and modification, within each falling within the protection domain that the claims in the present invention are defined.
Claims (3)
1. the technique suppressing p type impurity auto-dope during there is the silicon epitaxy of p type buried layer, including step:
A. providing silicon chip, as the substrate of making semiconductor device, the surface of described silicon chip is injected and is formed with p type buried layer and n type buried layer, is toasted by described silicon chip in the environment of low temperature and normal pressure；
B. described silicon chip is etched in the environment of low temperature and normal pressure, remove the surface of described silicon chip because of the damage caused when forming described p type buried layer and described n type buried layer before；
C. in the environment of normal pressure, the cap layer of one layer of intrinsic is formed in the surface of described silicon chip；And
D. in the superficial growth epitaxial layer of described cap layer in the environment of decompression；
Wherein, described low temperature refers to that temperature is 1080 ~ 1120 DEG C；Described normal pressure refers to that air pressure is normal atmosphere；Described decompression refers to that air pressure is 45 ~ 60 torr.
Technique the most according to claim 1, it is characterised in that described p type buried layer refers to that boron buried regions, described p type impurity refer to boron atom；Described n type buried layer refers to antimony buried regions.
Technique the most according to claim 2, it is characterised in that described silicon chip is p-type doping, and its resistivity is 35 ~ 40 Ohm cm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410225224.2A CN103972064B (en) | 2014-05-26 | 2014-05-26 | Technique for inhibiting self doping of P-type impurities in epitaxial process of silicon with P-type buried layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410225224.2A CN103972064B (en) | 2014-05-26 | 2014-05-26 | Technique for inhibiting self doping of P-type impurities in epitaxial process of silicon with P-type buried layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103972064A CN103972064A (en) | 2014-08-06 |
| CN103972064B true CN103972064B (en) | 2017-01-11 |
Family
ID=51241430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410225224.2A Active CN103972064B (en) | 2014-05-26 | 2014-05-26 | Technique for inhibiting self doping of P-type impurities in epitaxial process of silicon with P-type buried layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103972064B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101599462A (en) * | 2009-06-13 | 2009-12-09 | 无锡中微爱芯电子有限公司 | Production method of high and low voltage devices based on thin epitaxy |
| CN101976680A (en) * | 2010-09-16 | 2011-02-16 | 中国电子科技集团公司第二十四研究所 | Semiconductor structure for increasing integration density of high-voltage integrated circuit device and manufacturing method |
| CN102013392A (en) * | 2009-09-04 | 2011-04-13 | 中芯国际集成电路制造(上海)有限公司 | Forming method of diffusion zone |
| WO2012028024A1 (en) * | 2010-08-31 | 2012-03-08 | 中国科学院上海微系统与信息技术研究所 | Epitaxial growth method of restraining the self-doping effect effectively |
| CN102453958A (en) * | 2010-10-21 | 2012-05-16 | 上海华虹Nec电子有限公司 | Method for reducing epitaxy auto-doping effect |
| CN102737970A (en) * | 2011-04-01 | 2012-10-17 | 无锡华润上华半导体有限公司 | Semiconductor device and manufacturing method for gate dielectric layer thereof |
| CN202772141U (en) * | 2012-09-27 | 2013-03-06 | 无锡华润矽科微电子有限公司 | Bipolar integrated circuit structure with realization of Schottky diode function |
| CN102969316A (en) * | 2012-11-20 | 2013-03-13 | 电子科技大学 | Single-particle radiation resistant MOSFET device and preparation method thereof |
| CN102969349A (en) * | 2011-09-01 | 2013-03-13 | 上海华虹Nec电子有限公司 | Transverse parasitic plug-and-play (PNP) device in SiGe heterojunction bipolar transistor (HBT) technique and production method |
| CN103681315A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Method for forming buried layer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7468537B2 (en) * | 2004-12-15 | 2008-12-23 | Texas Instruments Incorporated | Drain extended PMOS transistors and methods for making the same |
-
2014
- 2014-05-26 CN CN201410225224.2A patent/CN103972064B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101599462A (en) * | 2009-06-13 | 2009-12-09 | 无锡中微爱芯电子有限公司 | Production method of high and low voltage devices based on thin epitaxy |
| CN102013392A (en) * | 2009-09-04 | 2011-04-13 | 中芯国际集成电路制造(上海)有限公司 | Forming method of diffusion zone |
| WO2012028024A1 (en) * | 2010-08-31 | 2012-03-08 | 中国科学院上海微系统与信息技术研究所 | Epitaxial growth method of restraining the self-doping effect effectively |
| CN101976680A (en) * | 2010-09-16 | 2011-02-16 | 中国电子科技集团公司第二十四研究所 | Semiconductor structure for increasing integration density of high-voltage integrated circuit device and manufacturing method |
| CN102453958A (en) * | 2010-10-21 | 2012-05-16 | 上海华虹Nec电子有限公司 | Method for reducing epitaxy auto-doping effect |
| CN102737970A (en) * | 2011-04-01 | 2012-10-17 | 无锡华润上华半导体有限公司 | Semiconductor device and manufacturing method for gate dielectric layer thereof |
| CN102969349A (en) * | 2011-09-01 | 2013-03-13 | 上海华虹Nec电子有限公司 | Transverse parasitic plug-and-play (PNP) device in SiGe heterojunction bipolar transistor (HBT) technique and production method |
| CN103681315A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Method for forming buried layer |
| CN202772141U (en) * | 2012-09-27 | 2013-03-06 | 无锡华润矽科微电子有限公司 | Bipolar integrated circuit structure with realization of Schottky diode function |
| CN102969316A (en) * | 2012-11-20 | 2013-03-13 | 电子科技大学 | Single-particle radiation resistant MOSFET device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103972064A (en) | 2014-08-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100957796B1 (en) | Low-voltage punch-through bi-directional transient-voltage suppression devices having surface breakdown protection and methods of making the same | |
| CN105280631B (en) | Transient voltage suppressing element and its manufacture method | |
| KR100879337B1 (en) | Low-voltage punch-through bi-directional transient-voltage suppression devices and methods of making the same | |
| CN104112653B (en) | Preparation method of self-compensation back-sealing semiconductor substrate | |
| JP6266485B2 (en) | Semiconductor device | |
| KR20070118659A (en) | Asymmetric bidirectional transient voltage suppressor and method of forming same | |
| US20080003782A1 (en) | Multilayer gettering structure for semiconductor device and method | |
| CN103972064B (en) | Technique for inhibiting self doping of P-type impurities in epitaxial process of silicon with P-type buried layer | |
| US20170110537A1 (en) | Deep trench isolation structures and systems and methods including the same | |
| CN105810583B (en) | The manufacturing method of landscape insulation bar double-pole-type transistor | |
| CN106298510A (en) | Groove-shaped packet routing device and manufacture method thereof | |
| CN107316863A (en) | Transient Voltage Suppressor and preparation method thereof | |
| CN103426879A (en) | Transient voltage suppressor and manufacturing method thereof | |
| CN107305839A (en) | The method for preventing autodoping effect | |
| CN106298511A (en) | The manufacture method of Transient Suppression Diode and Transient Suppression Diode | |
| KR20090017074A (en) | Method for deposition epitaxial silicon layer | |
| CN102376548A (en) | Method for reducing auto-doping and external diffusion in epitaxial process | |
| JPS61125012A (en) | Epitaxial wafer | |
| CN113838747A (en) | Semiconductor device with epitaxial layer and manufacturing method thereof | |
| KR100981793B1 (en) | Low-voltage transient-voltage supression devices having bi-directional breakedown protection and manufacturing method thereby | |
| TW201436172A (en) | Semiconductor structure, method for forming the same and method for suppressing hot cluster | |
| Gan et al. | npn array yield improvement in a 0.18-μm deep trench SiGe BiCMOS process | |
| CN107611011A (en) | A kind of bilayer mask technique of inhibition of self-doped | |
| CN104576334A (en) | Integrated manufacturing method for NPN devices with different BVCBOs | |
| CN104517835A (en) | Back surface technology of field cut-off type insulated gate bipolar transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |